Next Article in Journal
Nanogroove-Enhanced Hydrogel Scaffolds for 3D Neuronal Cell Culture: An Easy Access Brain-on-Chip Model
Next Article in Special Issue
Selective Growth and Contact Gap-Fill of Low Resistivity Si via Microwave Plasma-Enhanced CVD
Previous Article in Journal
Molecular Dynamics Simulations on the Demolding Process for Nanostructures with Different Aspect Ratios in Injection Molding
Previous Article in Special Issue
Thermomagnetic Convection of Ferrofluid in an Enclosure Channel with an Internal Magnetic Field
Open AccessArticle

Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory

1
Department of Electrical, Electronic and Control Engineering and IITC, Hankyong National University, 327 Jungang-ro, Anseong-si, Gyenggi-do 17579, Korea
2
Group for Nano-Photonics Convergence Technology, Korea Institute of Industrial Technology, Gwangju 500-480, Korea
3
School of Electrical and Computer Engineering, Georgia Institute of Technology, Atlanta, GA 30308, USA
*
Author to whom correspondence should be addressed.
Micromachines 2019, 10(10), 637; https://doi.org/10.3390/mi10100637
Received: 2 August 2019 / Revised: 17 September 2019 / Accepted: 20 September 2019 / Published: 23 September 2019
(This article belongs to the Special Issue NANO KOREA 2019)
In order to simulate a circuit by applying various logic circuits and full chip using the HSPICE model, which can consider electrical coupling proposed in the previous research, it is investigated whether additional electrical coupling other than electrical coupling by top and bottom layer exists. Additional electrical coupling were verified through device simulation and confirmed to be blocked by heavily doped source/drain. Comparing the HSPICE circuit simulation results using the newly proposed monolithic 3D NAND (M3DNAND) structure in the technology computer-aided design (TCAD) mixed-mode and monolithic 3D inverter (M3DINV) unit cell model was once more verified. It is possible to simulate various logic circuits using the previously proposed M3DINV unit cell model. We simulated the operation and performances of M3DNAND, M3DNOR, 2 × 1 multiplexer (MUX), D flip-flop (D-FF), and static random access memry (SRAM). View Full-Text
Keywords: circuit simulation; electrical coupling; monolithic 3D integrated circuit (IC); parameter extraction circuit simulation; electrical coupling; monolithic 3D integrated circuit (IC); parameter extraction
Show Figures

Figure 1

MDPI and ACS Style

Ahn, T.J.; Choi, B.H.; Lim, S.K.; Yu, Y.S. Electrical Coupling and Simulation of Monolithic 3D Logic Circuits and Static Random Access Memory. Micromachines 2019, 10, 637.

Show more citation formats Show less citations formats
Note that from the first issue of 2016, MDPI journals use article numbers instead of page numbers. See further details here.

Article Access Map by Country/Region

1
Back to TopTop