# Study on Modulation Strategy of Electronic Converters Based on Improved D-NPC Topology for Full Electric Vehicle

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## Abstract

**:**

## 1. Introduction

## 2. D-NPC and ID-NPC Topology Converter and Loss Allocation Analysis

#### 2.1. Traditional D-NPC (Diode Neutral-Point-Clamped) Topology

_{dc/2}in series, and the neutral point of the DC source is connected with the neutral point of the series diode. Taking the first group of main bridge arms as an example, when the first element T

_{11}and the second element T

_{12}of the four elements of main bridge arms are connected, the output voltage is V

_{dc/2}(called the positive-level state); when the second element T

_{12}is connected with the third element T

_{13}, the output voltage is 0 (called the zero-level state); when the third element T

_{13}is connected with the fourth element T

_{14}, the output voltage is −V

_{dc/2}(called the negative-level state). Four controllable switching elements turn on in turn to make the output present the three-level state. In the process of switching from the positive-level state to the zero-level state and from the zero-level state to the negative-level state, the second and third elements are in a repeated conduction state, that is, a continuous state, and the heat distribution on the single device is uneven [13,14]. Since each bridge arm has four elements, each element needs one driving circuit, and a set of converters needs 12 driving circuits [15,16].

#### 2.2. D-NPC (Diode Neutral-Point-Clamped) Switching States

#### 2.3. ID-NPC (Improved Diode Neutral-Point-Clamped) Topology

_{11}and T

_{12}, T

_{13}and T

_{14}, and T

_{15}and T

_{16}, and the driving ports are G

_{11}, G

_{13}, and G

_{15}, respectively. When the driving port G

_{11}is connected, the output voltage is V

_{dc/2}(positive state); when the driving port G

_{15}is connected, the output voltage is 0 (zero state); when the driving port G

_{13}is connected, the output voltage is −V

_{dc/2}(negative state). Three groups of switching elements turn on to make the output voltage present the three-level state. During switching states, the positive state, zero state, and negative state are completed by independent components, with no overlapping, meaning the heat distribution is uniform. The three groups of elements need three driving circuits, and the converter needs nine driving circuits.

#### 2.4. ID-NPC (Improved Diode Neutral-Point-Clamped) Switching States

#### 2.5. Analysis of D-NPC (Diode Neutral-Point-Clamped) Switching Loss

_{11}turns off and D

_{17}turns on, and T

_{12}bears the half-wave phase current in the whole switching process. In the case of maximum modulation M, T

_{11}has on-loss at the beginning of switching and current loss at the end of switching. D

_{17}has smaller conduction loss and self-loss after conduction. The solid line represents the current path direction in the “+” state, the dotted line represents the current path direction in the “0” state, and the thickness of the solid line and the dotted line represents the duty cycle.

_{12}and T

_{13}have switching losses. After switching to the “−” state, the reverse diodes D

_{13}and D

_{14}are connected in series, and the two are on after switching, with negligible switching loss. When the state switches from “−” to “0” states, D

_{14}or D

_{13}has reverse recovery loss. T

_{12}needs to turn the current on and off in the “0” to “−” states and bears a large on and off loss. When the reverse recovery loss occurs in D

_{14}, the loss scale for D

_{14}and T

_{12}also depends on the duty cycle of both. When the lower current is reversed, for T

_{14}, the internal switch and diode have loss, and the two also have an obvious junction temperature in the same housing.

_{17}has a negligible turn-on loss, directional recovery loss, and large duty cycle turn-on loss.

_{17}and T

_{12}have a current most of the time. T

_{12}has conduction and turn-off loss. Due to the large duty cycle, the conduction loss is also large. D

_{13}and D

_{14}also bear reverse recovery losses when off.

#### 2.6. Analysis of ID-NPC (Improved Diode Neutral-Point-Clamped) Switching Loss

_{11}and T

_{12}switch with D

_{17}and T

_{15}. T

_{11}and T

_{12}are off and bear the turn-off loss. The mechanism is the same when opening, and the two pipes bear the turn-on loss. T

_{15}bears the conduction loss. After conduction, T

_{15}bears the half-wave phase current. The solid line represents the current path in the “+” state, the dotted line represents the current path in the “0” state, the thickness of the solid line and the dotted line indicates the duty cycle, and the arrow direction is the current direction. Compared with the type D1 switching loss in Figure 3, the circuit switching has one more on–off loss.

_{15}is off, then D

_{17}is off, and after the dead time, T

_{13}and T

_{14}are on. On the contrary, D

_{13}and D

_{16}or D

_{14}bear large reverse recovery loss. T

_{15}needs to turn the conduction current on and off when switching and bears the on–off loss. Due to the different duty cycles, for D

_{13}and D

_{16}, D

_{14}and T

_{15}, and D

_{17}, the loss is different.

_{11}and T

_{12}turn off, and T

_{15}turns on. In the switching process, T

_{11}and T

_{12}have on and off losses. Different from D3, T

_{15}has on and off losses. Due to the different duty cycles, the conduction loss is also different.

_{14}is connected in series with D

_{13}and D

_{16}, the three diodes conduct at the same time when they are on, and there are reverse recovery losses when they are off.

#### 2.7. Comparison and Analysis

- The ID-NPC topology only needs nine driving circuits.
- ID-NPC has two more elements per phase, and six more elements in three phases.
- The ID-NPC topology has more switching loss in no-load switching.
- The additional switching elements of ID-NPC can evenly distribute the heat generated by switching loss, and the heat distribution is relatively more uniform.
- ID-NPC can run in the two-level state, when G
_{12}is zero (take the U-phase as an example). This is very suitable for the field of zero speed in the power drive system, and the characteristic is that the regulation system is low, and the frequency output is zero or near zero. - In the ID-NPC topology, because the zero level is realized by independent components, although the switching loss is increased, the heat dissipation can be dispersed, and the switching frequency can be increased.

## 3. Three-Level and Two-Level Modulation Conversion Strategy Based on ID-NPC

#### 3.1. I-TL (Improved Two-Level) Topology

_{13}, G

_{23}, and G

_{33}are on, and the reverse current flows into the zero potential through T

_{13}and D

_{18}, T

_{23}and D

_{28}, and T

_{33}and D

_{38}, which increases the return path and reduces the impact of the reverse current on the on–off components.

#### 3.2. Region Order Algorithm

#### 3.3. Optimization of Vector Action Time

_{1}, U

_{2}, and U

_{3}, and some simple transformation can be conducted. Take the vector composition in the ($0-\pi /3$) region as an example, as shown in Figure 12.

_{1}, U

_{2}, and U

_{3}, in Equation (2), the region of the reference voltage vector is determined. Then, by using the look-up table in the FPGA (field-programmable gate array), the action time of the basic voltage vector in the corresponding region can be obtained, and the relationship between the action time and the vector in the region is obtained, as shown in Table 7. In the table, K = 1.732T

_{s}/V

_{dc}, where V

_{dc}represents the DC bus voltage.

_{1}, U

_{2}, U

_{3}, and ${\mathrm{U}}_{\mathsf{\alpha}}$, ${\mathrm{U}}_{\mathsf{\beta}}$ is derived from ${\mathrm{U}}_{\mathrm{m}}\mathrm{cos}\left(\mathsf{\omega}\mathrm{t}\right)$ and ${\mathrm{U}}_{\mathrm{m}}\mathrm{sin}\left(\mathsf{\omega}\mathrm{t}\right)$. For PMSM, the rotation vector does not need to be judged on which sector it is located in but can rotate sequentially counterclockwise or clockwise. Therefore, the RAM allocation value is used to directly express the sector action time. Equation (3) can be obtained:

_{s}/V

_{dc}.

#### 3.4. Three–Two- and Two–Three-Level Modulation Conversion Strategy Based on Loss Allocation and Fault Tolerance

## 4. Simulation Analysis

#### 4.1. Simulation Comparison Based on Two Two-Level Topologies

_{ac}and U

_{bc}voltage waveforms, respectively, and Uac2 and Ubc2 are the improved two-level U

_{ac}and U

_{bc}waveforms, respectively. Additionally, the x-axis is in seconds, and the y-axis is in volts.

#### 4.2. Simulation Analysis of Three-Level and Two-Level Modulation Conversion Strategies

_{ac}and U

_{bc}are in volts. The simulation time is one second, and when the time is at 0.5 s, the level converts from three-level to two level or two-level to three-level. It can be seen from the below two figures that the voltage fluctuation is small, which indicates that the conversion influence is relatively small.

_{ac}and U

_{bc}simulation waveforms of the whole process are shown in Figure 17. The simulation time is 1.5 s. At 0.5 s, two-level (6.1 Hz) converts to three-level (48.8 Hz), and at 1.0 s, three-level (48.8 Hz) converts to two-level (6.1 Hz) until it stops. The feasibility of the three-level and two-level modulation conversion strategies based on loss allocation and fault tolerance is verified. The units of U

_{ac}and U

_{bc}are in volts.

## 5. Experimental Analysis

#### 5.1. Experimental Comparison Based on Two Two-Level Topologies

_{ac}and U

_{bc}voltage waveforms, respectively, and 3 and 4 are the improved two-level U

_{ac}and U

_{bc}waveforms, respectively. The experimental waveform is basically consistent with the simulation waveform.

#### 5.2. Experimental Analysis of Three-Level and Two-Level Modulation Conversion Strategies

_{ac}voltage waveform, and 2 is the U

_{bc}waveform.

## 6. Summary

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

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Topological Structure | Two-Level | D-NPC | A-NPC | T-NPC |
---|---|---|---|---|

Number of IGBT | 2 | 4 | 6 | 4 |

Number of driving paths | 2 | 4 | 6 | 4 |

Number of diodes | 2 | 6 | 6 | 4 |

Device withstand voltage | V_{dc} | V_{dc/2} | V_{dc/2} | Horizontal switch: V_{dc/2}Vertical switch: V _{dc} |

Control difficulty | Easy | More difficult | Most difficult | More difficult |

Withstand voltage | No | Capacitance | Capacitance | Capacitance |

Output level | 2 | 3 | 3 | 3 |

Conduction loss | Minimum | Large | Large | Maximum |

Switching loss | Large | Low | Low | Maximum |

Heat distribution | Balance | Imbalance | Algorithmic balance | Balance |

Switching | G_{11} | G_{12} | G_{13} | G_{14} |
---|---|---|---|---|

“+” | 1 | 1 | 0 | 0 |

“0” | 0 | 1 | 1 | 0 |

“−” | 0 | 0 | 1 | 1 |

Switching | G_{11} | G_{15} | G_{13} |
---|---|---|---|

“+” | 1 | 0 | 0 |

“0” | 0 | 1 | 0 |

“−” | 0 | 0 | 1 |

α | M | T | State | T_{11} | D_{11} | T_{12} | D_{12} | T_{13} | D_{13} | T_{14} | D_{14} | T_{15} | D_{15} | T_{16} | D_{16} | D_{17} | D_{18} |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|

+1 | 1.15 | D1 | “+”⟷“0” | √ | ○ | ○ | |||||||||||

−1 | 0 | D2 | “0”⟷“−” | √ | ○ | ○ | ○ | ○ | √ | ||||||||

+1 | 1.15 | D3 | “+”⟷“0” | √ | ○ | ○ | |||||||||||

−1 | 0 | D4 | “0”⟷“−” | √ | ○ | ○ | ○ | ○ | √ |

α | M | T | State | T_{11} | D_{11} | T_{12} | D_{12} | T_{13} | D_{13} | T_{14} | D_{14} | T_{15} | D_{15} | T_{16} | D_{16} | D_{17} | D_{18} |
---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|

+1 | 1.15 | D1 | “+”⟷“0” | √ | √ | ○ | ○ | ○ | |||||||||

−1 | 0 | D2 | “0”⟷“−” | ○ | ○ | ○ | ○ | √ | √ | ○ | √ | ||||||

+1 | 1.15 | D3 | “+”⟷“0” | √ | √ | ○ | ○ | ○ | |||||||||

−1 | 0 | D4 | “0”⟷“−” | ○ | ○ | ○ | ○ | √ | √ | ○ | √ |

**Table 6.**Corresponding relationship of sector, basic vector, αβ coordinate system region order, and RAM.

Sector | Basic Vector | $\mathsf{\alpha}\mathsf{\beta}\mathbf{Coordinate}\mathbf{System}\mathbf{Region}\mathbf{Order}$ | RAM |
---|---|---|---|

III | T4, T6 | $0-\pi /3$ | 1–683 |

I | T6, T2 | $\pi /3-2\pi /3$ | 684–1366 |

V | T2, T3 | $2\pi /3-3\pi /3$ | 1367–2048 |

IV | T3, T1 | $3\pi /3-4\pi /3$ | 2049–2731 |

VI | T1, T5 | $4\pi /3-5\pi /3$ | 2732–3414 |

II | T5, T4 | $5\pi /3-6\pi /3$ | 3415–4096 |

Order | T_{i} | T_{j} | T_{0} |
---|---|---|---|

($0-\pi /3$)(T4, T6) | ${\mathrm{T}}_{4}=\mathrm{K}\times {\mathrm{U}}_{2}$ | ${\mathrm{T}}_{6}=\mathrm{K}\times {\mathrm{U}}_{1}$ | ${\mathrm{T}}_{0}={\mathrm{T}}_{\mathrm{s}}-{\mathrm{T}}_{4}-{\mathrm{T}}_{6}$ |

($\pi /3-2\pi /3$)(T6, T2) | ${\mathrm{T}}_{6}=\mathrm{K}\times -{\mathrm{U}}_{3}$ | ${\mathrm{T}}_{2}=\mathrm{K}\times -{\mathrm{U}}_{2}$ | ${\mathrm{T}}_{0}={\mathrm{T}}_{\mathrm{s}}-{\mathrm{T}}_{6}-{\mathrm{T}}_{2}$ |

$\left(2\pi /3-3\pi /3\right)$(T2, T3) | ${\mathrm{T}}_{2}=\mathrm{K}\times {\mathrm{U}}_{1}$ | ${\mathrm{T}}_{3}=\mathrm{K}\times {\mathrm{U}}_{3}$ | ${\mathrm{T}}_{0}={\mathrm{T}}_{\mathrm{s}}-{\mathrm{T}}_{2}-{\mathrm{T}}_{3}$ |

$\left(3\pi /3-4\pi /3\right)$(T3, T1) | ${\mathrm{T}}_{3}=\mathrm{K}\times -{\mathrm{U}}_{2}$ | ${\mathrm{T}}_{1}=\mathrm{K}\times -{\mathrm{U}}_{1}$ | ${\mathrm{T}}_{0}={\mathrm{T}}_{\mathrm{s}}-{\mathrm{T}}_{3}-{\mathrm{T}}_{1}$ |

$\left(4\pi /3-5\pi /3\right)$(T1, T5) | ${\mathrm{T}}_{1}=\mathrm{K}\times {\mathrm{U}}_{3}$ | ${\mathrm{T}}_{5}=\mathrm{K}\times {\mathrm{U}}_{2}$ | ${\mathrm{T}}_{0}={\mathrm{T}}_{\mathrm{s}}-{\mathrm{T}}_{1}-{\mathrm{T}}_{5}$ |

$\left(5\pi /3-6\pi /3\right)$(T5, T4) | ${\mathrm{T}}_{4}=\mathrm{K}\times {\mathrm{U}}_{1}$ | ${\mathrm{T}}_{4}=\mathrm{K}\times {\mathrm{U}}_{2}$ | ${\mathrm{T}}_{0}={\mathrm{T}}_{\mathrm{s}}-{\mathrm{T}}_{5}-{\mathrm{T}}_{4}$ |

Order | T_{i} | T_{j} | T_{0} |
---|---|---|---|

RAM value | 1–683 | 1–683 | 1–683 |

($0-1/3\mathsf{\pi}$)(T4, T6) | ${\mathrm{T}}_{4}=\mathrm{K}\times \left(\mathrm{C}-\mathrm{D}\right)$ | ${\mathrm{T}}_{6}=\mathrm{K}\times 2\mathrm{C}$ | ${\mathrm{T}}_{0}={\mathrm{T}}_{\mathrm{s}}-{\mathrm{T}}_{4}-{\mathrm{T}}_{6}$ |

RAM value | 684–1366 | 684–1366 | 684–1366 |

($1/3\mathsf{\pi}-2/3\mathsf{\pi}$)(T6, T2) | ${\mathrm{T}}_{6}=\mathrm{K}\times \left(\mathrm{C}+\mathrm{D}\right)$ | ${\mathrm{T}}_{2}=\mathrm{K}\times \left(\mathrm{D}-\mathrm{C}\right)$ | ${\mathrm{T}}_{0}={\mathrm{T}}_{\mathrm{s}}-{\mathrm{T}}_{6}-{\mathrm{T}}_{2}$ |

RAM value | 1367–2048 | 1367–2048 | 1367–2048 |

($2/3\mathsf{\pi}-3/3\mathsf{\pi}$)(T2, T3) | ${\mathrm{T}}_{2}=\mathrm{K}\times 2\mathrm{C}$ | ${\mathrm{T}}_{3}=\mathrm{K}\times -\left(\mathrm{C}+\mathrm{D}\right)$ | ${\mathrm{T}}_{0}={\mathrm{T}}_{\mathrm{s}}-{\mathrm{T}}_{2}-{\mathrm{T}}_{3}$ |

RAM value | 2049–2731 | 2049–2731 | 2049–2731 |

($3/3\mathsf{\pi}-4/3\mathsf{\pi}$)(T3, T1) | ${\mathrm{T}}_{3}=\mathrm{K}\times \left(\mathrm{D}-\mathrm{C}\right)$ | ${\mathrm{T}}_{1}=\mathrm{K}\times -2\mathrm{C}$ | ${\mathrm{T}}_{0}={\mathrm{T}}_{\mathrm{s}}-{\mathrm{T}}_{3}-{\mathrm{T}}_{1}$ |

RAM value | 2732–3414 | 2732–3414 | 2732–3414 |

($4/3\mathsf{\pi}-5/3\mathsf{\pi}$)(T1, T5) | ${\mathrm{T}}_{1}=\mathrm{K}\times -\left(\mathrm{C}+\mathrm{D}\right)$ | ${\mathrm{T}}_{5}=\mathrm{K}\times \left(\mathrm{C}-\mathrm{D}\right)$ | ${\mathrm{T}}_{0}={\mathrm{T}}_{\mathrm{s}}-{\mathrm{T}}_{1}-{\mathrm{T}}_{5}$ |

RAM value | 3415–4096 | 3415–4096 | 3415–4096 |

($5/3\mathsf{\pi}-6/3\mathsf{\pi})$(T5, T4) | ${\mathrm{T}}_{5}=\mathrm{K}\times 2\mathrm{C}$ | ${\mathrm{T}}_{4}=\mathrm{K}\times \left(\mathrm{C}-\mathrm{D}\right)$ | ${\mathrm{T}}_{0}={\mathrm{T}}_{\mathrm{s}}-{\mathrm{T}}_{5}-{\mathrm{T}}_{4}$ |

Name | DC Voltage | $\mathbf{Sampling}\mathbf{Frequency}$ | $\mathbf{Simulation}\mathbf{Time}$ | $\mathbf{Modulation}\mathbf{Frequency}$ |
---|---|---|---|---|

Value | 30 V | 10$\mathrm{kHz}$ | $1\mathrm{s}$ | $48.8\mathrm{Hz}$ |

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**MDPI and ACS Style**

Cao, Y.; Zhang, X.; Liu, X.; Ma, Y.
Study on Modulation Strategy of Electronic Converters Based on Improved D-NPC Topology for Full Electric Vehicle. *World Electr. Veh. J.* **2021**, *12*, 80.
https://doi.org/10.3390/wevj12020080

**AMA Style**

Cao Y, Zhang X, Liu X, Ma Y.
Study on Modulation Strategy of Electronic Converters Based on Improved D-NPC Topology for Full Electric Vehicle. *World Electric Vehicle Journal*. 2021; 12(2):80.
https://doi.org/10.3390/wevj12020080

**Chicago/Turabian Style**

Cao, Yonglei, Xiaodong Zhang, Xiang Liu, and Yuling Ma.
2021. "Study on Modulation Strategy of Electronic Converters Based on Improved D-NPC Topology for Full Electric Vehicle" *World Electric Vehicle Journal* 12, no. 2: 80.
https://doi.org/10.3390/wevj12020080