An Abnormal Increase in Switching Frequency in Multi-Sources Line Commutated Converter and Suppression Method

Abstract

Distinct from the traditional Modular Multilevel Converter (MMC) which focuses on fundamental frequency operation, the Static Var and Filter (SVF) within the Multi-Source Line-Commutated Converter (SLCC) system is tasked with the core function of high-frequency harmonic filtering. This paper reveals a unique engineering reliability issue stemming from this functional difference: to satisfy the Nyquist sampling theorem for precise tracking and elimination of high-frequency harmonics, the update frequency of the capacitor voltage balancing algorithm in the SLCC-SVF system is forced to increase significantly. Mathematical modeling and quantitative analysis demonstrate that this strong coupling between harmonic tracking demands and the voltage sorting strategy directly drives an abnormal surge in the average switching frequency (reaching over five times that of the fundamental condition), severely threatening device safety. To address this, an optimized adaptive hybrid modulation strategy is proposed. The system operates under Nearest Level Modulation (NLM) in normal conditions and automatically transitions to Carrier Phase-Shifted PWM (CPS-PWM)—leveraging its closed-loop balancing capability—when switching frequency or junction temperature exceeds safety thresholds. Furthermore, a non-integer frequency ratio optimization theory for low-modulation indices is constructed specifically for SVF conditions to prevent low-frequency oscillations. PLECS simulation results validate the theoretical analysis, showing that the proposed strategy effectively reduces the average switching frequency by approximately 20% under complex harmonic conditions, significantly enhancing thermal stability and operational reliability while guaranteeing filtering performance.

1. Introduction

Driven by the “dual-carbon” goals, the exponential growth of wind and photovoltaic power has necessitated robust cross-regional transmission capabilities. Due to their high capacity and long-distance efficiency, line-commutated converter-based high-voltage direct current (LCC-HVDC) systems have been widely adopted. To further enhance large-scale power transmission and improve power quality, the multi-Source Line-Commutated Converter (SLCC) system, formed by integrating a Static Var and Filter (SVF) on the converter side, has emerged as a pivotal technological direction [1,2]. Notably, Reference [3] proposed a novel SLCC composite structure by connecting an SVF in parallel with the LCC. This scheme fundamentally leverages the high-frequency switching characteristics and active filtering capability of the SVF. By modulating turn-off power electronic devices at high frequencies, the SVF detects harmonic components in real time and generates compensating currents equal in magnitude and opposite in phase, thereby achieving precise suppression of characteristic harmonics. As demonstrated by the Jiangsu Yangzhou-Zhenjiang HVDC project (±200 kV/1200 MW), this topology not only simplifies filter configuration and minimizes spatial footprint but also significantly reduces Total Harmonic Distortion (THD) on the AC side while enhancing voltage stability. Consequently, it offers a promising technical solution for ensuring the secure and high-quality operation of the grid amidst the large-scale integration of renewable energy.

However, submodule capacitor voltage imbalance remains an inherent challenge in SVF systems, primarily induced by parameter variations, switching harmonics, and grid distortions [4,5]. To maintain voltage equilibrium, sorting-based balancing strategies are widely utilized for their rapid response and adaptability [6,7,8]. Although these strategies regulate energy throughput by adjusting submodule switching states [9], the frequent dynamic adjustments disrupt switching signal sequences, inevitably causing a surge in switching frequency and increased system losses [10]. Recent research has revealed the underlying mechanisms: sorting algorithms introduce redundant switching transitions [11]; high-frequency modulation methods (e.g., NLM) inherently amplify frequency issues [12]; and parameter deviations combined with grid distortions trigger frequent balancing actions, forming a vicious cycle [13]. Crucially, most existing studies focus solely on fundamental frequency conditions, overlooking the critical impact of harmonics on switching frequency. This places traditional strategies in a dilemma between maintaining voltage balance and suppressing switching frequency.

To mitigate excessive switching frequency, existing research has primarily focused on reducing redundant switching actions and optimizing modulation strategies. In terms of reducing switching actions, Reference [14] suggests setting voltage thresholds to limit the frequency of balancing triggers, while Reference [15] suppresses mode transitions by constraining the number of inserted submodules. Regarding modulation optimization, Reference [16] proposes switching from Carrier Phase-Shifted PWM (CPS-PWM) to Reduced Switching Space Vector (RSSV) modulation. However, these methods suffer from distinct limitations: threshold-based approaches are sensitive to parameter variations; alternative modulation strategies may lead to uneven power distribution or voltage deviations; and insertion limit methods can result in uneven thermal stress distribution.

To further optimize the trade-off between performance and efficiency, hybrid modulation strategies have emerged as a research hotspot. References [17,18] improved steady-state performance through modified CPS-PWM and fractional-level modulation, respectively. Reference [19] proposed the NHPWM method, which flexibly allocates modes but relies on offline settings. Overall, most existing strategies rely on static parameters and lack closed-loop interaction with real-time system states. Most critically, previous studies have not sufficiently explored the mechanism by which harmonic filtering conditions induce switching frequency fluctuations, a key factor affecting the stable operation of SLCC systems.

Addressing these deficiencies, based on the SLCC-SVF system architecture using the Nearest Level Modulation (NLM) strategy, this paper focuses on the impact of harmonic filtering on switching frequency and proposes corresponding optimization strategies. The main contributions are as follows:

(1)

Mechanism Revelation and Risk Quantification: This study reveals that harmonic filtering in SLCC-SVF systems forces the balancing frequency to rise to satisfy the Nyquist theorem, causing the average switching frequency to surge to over five times that of the fundamental condition (MMC operating condition), posing a unique reliability risk.

(2)

Mathematical Modeling and Theoretical Analysis: A mathematical model is established to quantify the strong coupling relationship between the number of inserted submodules and the redistribution of switching signals, providing a theoretical basis for analyzing frequency anomalies.

(3)

Adaptive Strategy and Parameter-Core Closed Loop: An adaptive hybrid modulation strategy based on a junction temperature criterion is proposed to achieve active thermal management. Furthermore, a non-integer modulation frequency ratio optimization theory is constructed to suppress low-frequency oscillations, deepening the solution from a macro-strategy to a micro-parameter core to form a complete closed-loop control system.

2. Modulation and Voltage Balancing Strategy in the SLCC-SVF System

2.1. Topology of the SLCC-SVF System

The SLCC-SVF system is tailored for high-power, long-distance transmission applications. Its core advantage lies in a complementary functional allocation: the LCC facilitates bulk power transfer with high voltage capacity and low losses, while the SVF provides rapid reactive power compensation and harmonic suppression. Within this architecture, the LCC manages active power transmission and commutation, whereas the SVF utilizes high-frequency fully controllable switches to inject dynamic reactive power and mitigate characteristic harmonics, ensuring power quality compliance at the inverter AC side [20,21,22].

Distinct from the Modular Multilevel Converter (MMC), which focuses on multilevel voltage synthesis, the SLCC-SVF adopts a parallel cooperative operation principle where “the LCC dominates energy transfer while the SVF secures power quality”. This integrated design internalizes harmonic management and reactive support within the converter station, significantly reducing the reliance on external passive filters and enhancing voltage stability and dynamic response during grid disturbances.

As illustrated in Figure 1, the SLCC topology features a cascaded H-bridge SVF connected in parallel between the converter transformer and the LCC valve group [17]. Each SVF phase comprises N_sub series-connected full-bridge submodules. In this configuration, active power flow is governed by the LCC, while the SVF supplies the necessary reactive power and generates compensating currents—equal in magnitude but opposite in phase to the harmonic currents—to ensure that AC-side grid current distortion remains within regulatory limits.

In Figure 1, L_s represents the grid-side inductance, L_f denotes the DC-filter inductance, and L_a, L_b, L_c are the arm inductors of the three SVF phases. The variables u_s and U_dc correspond to the AC grid voltage and DC-link voltage, respectively. Regarding the currents, i_s, i_f, and i_LCC refer to the AC input current, filter branch current, and LCC current, while i_a, i_b, i_c denote the three-phase arm currents. The SVF employs a three-phase cascaded H-bridge topology, with each phase comprising N_sub series-connected full-bridge submodules (SMs). These SMs are indexed as SM_a1 … SM_aN, SM_b1 … SM_bN, and SM_c1 … SM_cN based on their phase and position. Each full-bridge SM consists of four power switches (VT₁–VT₄) with anti-parallel diodes (VD₁–VD₄), and the capacitor voltage of each SM is denoted by u_c. The LCC current i_LCC is expressed as follows:

$$\left\{\begin{array}{l}{i}_{\mathrm{LCC}}={\displaystyle \sum _{n=1}^{\infty }\sqrt{2}{I}_{\left(n\right)}\sin (n\omega t+{\phi }_n)}\\ I_{\left(n\right)}={\displaystyle \frac{I_d}{n}},n=6\mathrm{k}\pm 1\end{array}\right.$$

(1)

In Equation (1), I_(n), φ_n, and I_d represent the RMS value of the nth harmonic current, its phase angle, and the DC current, respectively. ω represents the fundamental angular frequency. Based on the arm current i_j (j ∈ {a,b,c}), two capacitor voltage insertion modes are defined: the positive insertion mode (S₁__i) and the negative insertion mode (S₂__i). Specifically, in the positive insertion mode, the current i_j conducts through the VT₁/VD₂ path, resulting in a positive output polarity of the capacitor voltage. Conversely, in the negative insertion mode, the current flows through VT₃/VD₄, producing a negative output polarity.

2.2. NLM Strategy and a Sorting Algorithm—Based Voltage Balancing Strategy

The Nearest Level Modulation (NLM) strategy approximates the reference voltage using a finite number of discrete levels. Consequently, the output voltage exhibits a staircase waveform, remaining constant within each level and undergoing step changes only when the reference crosses a quantization threshold. Specifically, at these crossing instants, the total number of inserted submodules must be updated to track the reference.

However, when the capacitor voltage sorting-based balancing algorithm is active, the selection of which specific submodules to insert or bypass is jointly determined by the sorting results and the arm current polarity. This process redistributes the switching actions—originally dictated solely by level transitions—among the various submodules. This redistribution frequently causes specific submodules to undergo repeated switching within short periods, resulting in a transient surge in the equivalent switching frequency [23,24,25].

In this study, the NLM strategy is employed to calculate the required number of inserted submodules, denoted as m_in. The detailed process is described as follows

$$\left\{\begin{array}{l}{m}_{\mathrm{in}\_\mathrm{norm}}={\displaystyle \frac{U_{\mathrm{ref}}}{u_{\mathrm{c}}}}\\ m_{\mathrm{in}}=\mathrm{round}(m_{\mathrm{in}\_\mathrm{norm}})\end{array}\right.$$

(2)

As defined in Equation (2), m_in__norm represents the normalized reference value, where U_ref denotes the submodule reference voltage, u_c is the actual capacitor voltage, and round (·) indicates the rounding function. Consequently, when the calculated integer m_in > 0, m_in submodules are inserted to generate a positive voltage level. Conversely, when m_in < 0, the number of inserted submodules is ∣m_in∣, resulting in a negative voltage output.

Furthermore, a sorting-based voltage balancing strategy is employed in the SLCC-SVF system to maintain capacitor voltage balance. The implementation of this strategy is depicted in Figure 2, which comprises four sequential steps:

(a)

Step 1: The required number of inserted submodules, denoted as m_in, is determined based on the NLM strategy.

(b)

Step 2: The capacitor voltages u_c are sorted (e.g., in ascending or descending order), yielding the sorting rank R__sort.

(c)

Step 3: The polarity of the arm current i_j is detected.

(d)

Step 4: The final gate switching signals are synthesized by integrating the results from the previous steps.

Upon completion of these four steps, the system enters an idle state and waits for the next computational cycle. It is worth noting that the sorting update rate is constrained by communication bandwidth and data frame length—a limitation that will be utilized in the subsequent frequency boundary analysis.

2.3. Distribution Metrics of Driving Signals: Instantaneous Switching Frequency f_inst and Average Switching Frequency f_avg

When the sorting-based voltage balancing strategy is integrated into an NLM-controlled SLCC-SVF system, the distribution of gate driving signals is no longer determined solely by the number of inserted submodules, m_in. Instead, it depends heavily on the dynamic variation in m_in and the resulting sorting rank, R__sort, during the balancing process.

To illustrate this, this analysis considers Phase A with four full-bridge submodules (N_sub = 4) as an example. Assume the capacitor voltages are sorted in the order u_{c_SMa4} > u_{c_SMa3} > u_{c_SMa2} > u_{c_SMa1}, and the arm current is positive (i_a > 0). If m_in gradually sweeps from 0 to +4 (for positive output) or to −4 (for negative output), the resulting switching state distribution—determined purely by the basic NLM logic—is shown in Figure 3a.

However, once the balancing strategy is enabled, the system dynamically assigns specific submodules to positive or negative insertion modes based on the arm current direction i_a and the sorting result R__sort to maintain voltage balance. Consequently, the driving signals for individual submodules are reshuffled, leading to the redistributed switching pattern illustrated in Figure 3b.

Figure 3a illustrates the switching signals for the four submodules generated directly by the NLM strategy. These signals exhibit a piecewise-constant behavior, maintaining a fixed output state until a level transition is required. Unlike the uniformly distributed pulses of CPS-PWM, the switching instants in NLM are determined solely by the voltage level requirements, independent of a fixed phase relationship. Consequently, the switching frequency is minimal; for instance, submodule SM1 changes its switching state only once per fundamental cycle (or switching period T_s).

To implement the voltage balancing strategy, the controller (Step 1) first calculates the required number of inserted submodules, m_in, using the NLM scheme. This value determines whether the full-bridge submodules operate in positive or negative output mode. As shown in the time-domain waveform in Figure 4, m_in exhibits a characteristic staircase profile: it oscillates between 0 and 1 at low voltage demands, transitions to 1–2 and 2–3 as demand rises, and reaches 3 or 4 at the peak.

Subsequently, based on m_in, the sorting-based balancing strategy (Step 4) generates the final gate signals, as depicted in Figure 3b. This process redistributes the switching actions dictated by m_in across different submodules. As a result, a single submodule may undergo multiple switching actions within one period T_s. For example, the waveform for SM₁ in Figure 3b reveals eight switching events in a single cycle, a sharp contrast to the minimal switching seen in the NLM-only case.

Crucially, this analysis demonstrates that the voltage balancing strategy induces a highly uneven distribution of switching signals. Even with constant capacitor voltages and a fixed sorting rank R__sort, the switching states of individual devices can vary significantly between periods. This phenomenon challenges the assertion in reference [5] that “minor capacitor voltage fluctuations are the primary cause of sharp rises in switching frequency”. Instead, it suggests that the redistribution mechanism itself is the driver. Thus, relying on a single frequency metric is insufficient to fully characterize this behavior.

To address this, two metrics are defined to evaluate the switching characteristics: the instantaneous switching frequency (f_inst), defined as the reciprocal of the time interval between two consecutive switching events, and the average switching frequency (f_avg), which calculates the mean number of switching events over a specified duration. The following section analyzes the impact of the voltage balancing strategy on these two metrics.

3. Mechanism of Switching Frequency Variation in SLCC-SVF Under Voltage Balancing Strategy and Harmonic Filtering Effects

With the introduction of the voltage balancing strategy, the instantaneous and average switching frequencies (f_inst, f_avg) of the submodules are no longer static; instead, they become dependent on multiple interacting factors. Specifically, these factors include the system’s fundamental switching frequency f_s, the number of inserted submodules m_in, and the real-time capacitor voltage sorting rank R__sort. Given that f_s is constant, the subsequent analysis focuses on the variation patterns of m_in and R__sort, as well as the impact of the balancing strategy’s update frequency, f_balance.

3.1. Definition: Variation Frequency of Inserted Submodules, Update Frequency of Capacitor Voltage Sorting and Voltage Balancing Frequency

The variation pattern of min is deterministic. As illustrated in Figure 4, it varies periodically within the range of 0 to 4. Extending this analysis to a general case with N_sub submodules, the amplitude range and step levels of the m_in reference will scale accordingly, while the fundamental periodic behavior remains unchanged. Consequently, its variation period T_m and variation frequency f_m can be expressed as follows:

$$\left\{\begin{array}{l}{T}_{\mathrm{m}}={\displaystyle \frac{T_{\mathrm{s}}}{N_{\mathrm{sub}}}}\\ f_{\mathrm{m}}={\displaystyle \frac{1}{T_{\mathrm{m}}}}=N_{\mathrm{sub}}{f}_{\mathrm{s}}\end{array}\right.$$

(3)

As indicated in Equation (3), the variation frequency f_m of m_in significantly exceeds the nominal switching frequency f_s and is directly proportional to the number of submodules, N_sub. In practical operation, the continuous fluctuation of capacitor voltages necessitates frequent updates to the sorting rank, R__sort. However, the attainable update rate is physically constrained by the digital control chain, encompassing sampling, quantization, and transmission. Among these, the communication bandwidth between the central controller and local submodule controllers serves as the primary bottleneck.

Defining f_{R_sort} as the update frequency, T_{R_sort} as the update period, and DaTa as the data frame length per submodule, the master-slave communication bandwidth BW must satisfy the following condition to ensure real-time sorting synchronization:

$$BW\ge Data\times f_{\mathrm{R}\_\mathrm{sort}}\times N_{\mathrm{sub}}$$

(4)

Given that the maximum physical layer transmission bandwidth is limited to 100 Mbit/s, the upper bound of the sorting update frequency, f_{R_sort}, can be derived from this bandwidth constraint as follows:

$$f_{\mathrm{R}\_\mathrm{sort}}\le {\displaystyle \frac{BW}{Data\times N_{\mathrm{sub}}}}\approx {\displaystyle \frac{1920}{N_{\mathrm{sub}}}}\mathrm{kHz}$$

(5)

As indicated in Equation (5), the update frequency of the voltage sorting rank, f_{R_sort}, is inversely proportional to the number of submodules, N_sub, in the arm. Consequently, when N_sub is large, the upper limit of f_{R_sort} is restricted to the order of hundreds or even merely tens of Hz. This implies that under the bandwidth-constrained balancing technique, the sorting rank can only be refreshed at a relatively low frequency.

Furthermore, since the sorting update frequency fundamentally dictates the balancing control loop, we define f_{R_sort} as the equivalent voltage balancing frequency, denoted as f_balance.

3.2. Range of the Instantaneous Switching Frequency f_inst Under Voltage Balancing Strategy

Building upon the analysis of the variation frequency f_m (for m_in) and the sorting update frequency f_{R_sort} in Section 3.1, the range of the instantaneous switching frequency f_inst can be further characterized. Specifically, depending on the quantitative relationship between the variation period T_m and the update period T_{R_sort} (or its corresponding frequency f_{R_sort}), three distinct cases are distinguished as follows:

(1)

Value of Instantaneous Switching Frequency Under Changing Insertion Count with Unchanged Sorting Result

When T_m < T_{R_sort} (i.e., f_m > f_{R_sort}), it can be assumed that m_in varies while the sorting rank R__sort remains effectively constant. For the following analysis, assume the capacitor voltages in the phase arm are sorted in descending order: u_{c_SM1} > u_{c_SM2} > u_{c_SM3} > … > u_{c_SMN}, and the arm current i_j remains positive (i_j > 0).

As illustrated in Figure 5, m_in exhibits periodic variation, fluctuating between N_k and N_k + 2 in the first interval, and between N_k and N_k + 3 in the second. According to the balancing strategy (Step 4), when the insertion command is m_in = N_k, a total of N_k submodules—specifically those indexed from N_sub − N_k + 1 to N_sub—are inserted. These submodules operate in either the positive (S₁) or negative (S₂) insertion mode.

During the first interval, the submodules indexed from N_sub − N_k + 1 to N_sub remain clamped in state S₁, while those from 1 to N_sub − N_k − 1 remain in state S₂. Consequently, the only submodule undergoing state transitions is SM_Nsub−Nk, which toggles between S₁ and S₂ in synchronization with m_in as it alternates between N_k and N_k + 1. Therefore, submodule SM_Nsub−Nk exhibits the highest instantaneous switching frequency, f_inst, which can be expressed as:

$$\max (f_{\mathrm{inst}})=f_{\mathrm{m}}=N_{\mathrm{sub}}{f}_{\mathrm{s}}$$

(6)

(2)

Value of Instantaneous Switching Frequency Under Unchanged Insertion Count with Changing Sorting Result

When T_m ≫ T_{R_sort} (i.e., f_m ≪ f_{R_sort}), m_in is treated as quasi-static (constant), while R__sort is considered the dominant variable. To determine the maximum instantaneous switching frequency f_inst, we analyze the worst-case scenario by considering two extreme capacitor voltage sorting ranks: R__sort 1 (descending order, u_{c_SM1} > u_{c_SM2} > u_{c_SM3} > … > u_{c_SMN}), and R__sort 2 (ascending order, u_{c_SM1} < u_{c_SM2} < u_{c_SM3} < … < u_{c_SMN}). Assume that the sorting rank alternates between R__sort 1 and R__sort 2 at the update frequency f_{R_sort}, resulting in a full oscillation cycle of 2 T_{R_sort}. Throughout this process, the arm current i_j remains positive, and m_in is held constant at N_k. The resulting driving signal waveforms for the different submodules under these conditions are illustrated in Figure 6.

Consequently, based on this variation pattern, the maximum value of f_inst can be expressed as:

$$\max (f_{\mathrm{inst}})={\displaystyle \frac{f_{\mathrm{R}\_\mathrm{sort}}}{2}}$$

(7)

(3)

Value of Instantaneous Switching Frequency Under Simultaneous Changes in Insertion Count and Sorting Result

As illustrated in Figure 7, the maximum value of f_inst occurs within the time interval T_d defined as the duration between the first and second transitions. Given that T_d is significantly smaller than both T_m and T_{R_sort}, the resulting instantaneous frequency can reach an extremely high magnitude—far surpassing both N_subf_s and f_{R_sort}. This maximum frequency is expressed as:

$$\max (f_{\mathrm{inst}})>>\max ({\displaystyle \frac{1}{T_{\mathrm{m}}}}, {\displaystyle \frac{1}{T_{\mathrm{R}\_\mathrm{sort}}}})=\max (N_{\mathrm{sub}}{f}_{\mathrm{s}}, {\displaystyle \frac{f_{\mathrm{R}\_\mathrm{sort}}}{2}})$$

(8)

3.3. Range of the Average Switching Frequency f_avg Under Voltage Balancing Strategy

(1)

Value of the Average Switching Frequency Under Changing Insertion Count with Unchanged Sorting Result

In this scenario, only a single submodule undergoes one switching action per period, while the remaining submodules maintain their switching states. Based on the preceding analysis, the total number of switching events, denoted as ΣS_c, for the N_sub submodules over a one-second interval can be expressed as:

$${{\displaystyle \sum S}}_{\mathrm{c}}=1\times {\displaystyle \frac{1}{T_{\mathrm{m}}}}=N_{\mathrm{sub}}{f}_{\mathrm{s}}$$

(9)

The average switching frequency f_avg can then be expressed as:

$$f_{\mathrm{avg}}={\displaystyle \frac{{\displaystyle \sum S_{\mathrm{c}}}}{N_{\mathrm{sub}}}}=f_{\mathrm{s}}$$

(10)

(2)

Value of the Average Switching Frequency Under Simultaneous Changes in Insertion Count and Sorting Result

As illustrated in Figure 6a, when N_k < (N_sub + 1)/2, the maximum total of additional switching actions for the N_sub submodules is 2N_k. Conversely, as shown in Figure 6b, when N_k > (N_sub + 1)/2, this total amounts to 2 (N_sub − N_k).

In the worst-case scenario where N_k = N_sub/2, every submodule undergoes a single state transition, resulting in a total of N_sub additional switching actions. Consequently, the maximum average switching frequency, f_avg, is given by:

$$\max (f_{\mathrm{avg}})={\displaystyle \frac{1}{N_{\mathrm{sub}}}}(N_{\mathrm{sub}}{f}_{\mathrm{s}}+N_{\mathrm{sub}}\times {\displaystyle \frac{1}{2T_{\mathrm{R}\_\mathrm{sort}}}})=f_{\mathrm{s}}+{\displaystyle \frac{f_{\mathrm{R}\_\mathrm{sort}}}{2}}$$

(11)

3.4. Values of Instantaneous and Average Switching Frequency Under Harmonic Filtering Effects

The primary function of the SVF is to “synthesize compensatory currents on demand”. This entails providing adjustable reactive power at the fundamental frequency while simultaneously generating compensating currents of equal magnitude and opposite phase at specific harmonic frequencies (e.g., the 3rd harmonic). According to the Nyquist-Shannon sampling theorem, accurately injecting a harmonic current requires the underlying control process to operate at a sufficient sampling rate. In this system, the capacitor voltage sorting update frequency, f_{R_sort}, serves as this effective sampling rate. As established in Section 3.1, f_{R_sort} is identical to the balancing frequency, f_balance. Therefore, to accurately reconstruct the harmonic signal f_h and avoid aliasing, the balancing frequency f_balance must be no less than twice the harmonic frequency f_h. Consequently, the maximum value of f_balance can be expressed as:

$$f_{\mathrm{balance}}\ge 2f_{\mathrm{h}}$$

(12)

Therefore, referring to Equations (8) and (11), the maximum instantaneous and average switching frequencies (f_inst and f_avg) are given by:

$$\left\{\begin{array}{l}\max (f_{\mathrm{inst}})>>\max (N_{\mathrm{sub}}{f}_{\mathrm{s}}, {\displaystyle \frac{f_{\mathrm{balance}}}{2}})\\ \max (f_{\mathrm{avg}})=f_{\mathrm{s}}+{\displaystyle \frac{f_{\mathrm{balance}}}{2}}\end{array}\right.$$

(13)

As indicated by Equation (12), tracking a higher harmonic frequency f_h necessitates a corresponding increase in the balancing frequency f_balance. Specifically, to effectively mitigate harmonics in the 300–500 Hz range, f_balance must be elevated to the order of several kHz (e.g., 2000–3000 Hz). Failure to meet this criterion compromises the system’s ability to accurately track harmonic variations, leading to voltage waveform distortion and degraded filtering performance—phenomena that are particularly pronounced under high harmonic frequencies or severe grid voltage distortion.

Crucially, as demonstrated by Equation (13) and Figure 8, increasing f_balance inevitably drives up both the instantaneous and average switching frequencies (f_inst and f_avg), This direct correlation explains the abnormal surge in switching frequency observed during harmonic filtering operations in the SLCC system.

Therefore, the schematic diagram illustrating the abnormal increase in the switching frequency of the SLCC is shown in Figure 9.

As shown in Figure 9, in the SLCC-SVF system, to achieve harmonic suppression, the SVF needs to inject high-frequency compensation current. According to the Nyquist sampling theorem, this requires that the update frequency of the capacitor voltage sequence (i.e., the equalization frequency f_balance) as the basis of the control loop must be high enough (at least twice the harmonic frequency). However, when this high-frequency update of the sequence update (the update of R_{_sort}) is in close temporal proximity or overlaps with the change in the number of insertion submodules (m_in) determined by the recent level modulation (NLM), it will cause the switching state of a specific sub-module to be repeatedly redistributed within an extremely short period of time, thereby triggering abnormal spikes in the instantaneous switching frequency (f_inst). At the same time, increasing fbalance itself will directly push up the average switching frequency (_favg).

The above theoretical analysis indicates that the harmonic suppression function of SVF, by forcing the uniform pressure frequency f_balance to track high-frequency harmonics, is the fundamental reason for the order-of-magnitude increase in the switching frequency (compared to the base wave condition). To visually demonstrate the above mechanism and separately quantify the specific amplitude of the frequency surge under different operating conditions, Section 5 will be verified and analyzed through high-precision simulations.

4. Limitation Methods and Optimal Generation Strategies for SLCC-SVF Switching Frequency Under Voltage Balancing and Harmonic Filtering Effects

The theoretical analysis in Section 3 reveals that under the influence of the voltage balancing strategy and harmonic injection, the maximum instantaneous switching frequency f_inst can significantly exceed both f_balance/2 and N_subf_s. In contrast, the maximum average switching frequency f_avg is primarily governed by the fundamental frequency f_s and the balancing frequency f_balance (where f_balance = f_{R_sort}). Consequently, effectively limiting these two frequency metrics necessitates distinct control approaches.

4.1. Limitation Method for the Instantaneous Switching Frequency f_inst

Based on the analysis in Section 3.2 and Section 3.4, the critical factor in limiting the instantaneous switching frequency f_inst is the prevention of extreme values caused by concurrent variations in m_in and R_{_sort}. Since these variations are driven by the balancing frequency (f_balance = f_{R_sort}), it is essential to constrain f_{R_sort}.

To address this, this study proposes a synchronized update method designed to eliminate sharp spikes in f_inst. The core principle is to trigger a logical update of R__sort exclusively when m_in changes, thereby synchronizing the sorting update rate with the step changes in m_in. Consequently, the driving signals for the specific submodules involved in transitions switch only when R__sort updates, ensuring a minimum switching interval of T_m. This effectively clamps the maximum f_inst at N_subf_s, avoiding excessive instantaneous frequency surges.

4.2. Limitation Method for the Average Switching Frequency f_avg

According to the analysis in Section 3.3 and Section 3.4, reducing f_balance effectively limits the magnitude of f_avg. Given that f_balance = f_{R_sort}, restricting f_{R_sort} l serves as a direct method to suppress f_avg. While Equation (5) indicates that f_{R_sort} has an upper bound imposed by the communication bandwidth, this section focuses on its lower bound. If f_{R_sort} falls below this critical threshold, the sorting rank R__sort cannot be updated at a sufficient rate. Under such restricted frequency conditions, specific submodules may remain prolonged in the positive insertion mode, leading to continuous capacitor charging. Consequently, the capacitor voltage may diverge, eventually violating the allowable voltage ripple constraints, as illustrated in Figure 10.

Based on the preceding analysis, the lower limit of f_{R_sort} is governed by the maximum permissible voltage fluctuation of the submodule capacitors. Consequently, the capacitor voltage increment Δu_c accumulated over a single update interval T_{R_sort} can be expressed as:

$$\Delta u_{\mathrm{c}}={\displaystyle \frac{1}{C}}{\displaystyle {\int }_{t_{\mathrm{charge}1}}^{t_{\mathrm{charge}2}}{i}_j}dt$$

(14)

Here, t_charge1 and t_charge2 denote the start and end instants of the charging interval, respectively, and their difference defines the charging duration T_{R_sort}. In the worst-case scenario, the submodule remains clamped in the positive insertion mode throughout the entire T_{R_sort} period, during which the arm current i_j continuously charges the capacitor. Furthermore, this charging process is assumed to be centered symmetrically around the peak current instant t_peak.

As illustrated in Figure 10, t_peak corresponds toT₀/2. Leveraging the temporal relationships among t_charge1, t_charge2, and t_peak, Equation (14) can be reformulated as:

$$\Delta u_{\mathrm{c}}\le {\displaystyle \frac{1}{C}}{\displaystyle {\int }_{t_{\mathrm{peak}}-\frac{T_{\mathrm{R}\_\mathrm{sort}}}{2}}^{t_{\mathrm{peak}}+\frac{T_{\mathrm{R}\_\mathrm{sort}}}{2}}{i}_j}dt$$

(15)

The maximum capacitor voltage increment Δu_c per submodule is given by:

$$\begin{array}{cc}\max (\Delta u_{\mathrm{c}})& ={\displaystyle \frac{1}{C}}{\displaystyle {\int }_{t_{\mathrm{peak}}-\frac{T_{\mathrm{R}\_\mathrm{sort}}}{2}}^{t_{\mathrm{peak}}+\frac{T_{\mathrm{R}\_\mathrm{sort}}}{2}}\frac{I_{\mathrm{s}}}{2}(\frac{M}{2}-\cos {\omega }_{0}t)}dt\\ & ={\displaystyle \frac{I_{\mathrm{s}}}{8C}}[T_{\mathrm{R}\_\mathrm{sort}}+{\displaystyle \frac{4}{\pi f_0}}\sin (\pi f_0{T}_{\mathrm{R}\_\mathrm{sort}})]\\ & \approx {\displaystyle \frac{5I_{\mathrm{s}}}{8C{f}_{\mathrm{R}\_\mathrm{sort}}}}\end{array}$$

(16)

As demonstrated in Equation (16), the maximum voltage increment Δu_c is directly dependent on f_{R_sort}. Given that typical engineering specifications mandate that the capacitor voltage ripple be maintained within 10% of the nominal value, the lower bound of f_{R_sort} can be expressed as:

$$f_{\mathrm{R}\_\mathrm{sort}}>{\displaystyle \frac{1}{T_{\mathrm{R}\_\mathrm{sort}}}}=6.25{\displaystyle \frac{N_{\mathrm{sub}}{I}_{\mathrm{s}}}{C{U}_{\mathrm{dc}}}}$$

(17)

As indicated in Equation (17), the lower bound of f_{R_sort} scales inversely with the DC-link voltage and the submodule capacitance, while scaling directly with the number of submodules. Consequently, configuring f_{R_sort} close to this theoretical lower limit—and setting f_balance accordingly—serves as an effective strategy to minimize f_avg.

4.3. Optimized Generation Strategy for Submodule Driving Signals

As established in previous sections, the maximum values of both f_inst and f_avg are inherently coupled with the fundamental switching frequency f_s; therefore, reducing f_s offers a direct pathway to suppress them. However, simply lowering f_s would inevitably increase harmonic distortion in the AC-side current and degrade power quality. Furthermore, the sorting-based voltage balancing strategy tends to result in an uneven distribution of driving signals among submodules.

To address these challenges, we propose an optimized submodule gate driving strategy. This approach is designed to mitigate high switching frequencies and improve signal distribution by dynamically switching the modulation scheme within the SVF system. Under normal operating conditions, the system employs Nearest Level Modulation (NLM) combined with a sorting-based balancing control. However, when specific submodules exceed frequency or temperature safety limits, the system transitions to the Carrier Phase-Shifted PWM (CPS-PWM) scheme, leveraging its built-in closed-loop voltage balancing capability for rapid regulation. Crucially, to ensure the efficacy of this mode, we provide a comprehensive parameter design methodology specifically for low Frequency Ratio (FR) CPS-PWM applications in SVF. We established that the FR must be set to a non-integer value with a theoretically optimized fractional part ε (e.g., minimizing f_h (2 + ε)). Recommended values, such as 2.35 or 3.35, are proven to effectively prevent low-frequency fluctuations, continuous drift, and capacitor voltage unbalance. This optimization resolves the traditional trade-off between high losses and poor waveform quality; it allows for operation at a low FR—crucial for minimizing switching losses and controlling junction temperature—while fundamentally suppressing frequency reduction effects and low-frequency harmonics, thereby guaranteeing both system stability and harmonic performance.

The decision to switch modes is governed by a weighted composite evaluation index, which combines switching frequency and junction temperature with weighting factors of 0.7 and 0.3, respectively. The transition of the driving signal generation module is triggered when this index exceeds a predefined threshold. The detailed optimization process is illustrated in Figure 11 and proceeds as follows:

(a)

Parameter Initialization and Data Acquisition: The system generates capacitor voltage references for each submodule and distributes them to both the NLM and CPS-PWM modules. Simultaneously, it acquires the real-time switching frequency (f_real) and junction temperature (T_real) of all submodules for threshold assessment.

(b)

Adaptive Signal Generation: During normal operation, driving signals are generated via NLM with sorting-based balancing, where the sorting rank R__sort dynamically optimizes the insertion priority. However, if the comprehensive evaluation metric W of a specific submodule exceeds Threshold 1, the system switches that submodule’s control to the CPS-PWM scheme. This mode utilizes phase-shifted carriers and closed-loop balancing to rapidly regulate voltage and mitigate the abnormal stress state.

The comprehensive evaluation metric W for threshold detection is defined as follows:

$$W=0.7{\displaystyle \frac{f_{\mathrm{real}}}{f\max }}+0.3{\displaystyle \frac{T_{\mathrm{real}}}{T_{\max }}}$$

(18)

where f_max and T_max are predefined safety thresholds.

(c)

Threshold Monitoring and Switching Logic: The system continuously computes the comprehensive evaluation metric W for each submodule in real time. Upon detecting W > 1, the system determines that this sub-module is in an abnormal stress condition (due to excessive switching frequency or high temperature). The controller immediately initiates a handover, shifting the submodule’s modulation source to the CPS-PWM scheme. To prevent chattering, the system reverts to the NLM-based strategy only after W returns to the normal range (W ≤ 1) and remains stable for a predefined hysteresis period. The hysteresis cycle is set to 10 fundamental wave cycles, corresponding to a 50 Hz system, which is approximately 0.2 s. This real-time decision-making is implemented via digital comparators, obviating the need for complex computational overhead.

(d)

Driving Signal Gating and Output: The gating unit arbitrates the output signals based on the threshold assessment. For submodules operating within normal limits (W ≤ 1), signals from the NLM-based balancing strategy are passed; for submodules exceeding the threshold (W > 1), signals from the CPS-PWM scheme are engaged. The gating logic is designed to ensure seamless switching between the two modulation sources, effectively eliminating transient disturbances during mode transitions.

5. Simulation

This section details the simulation studies conducted on the PLECS platform to validate the effectiveness of the proposed strategy. The simulation parameters in this article are all based on the engineering design standards for the project in Yangzhou and Zhenjiang, Jiangsu Province, China. The key parameters of the SLCC-SVF system are configured as follows: DC-link voltage U_dc = 200 kV, AC voltage U_s = 230 kV, rated output power P = 12,000 MW, arm inductance L_arm = 150 mH, submodule capacitance C_sm = 13 mF, fundamental frequency f = 50 Hz, and number of submodules per arm N_sub = 72. To comprehensively evaluate the system performance, simulations were carried out under two distinct operating scenarios: one without SVF harmonic filtering (baseline) and the other with the SVF actively injecting harmonic currents. In both cases, the submodule switching characteristics were analyzed under varying balancing frequencies, f_balance (equivalent to varying f_{R_sort}).

5.1. Impact of Balancing Frequency on SLCC-SVF Submodule Driving Signals with Non-Harmonic Filtering Conditions

(1)

Case with a Balancing Frequency of 100 Hz

Figure 12 presents the steady-state voltage and current waveforms at the LCC under fundamental operation with a balancing frequency (f_balance) of 100 Hz. The figure displays both the steady-state waveforms and the compensated waveforms following SVF filtering. The corresponding filtering performance is further analyzed in Figure 13a.

As illustrated in Figure 12a,b, in the absence of active harmonic injection from the SVF, the system effectively suppresses high-frequency switching noise but remains ineffective in mitigating low-frequency harmonics. This deficiency leads to evident waveform distortion and amplitude fluctuations. Specifically, the inadequate filtering capability within the 0–200 Hz range, as indicated in Figure 13a, results in the current phase mismatch observed in Figure 12b. The severity of this distortion is substantiated by the Total Harmonic Distortion (THD) values of 32.3%, 34.0%, and 18.24% across the three phases.

Conversely, Figure 13b demonstrates the efficacy of the proposed strategy. With the method active at f_balance = 100 Hz, the submodule driving signals achieve a uniform distribution. Under this condition, the average switching frequency f_avg is 61.2 Hz.

(2)

Case with a Balancing Frequency of 500 Hz

Figure 14 presents the steady-state voltage and current waveforms at the LCC obtained with a balancing frequency (f_balance) of 500 Hz, The figure displays both the steady-state waveforms and the compensated waveforms following SVF filtering. The corresponding filtering performance is detailed in Figure 15a.

As illustrated in Figure 14b, the filtered LCC current waveform continues to exhibit abrupt fluctuations. This observation, corroborated by the frequency spectrum in Figure 15a, indicates that while the SLCC-SVF system effectively suppresses high-frequency harmonics, significant low-frequency components persist. These residual harmonics result in distortion of the fundamental waveform. Nevertheless, increasing the balancing frequency to f_balance = 500 Hz yields superior suppression of high-frequency harmonics compared to the 100 Hz case. This improvement is evidenced by the reduced three-phase THD values of 12.32%, 11.09%, and 10.99%.

Regarding switching behavior, Figure 15b shows that although the total number of switching events at 500 Hz is higher than at 100 Hz, the distribution of submodule driving signals remains relatively uniform. Under this condition, the average switching frequency f_avg reaches 161.4 Hz.

(3)

Case with a Balancing Frequency of 1000 Hz

With the balancing frequency f_balance set to 1000 Hz, Figure 16 presents the steady-state voltage and current waveforms at the LCC, displaying both the original signals and the compensated waveforms following SVF filtering. The corresponding filtering performance is further detailed in Figure 17a.

As illustrated in Figure 16b, the filtered LCC current waveform continues to exhibit visible fluctuations. The frequency spectrum in Figure 17a reveals that while the SLCC-SVF system effectively mitigates high-frequency components—with amplitudes approaching negligible levels beyond 200 Hz—low-frequency harmonics persist. These residual components distort the fundamental waveform. However, However, compared to the scenarios with f_balance = 100 Hz and 500 Hz (Figure 13a and Figure 15a), the system outperforms in the high-frequency range. This superior filtering capability is corroborated by the reduced three-phase THD values of 10.51%, 10.59%, and 10.54%.

Regarding switching characteristics, Figure 17b indicates that the number of switching events at f_balance = 1000 Hz s markedly higher than in the 100 Hz and 500 Hz cases. Under this condition, the average switching frequency f_avg escalates to 250 Hz.

5.2. Impact of Balancing Frequency on SLCC-SVF Submodule Driving Signals with Harmonic Filtering Conditions

(1)

Case with a Balancing Frequency of 200 Hz and SVF-Injected Harmonic Frequency of 250 Hz

In this scenario, the SVF is configured to inject 250 Hz harmonics into the SLCC-SVF system for harmonic suppression, while the balancing frequency f_balance is set to 200 Hz. Figure 18 depicts the steady-state LCC voltage and current waveforms, comparing the original signals with the waveforms after harmonic compensation. The corresponding filtering performance is further illustrated in Figure 19a.

As illustrated in Figure 18b, although the injection of 250 Hz harmonics suppresses high-frequency switching noise, the system fails to effectively track the target harmonics due to the insufficient balancing frequency. This inadequate filtering allows low-frequency components to distort the fundamental waveform, causing severe amplitude fluctuations. Figure 19a substantiates this poor performance in the low-frequency range (0–200 Hz), which directly accounts for the current phase mismatch observed in Figure 18b. Consequently, the three-phase Total Harmonic Distortion (THD) values remain critically high at 62.69%, 58.51%, and 69.95%, indicating significant waveform deterioration.

Furthermore, regarding switching characteristics, Figure 19b reveals that operating at f_balance = 200 Hz with 250 Hz harmonic injection disrupts the uniformity of submodule driving signals. The number of switching events increases, and the average switching frequency f_avg reaches 82.4 Hz.

(2)

Case with a Balancing Frequency of 1000 Hz and SVF-Injected Harmonic Frequencies of 250 Hz, 350 Hz and 450 Hz

In the scenario involving the simultaneous injection of 250 Hz, 350 Hz, and 450 Hz harmonics for suppression, the balancing frequency f_balance is configured to 1000 Hz. Figure 20 presents the steady-state voltage and current waveforms at the LCC, displaying both the original signals and the compensated waveforms following SVF filtering. The corresponding filtering performance is detailed in Figure 21a.

As illustrated in Figure 20b, the simultaneous injection of 250 Hz, 350 Hz, and 450 Hz harmonics effectively mitigates high-frequency switching noise. However, despite partial filtering, low-frequency harmonics are not fully suppressed and continue to distort the fundamental waveform, causing amplitude fluctuations. Figure 21a corroborates the insufficient filtering capability in the 0–200 Hz range, where residual harmonics are clearly evident. Consequently, the three-phase Total Harmonic Distortion (THD) values remain noticeable at 8.08%, 7.75%, and 8.06%, confirming the persistence of waveform distortion.

Regarding switching behavior, Figure 21b reveals that the number of switching events is significantly higher than that observed in Figure 19b. This increase is attributed to the high balancing frequency (f_balance = 1000 Hz) required for multi-frequency harmonic injection. Under this condition, the average switching frequency f_avg reaches 240.4 Hz.

(3)

Case with a Balancing Frequency of 3000 Hz and SVF-Injected Harmonic Frequencies of 250 Hz, 350 Hz, 450 Hz, 550 Hz and 650 Hz

In the scenario targeting comprehensive harmonic suppression, the SVF injects a broad spectrum of harmonics (250 Hz, 350 Hz, 450 Hz, 550 Hz, and 650 Hz) into the system. Accordingly, the balancing frequency f_balance is configured to 3000 Hz to ensure adequate control bandwidth. Figure 22 presents the steady-state LCC waveforms, displaying both the original signals and the compensated versions. The corresponding filtering performance is further detailed in Figure 23a.

As illustrated in Figure 22b, the injection of broad-spectrum harmonics (250–650 Hz) effectively suppresses high-frequency switching noise. While most low-frequency harmonics are substantially attenuated, a small residual portion persists, causing minor distortion and amplitude fluctuations in the fundamental waveform.

Figure 23a confirms that these residual components remain primarily in the 0–100 Hz range. However, the overall filtering performance is significantly improved, resulting in three-phase Total Harmonic Distortion (THD) values of 5.07%, 5.59%, and 5.06%, respectively.

In terms of switching behavior, Figure 23b reveals a dramatic increase in the density of submodule switching signals compared to both the 1000 Hz case (Figure 21b) and the fundamental operating condition. This surge is driven by the high balancing frequency (f_balance = 3000 Hz) required for the multi-frequency injection. Consequently, the average switching frequency f_avg escalates to 863 Hz.

5.3. Average Switching Frequency Under Various Operating Conditions

As summarized in

Table 1. Impact of Operating Conditions on Average Switching Frequency.

Operating Condition	fbalance/fh	favg
Non-harmonic filtering conditions	fbalance = 100 Hz	61.2 Hz
	fbalance = 500 Hz	161.4 Hz
	fbalance = 1000 Hz	250 Hz
Harmonic filtering conditions	fbalance = 200 Hz; fh = 250 Hz	82.4 Hz
	fbalance = 1000 Hz; fh = 250 Hz, 350 Hz, 450 Hz	240.4 Hz
	fbalance = 3000 Hz; fh = 250 Hz, 350 Hz, 450 Hz, 550 Hz, 650 Hz	863 Hz

and Figure 24, when the SVF operates without active harmonic injection, the increase in average switching frequency f_avg is marginal. In contrast, during active harmonic suppression, the balancing frequency f_balance must be raised significantly to accommodate higher harmonic frequencies—a trend consistent with the theoretical analysis. This adjustment results in a substantial surge in f_avg.

Specifically, consider the scenario requiring the suppression of 250, 350, 450, 550, and 650 Hz harmonics. To comply with the Nyquist sampling theorem, f_balance t must be increased to 3000 Hz. This configuration leads to an f_avg that markedly exceeds those observed in both the fundamental operating case and the 1000 Hz scenario (which targeted a narrower spectrum of 250–450 Hz).

5.4. Average Switching Frequency Under Optimized Generation Strategy

Building upon the analysis in Section 5.2, the optimized submodule driving strategy proposed in this study is applied to the SLCC-SVF system. The resulting average switching frequencies (f_avg) are summarized in

Table 2. Frequency Average Switching Frequency Under the Proposed Optimization Strategy.

Operating Condition	fbalance/fh	favg
Harmonic filtering conditions	fbalance = 200 Hz; fh = 250 Hz	62.6 Hz
	fbalance = 1000 Hz; fh = 250 Hz, 350 Hz, 450 Hz	197.8 Hz
	fbalance = 3000 Hz; fh = 250 Hz, 350 Hz, 450 Hz, 550 Hz, 650 Hz	678.3 Hz

.

A comparative analysis of Table 1 and Table 2 demonstrates that the proposed strategy effectively mitigates switching frequency fluctuations and substantially minimizes redundant switching events. Notably, this improvement is evidenced by an approximate 20% reduction in the average switching frequency, f_avg.

The average switching frequency under the optimized generation strategy for driving signals with different weighting factors is detailed in

Table 3. The influence of different weights on the average switching frequency.

fbalance	Different Weight	favg
3000 Hz	0.6:0.4	853.7 Hz
	0.8:0.2	785.6 Hz
	0.7:0.3	678.3 Hz

.

As shown in the data in Table 3, when the weighting factors were set to 0.8:0.2 and 0.6:0.4, the average system switching frequency increased by approximately 15% and 25%, respectively, compared to the 0.7:0.3 scheme. This indicates that overemphasizing the frequency weight (0.8) makes the system susceptible to measurement noise interference, while overemphasizing the temperature weight (0.4) delays the response to electrical stress threats. Therefore, the 0.7:0.3 weighting achieves the optimal balance between rapid frequency suppression and ensuring thermal safety, resulting in the best overall performance.

5.5. Limitations and Future Work

This study provides a systematic theoretical verification for the mechanism and suppression strategies of abnormal increase in switching frequency through simulation analysis. However, there are still certain limitations. Mainly due to the constraints of actual engineering safety regulations and operating conditions, no field experimental verification has been conducted at present. In the future, a small-scale model will be built to carry out experimental research.

Furthermore, the current model not only accurately depicts the coupling relationship between harmonic filtering and the voltage balancing algorithm but also eliminates the influence of secondary factors by simplifying practical aspects such as communication delays, device non-linearities, and grid dynamic interactions. Therefore, we have identified ‘establishing a precise dynamic model that accounts for communication delays, device non-linearities, and grid interactions, and optimizing the hybrid modulation strategy on this basis’ as a priority direction for our future research.

6. Conclusions

This study has systematically investigated the abnormal switching frequency surge observed in SLCC-SVF systems during harmonic filtering and proposed an optimized submodule driving strategy. The mechanism driving these frequency fluctuations—primarily attributed to the voltage-sorting balancing algorithm—has been elucidated, followed by a quantitative analysis of both instantaneous and average switching frequencies.

Results indicate that in the absence of harmonic filtering, the average switching frequency (f_avg) increases moderately—for example, rising from 161.4 Hz to 250 Hz (a 54% increase) as the balancing frequency (f_balance) shifts from 500 Hz to 1000 Hz. In contrast, during active harmonic filtering, f_balance must increase synchronously with the injected harmonic frequencies to satisfy the sampling theorem, leading to an abnormal surge in f_avg. For instance, when filtering a wide spectrum (250–650 Hz), f_avg jumps from 240.4 Hz (at f_balance = 1000 Hz) to 863 Hz (at f_balance = 3000 Hz), marking a massive 259.1% increase.

To mitigate this, an adaptive hybrid modulation strategy is proposed. Under normal conditions, the system operates using the NLM scheme combined with sorting-based balancing. However, if a submodule exceeds frequency or temperature limits, it seamlessly transitions to CPS-PWM, leveraging closed-loop balancing for rapid regulation. This approach effectively reduces f_avg and optimizes the switching distribution. Simulation results confirm the strategy’s effectiveness: under the complex filtering condition (f_balance =3000 Hz, injecting 250–650 Hz harmonics), f_avg is reduced from 863 Hz to 687.3 Hz—a decrease of approximately 20%. This significantly minimizes redundant switching actions, thereby enhancing overall system efficiency and stability.