Improved Thermal Transient Testing of Wide Bandgap Devices with Extremely Low Channel Resistance ^†

Abstract

Thermal transient testing (TTT) is an essential technique for characterizing electronic systems, including packaged devices, modules, and subassemblies. These tests serve two closely related purposes: first, they enable determination of peak operating temperatures under various power conditions; on the other hand, they allow extraction of partial thermal resistances within the tested structure and identification of structural details near the active devices. The latter objective has become increasingly challenging with the advent of wide bandgap devices featuring extremely low on-state resistance, such as GaN HEMTs. This paper first identifies the temperature-sensitive electrical parameters and heater structures relevant for TTT of semiconductor devices. It then narrows the focus on GaN power devices and analyzes how external series resistances, originating from HEMT packages and the associated printed circuit boards, affect thermal impedances and structure functions. To remove the influence of these external resistances, which distort the extracted thermal descriptors, an analytical correction methodology has been developed. The proposed approach is validated through measurements performed on real devices. The results demonstrate that the method successfully restores the intrinsic thermal properties of the devices, yielding more accurate and physically meaningful thermal characteristics.

1. Introduction

Thermal transient testing is the essential characterization methodology for the analysis of a wide range of electronic systems, including discrete packaged semiconductor devices, power modules with internal wiring, LED luminaires, and complete subassemblies. It provides a deep analysis of the whole heat conducting path, from the heat generating semiconductor chips through the package, thermal interfaces and cooling mounts.

In all cases, the main steps in thermal transient analysis are: identifying semiconductor structures for heating, others with temperature-sensitive electric parameters (TSPs), switching between two power levels and recording the temperature change during cooling [1].

Comprehensive thermal transient testing of modules and subassemblies is essential in quality assurance, as it reveals potential manufacturing defects and failures, thus preventing the mass recall of high-value products, which can damage business reputation and cause significant financial losses [2].

In recent decades, relevant procedures have been elaborated for handling complex structures with multiple heat-conducting paths (Figure 1), based on various boundary conditions applied on several parts within the structure. These methods have a theoretical background [1] and are supported with a combination of simulations [3] and measurements [1].

In reality, with the advent of novel power switching elements, such as SiC MOSFETs and GaN HEMTs combining high blocking voltage and extremely low ON resistance, a significant portion of heat is dissipated in the bond wiring, PCB traces, cables and test jigs of a transient tester.

The current research gap in thermal transient testing for wide bandgap (WBG) devices is that neither engineering praxis nor related standards [4,5] take into consideration the significant power component which is dissipated farther from the powered die and leaves the system through an alternative heat conducting path.

This work targets resolving the problem with a series of thermal transient tests at various power levels and analytical calculations on the results for clear separation of the dissipating constituents.

Based on these new results, the accuracy of thermal transient measurements on WBG devices can be highly improved.

Below, Section 2 reviews the state of the art in thermal transient concepts and Section 3 presents the equivalent model on which the analytical equations can be formulated.

Section 4 presents the analytical apparatus which is applied. Section 5 shortly summarizes the GaN operation only to the extent needed to understand the measurement principles and refers to a broader background; further on, it presents typical transient measurement schemes.

In Section 6, a case study proves the validity of the novel measurement and evaluation concept.

2. Review of Existing Thermal Transient Measurement Concepts

In the case of traditional packaged transistors and IGBT modules, the heat flow is basically one-dimensional, and thermal metrics are based on temperature measurements in a single major heat-conducting path.

An eminent field of use of transient analysis is in situ testing. Appropriate excitation on power components in a subassembly or in an appropriate mockup may reveal structural details, material parameters and failure locations.

In modules and subassemblies, the largest dissipation typically occurs on simple power semiconductor devices, such as diodes (two-terminal devices) and transistors (three-terminal devices). Below, we discuss the measurement and calculation methods which are relevant for these categories.

2.1. Thermal Transient Measurement on Basic Semiconductor Devices

We first recapitulate measurements on standard MOSFETs, as conventional thermal transient testers provide the required instrumentation. By shorting two of the three terminals (Figure 2a), a power step can be produced by switching between two current levels, while the voltage across the terminals is recorded as TSP.

In real applications, a constant I_sense “sensor” or “measurement” current is maintained on the device, and a significantly larger I_drive current is switched on and off.

The schematic of Figure 2a poorly resembles the real-world use of the device; the heating and sensing occur on the reverse diode of the MOSFET.

The power is limited; it is the product of the V_F forward voltage and the forward current (I_F = I_drive + I_sense). Nonetheless, junctions provide crisp and noise-free transient at low I_sense, enabling high-fidelity evaluation.

Heating and sensing on the channel (Figure 2b) correctly mimic the power dissipation during operation. However, this method provides low signal levels in devices with low channel resistance.

In the third method, the advantages of the two preceding methods are combined: heating is applied to the channel, as in realistic operating conditions, while temperature sensing is performed on the reverse diode, as can be seen in Figure 2c.

In all cases, parasitic electrical effects—including external and internal capacitances and inductances as well as time- and operating-point-dependent variations in device parameters—can generate transients in the same time domain as the thermal transient with comparable or higher amplitude, thus significantly distorting the temperature signal.

The removal and the substitution of this electrical transient is addressed in the corresponding standards [4,5], but separating the electrical and thermal transients may require additional treating, such as dynamic calibration introduced in [6].

2.2. Interpretations of Power, Thermal Resistance and Thermal Impedance in Thermal Transient Tests

It is important to note that thermal transient measurements serve two closely related, yet distinct objectives.

First, they predict the temperature response of the tested object (e.g., a subassembly or an LED lamp) under arbitrary power dissipation levels. In this interpretation, the assembly is handled as an entirety, without knowledge of its internal details. The prediction is based on the result of a transient thermal test performed at a single, selected test power. This P_el power is calculated from the changing External Electric quantities, i.e., voltages and currents applied on the Entire assembly, so this measurement objective is denoted below as Task E.

Linearity is assumed in the thermal domain, so the temperature responses at different locations in the assembly are upscaled and downscaled proportionally for different P_el powering.

A basic outcome of Task E is the junction-to-ambient thermal resistance R_thJA. When a heat source within the system dissipates P_el power, R_thJA provides a simple estimate on the $T_J$ temperature at the heat source location, traditionally called “junction”.

A different target is to determine the real thermal performance of the core component, such as a transistor or LED, either measured in a dedicated test fixture or in situ while embedded within a higher-level subassembly. This test, referred to here as Task R, relates calculations on the P_real power which appears on the core semiconductor component in an assembly. It yields detailed thermal metrics, including thermal properties of interface layers around the power source and the identification of thermal bottlenecks or failure locations. A fundamental output of Task R is, for instance, the junction-to-case thermal resistance R_thJC, which is essential for thermal design and for evaluating the impact of different heat sinks with a given thermal resistance $R_{\mathrm{t}\mathrm{h},\mathrm{s}\mathrm{i}\mathrm{n}\mathrm{k}}$.

The distinction between Task E and Task R becomes critical when the P_el electrical input power applied to the system does not reach the core device under investigation. This arises, e.g., in optoelectronic devices, where a significant fraction of the input power is emitted as optical radiation and therefore does not contribute to heating of the light-emitting junction. A similar separation of Task E and Task R occurs when the device under test (DUT) is of mainly resistive nature. This effect becomes particularly important in field-effect transistors with extremely low R_DSON channel on-resistance when the resistance of external wiring, test fixtures, or module interconnects is comparable to R_DSON.

With the introduction of High Electron Mobility Transistors (HEMT) on gallium nitride (GaN) material, this issue became even more significant. In such cases, it is indispensable to determine the effective power P_real dissipated within the DUT by subtracting the externally dissipated power P_ext associated with wiring and other external structures that do not thermally load the DUT.

Unfortunately, while extensive attention is devoted to system-level electrical testability in product design, the aspects of thermal testability are often neglected. In this work, we introduce a set of methods that also restore accurate thermal parameters when direct access to the core semiconductor device is limited.

As highlighted above, in transient thermal measurements, the temperature response of the DUT is recorded following an abrupt change in applied power. Dividing the ΔT_J junction temperature change in time by the applied power step δP, the normalized temperature response, also called thermal impedance curve, is obtained: Zth(t) = ΔT_J(t)/δP.

Note that throughout this work, the symbol Δ denotes temperature changes occurring over prolonged time intervals, whereas δ denotes instantaneous changes associated with switching events.

The use of thermal impedance assumes linearity of the device or assembly in the thermal domain; once a single Zth(t) curve has been measured, the transient temperature corresponding to any other $\delta P_{\mathrm{n}\mathrm{e}\mathrm{w}}$ power step may be approximated as

$$\mathsf{\Delta }{T}_{\mathrm{n}\mathrm{e}\mathrm{w}}\left(t\right)=\delta P_{\mathrm{n}\mathrm{e}\mathrm{w}}\cdot Z_{\mathrm{t}\mathrm{h}}\left(t\right).$$

Complete transients, from steady state to steady state, provide information on the structure over the entire heat-conducting path. When the transient process reaches the opposite steady state at t_ss time, Zth(t_ss) produces the Rth thermal resistance value.

In Task R, when $\delta P_{\mathrm{r}\mathrm{e}\mathrm{a}\mathrm{l}}$ is known, the measured thermal impedance curve $Z_{\mathrm{t}\mathrm{h},\mathrm{r}\mathrm{e}\mathrm{a}\mathrm{l}}\left(t\right)$ can be further transformed into an equivalent one-dimensional network of thermal resistances and capacitances, known as structure functions [1,5]. These reveal structural features, material properties, and potential failure locations within the assembly, and help extract valid thermal metrics. Their underlying theory and practical applications are given in textbooks, e.g., [1].

The product $\delta P\cdot Z_{\mathrm{t}\mathrm{h}}$ yields the correct junction temperature change $\mathsf{\Delta }{T}_J$ in both Task E and Task R, as long as the matching P and Zth functions are used. Combining the higher nominal power step $\delta P_{el}$ with measured temperature change leads to erroneous values of R_thJC in Task E and distorted structural information when applied to Task R.

The heat sources generating $\delta P$ and the temperature sensors measuring $\mathsf{\Delta }T$ within the DUT are typically realized using pn junctions or resistive semiconductor regions. The main limitations on achievable measurement accuracy are illustrated below in numerical calculations and a simplified test example.

3. Improved Model for Thermal Transient Testing: Testing of Series Circuits

The first step towards improved test results is modeling the traces, wires, cables and similar resistive elements in the packaged device or test scheme in the form of an R_ext series resistor (Figure 3).

In this approach, the core device under test is simplified to a diode D or resistor R_DUT. Due to their temperature-sensitive electric parameters, they can operate as a heater and sensor simultaneously.

The impact of R_ext is minor in conventional packaged silicon devices but becomes significant in modules, embedded systems, and GaN devices with low on-resistance.

In silicon devices, pn junctions (core part of D) play a central role due to their widespread availability. In GaN devices, only specific technologies provide such junctions; for this reason, resistive heaters and sensors, e.g., an R_DUT channel resistance, are preeminent.

Condensing external structures into R_ext is valid if, during the test, their location is not heated up drastically by the DUT.

In reality, these structures also heat up when the core device is dissipating power, but this is mostly negligible, especially in the critical high-temperature state of the core device. For example, when the device junction or channel has already reached 150 °C, the approximately 40 °C heating of the connecting leads causes only a minor calculation error. This effect can be observed in certain figures in Section 6.

Depending on the test setup, the nearest access points to the DUT may differ. Using standard terminology, configurations with separate access to the DUT and R_ext (P1-P2-P3 in Figure 3) are referred to as four-wire (4W) measurements, whereas two-wire (2W) measurements provide access only via the outer terminals P1 and P3.

For two-pin devices, the obvious TSP is the V_sense voltage across the best accessible points at a low I_sense current. V_sense is recorded between P2-P3 in 4W and P1-P3 in 2W configurations.

Expanding the definition of thermal transient testing, as given above in the Introduction section, we can state that the actual transient test always consists of more consecutive steps:

• In a calibration process, the DUT is placed in a temperature-controlled environment and the T_J to V_sense relation defining the TSP is recorded at various temperatures.
• During the heating phase, a high I_H = I_drive + I_sense current is applied until steady state is reached at $t_{\mathrm{s}\mathrm{s}}$, and the corresponding voltage $V_H$ is stored. As defined by various standards, e.g., [4,5], the full electric power supplied to the device is P_elH = I_H · V_H.
• Before starting cooling, I_drive is switched off while maintaining I_sense, and the transient V_sense is measured and converted to temperature using the TSP mapping.
• The raw transient voltage data are converted to temperature change using the calibration points.
• Normalizing the temperature change by the δP power step—whichever interpretation of it is relevant for the intended purpose—Zth curves and structure function are calculated.

The change in the electric powering at the moment of switching is δP_el = P_elH − P_elL, where the power at low current is P_elL, which can be computed as the product of I_sense and V_sense on the hot DUT, just after switching off.

Junctions exhibit a negative thermal coefficient, whereas resistive semiconductor regions may show a positive one, depending on technology. For example, the conductive channels in silicon MOSFETs and GaN HEMTs typically have a positive thermal coefficient.

The effect of R_ext on the TSP calibration is negligible; it is largely compensated by the calibration which occurs at low power.

Regarding the power calculation, in cases such as module testing, the P_Rext = R_ext · I_H² power does not heat the DUT, whose temperature is instead governed by P_real = P_el − P_Rext quantity (In optical devices, the emitted optical power is also to be subtracted, see [7]).

For this reason, the definition of Zth and Rth diverges into two interpretations; R_thel defines an electric while R_threal a real thermal resistance, depending on whether the temperature change was divided by a δP_el or δP_real change. Both definitions are physically meaningful and yield the same T_J = Rth_{_X} · δP__X temperature rise.

R_threal is a property of the internal DUT and is independent of the applied I_H. It is relevant for cooling system design, as this is the power component which flows towards, e.g., the heat sinks. Corresponding Z_threal curves are to be used in the calculation of undistorted structure functions, providing correct material parameters of the structural components and accurate failure locations.

In contrast, R_thel reflects the actual final temperature of the DUT in a 2W assembly at I_H current and T_amb ambient temperature.

In diode-type devices, P_real grows logarithmically with $I_H$, whereas P_Rext scales quadratically, leading to the characteristic shrinking (“accordion”) effect observed in Z_thel functions (Figure 4).

When 4W access is available, measuring the voltage on P2-P3 pins for power calculation mostly eliminates the effect of R_ext.

In the case of pn type DUTs, in the literature, a methodology for an acceptable restoration of Z_threal is proposed for 2W cases (e.g., in [1] Chapter 6).

Regarding the cooling phase of the transient, it is important to notice that at I_sense, the power on R_ext is low. Moreover, its existence does not affect the accuracy of the TSP calculation; this is processed out through the calibration process (step 1 above). However, when dividing the temperature change by the power (step 5), in the 2W case, the remaining power on the series resistance does not actually participate in the heating of the DUT, causing the known shrinking effect in Zth curves, typical when measuring modules and embedded structures.

4. Analytical Approach to Thermal Transient Problems

4.1. Estimations on the Impact of External Resistive Components

Surprisingly good estimates of the impact of an external R_ext resistance can be made based on simple analytic calculations.

The behavior of pn junctions is sufficiently accurately determined by the Shockley equation. For the voltage, current and power:

V_F = m·V_T · ln(I_F/I₀),   P_D = V_F · I_F

(1)

where, as is known from textbooks (e.g., [1]),

• I_F is the current applied to the device
• V_T is the thermal voltage, a physical amount proportional to the T_J absolute temperature of the device; its value is 26 mV at 300 K (27 °C)
• m is a technological parameter, between 1 and 2 in practical cases and
• I₀ is a temperature-dependent saturation current.

In (1), only m and I₀ are related to the actual device, while the test environment regulates the current I_F and the temperature T_J, taking the thermal resistance of the assembly also into consideration.

Due to the exponential nature of the Shockley equation, just measuring at two different currents, many unknown quantities can be eliminated or calculated. The difference in the V_F forward voltages is

V_F2 − V_F1 = m · V_T · ln(I_F2/I_F1)

(2)

For resistors,

V_R = R · I,   P_R = R · I²

(3)

Example 1.

A typical chart illustrating the temperature and current-related changes in an ideal pn junction is presented in Figure 5.

Figure 6 repeats the quantities of Figure 5 in logarithmic scale. The exponential nature of the Shockley equation can be observed as a straight line in the chart.

As (1) dictates the characteristics in a rigid way, measuring a typical single operating point already defines the core device behavior over a large temperature and current range. Suppose a typical silicon diode has V_F = 700 mV forward voltage at I_F1 = 1 A, at T_J = 25 °C junction temperature. This “Low current at cold temperature” point is denoted as cL in the chart. Curve tracers draw device characteristics at constant temperatures, in pulsed current operation. Such an instrument would draw the “cold pn” thread, corresponding to 25 °C in the 1 A to 20 A range, now calculated from (1). The thread ends in the “high current at cold temperature” point, denoted as cH.

Let us assume 5 K/W for the R_thJA junction-to-ambient thermal resistance and dV_F/dT = −2 mV/K temperature coefficient for the forward voltage change at increasing temperature. Both parameters are typical values. Using these parameters, in a later iteration process, we estimated that the junction temperature rise is about 70 °C at 20 A forward current.

With similar calculation, we established the “hot pn” thread, between the “low current at hot temperature” point, hL, and “high current at hot temperature” point, hH. We can observe that with the assumed thermal coefficient, the 70 °C temperature growth induces the 140 mV voltage decrease in Figure 6.

In an actual thermal transient testing process, the heating starts from the cL point and in a short time, determined by the tester electronics, jumps to the cH point. The heating process covers a few or many minutes, slowly descending from cH to hH (heating transient).

Switching down from 20 A to 1 A, an electric transient occurs in a few microseconds between hH and hL. Finally, the cooling transient is recorded for a prolonged time between hL and cL.

Assume the external package or wiring elements are concentrated in an R_ext = 10 mΩ series resistance, only mildly affected by the heating of the junction. This resistance provides an additional 10 mV in the scheme of Figure 3a. In the starting cL point, the P_D power on the D diode is 0.7 W, while R_ext is dissipating 10 mW, only 1.4% of P_D, which is often negligible.

Instead of sharp changes in the driving current, we can calculate the corresponding power and temperature of the diode at different currents while waiting at each current for equilibrium (T_J static curve in Figure 5). For presenting T_J static curve, Equation (2) was solved by a Python code in a few iterations. This curve also indicates where the final hH point would be if the transient occurred at lower than I_F = 20 A; at this heating, the “hot pn” curve would be shifted up to this other hH point.

The power dissipation of each component in Figure 3 can also be easily calculated. The power loss on the external resistance scales quadratically with the current, and the power of the diode scales nearly linearly due to the logarithmic nature of the I-V characteristics and the negative thermal coefficient. As calculated from the simulation, the power loss therefore increases from 1.4% to 22% of the total dissipation while the current is changing from 1 A to 20 A (Figure 7). Exactly this growth of the power share on the resistor causes the characteristic “accordion” shrinking of the Zth thermal impedance in Figure 4.

It should be noted that in this simple model, we have neglected the current dependence of the $d{V}_F/dT$, which slightly decreases with increasing forward current. Assuming constant R_ext, we also neglected the temperature-dependent resistivity change of the internal layers inside the component.

Example 2.

Suppose in a data sheet, a MOSFET transistor is characterized with a drain-source on-state resistance of R₂₅ = 55 mΩ value at room temperature and R₁₅₀ = 100 mΩ at 150 °C. The related literature claims that the on-state resistance at a given temperature can be approximated with:

$$R_{DS}(T)=R_{25}{\left({\displaystyle \frac{T}{T_0}}\right)}^{\alpha }$$

(4)

From the given datasheet resistivity values, using Equation (4), we can calculate $\alpha =1.7$.

Let us assume a series R_ext = 10 mΩ again and 2 K/W for the junction-to-ambient thermal resistance. Starting with 1 A transistor current again, the voltage on the channel would be 55 mV, to which the external resistance adds 10 mV. The power on the transistor is 55 mW, causing just 0.11 °C temperature elevation, so reckoning with 55 mΩ channel resistance is still valid. R_ext is dissipating 10 mW, which is now a considerable 15% of the measured power.

Based on (4) and Ohm’s law, we can calculate the corresponding voltage, power and temperature of the transistor again at different currents, as we did in the previous example.

As shown in Figure 8, in this case, the hot and cold voltage–current curves are linear, but the static characteristic shows strong nonlinearity due to the increase in the channel resistance. At 20 A current, the power dissipated on the transistor in hot steady state is nearly doubled, growing to P_RDS = 38 W from the initial 22 W dissipation on the cold device at 20 A. The series R_ext still dissipates 4 W, but its share decreased to 9% of the total power.

A similar but opposite accordion effect is expected in Zth, in a two-wire measurement arrangement. Now, the percentage of the power remaining outside decreases, resulting in an increase in the calculated Zth (Figure 9).

If we compare the two examples, we find that with a diode-type heater/sensor, the shrinking effect can be suppressed by creating reference Zth curves at a lower current, and rescaling higher current curves by upscaling them to the reference. In resistive heater/sensor arrangements, the powering error is larger at low currents than at high ones, which makes this kind of correction unfeasible.

4.2. Calculation of R_ext for Resistive Heaters and Sensors

The total ΔT_J temperature change on the DUT, from the moment of switching until the stabilization time t_ss, can be expressed in a true 4W measurement as ΔT_J = R_threal · δP_real.

If one has only 2W access to the HEMT in the arrangement in Figure 12 or Figure 13, a higher δP_el power step is measured at the best accessible points, due to the power dissipated on the wiring.

Although the wiring resistance exhibits temperature dependence, this effect is neglected in the first-order approximation of our model. Incorporating an averaged but temperature-independent external resistance yields improved results, as discussed in the subsequent sections. In power transistor structures, the temperature coefficient of the wiring is typically lower than that of the resistive channel in the transistor, while the temperature rise in the wiring remains substantially smaller than that in the junction region. Therefore, the applied approximation is considered justified.

For calculating R_ext, we can express the ΔT_J total temperature change as:

ΔT_J = R_thel · δP_el = R_threal · [δP_el − R_ext · (I_H² − I_sense²)]

(5)

In the equation, we corrected the measured power step by subtracting the dissipated power on the external wiring from the measured electrical power. I_H is again the shorthand notation for I_drive + I_sense.

Since R_threal should not depend on the power applied, from (5), simply dividing two measurements at different I_drive2 and I_drive1 heating currents without varying I_sense measurement currents gives the following equation:

$${\displaystyle \frac{{\mathsf{\Delta }T}_{J2}}{\mathsf{\Delta }{T}_{J1}}}={\displaystyle \frac{\delta P_{el2}- R_{ext}[{\left(I_{drive2}+I_{sense}\right)}^2-I_{sense}^2)]}{\delta P_{el1}- R_{ext}[{\left(I_{drive1}+I_{sense}\right)}^2-I_{sense}^2)]}}$$

(6)

Introducing the ${\mathrm{K}}_X\left(I_{driveX},I_{sense}\right)=I_{driveX}^2+2I_{driveX}{I}_{sense}$ factor, (6) is simplified to

$${\displaystyle \frac{{\mathsf{\Delta }T}_{J2}}{\mathsf{\Delta }{T}_{J1}}}={\displaystyle \frac{\delta P_{el2}-R_{ext}\cdot K_2}{\delta P_{el1}-R_{ext}\cdot K_1}}$$

(7)

From (7), R_ext can be expressed as:

$$R_{ext}={\displaystyle \frac{{\mathsf{\Delta }T}_{J2}\delta P_{el1}-{\mathsf{\Delta }T}_{J1}\delta P_{el2}}{K_1{\mathsf{\Delta }T}_{J2}-K_2\mathsf{\Delta }{T}_{J1}}}$$

(8)

Equations (6) and (8) provide a tool to determine R_ext when there is only 2W access to a DUT, and so, no reference Z_threal is available. It may work well for larger power differences, but the formula is very sensitive to measurement errors and perturbations as both the numerator and the denominator are small.

5. Basic GaN Operation and Thermal Transient Measurement Schemes

5.1. Basic GaN Operation

The most common type of GaN devices, the lateral HEMT, is sketched below in Figure 10.

In HEMTs, an aluminum–gallium nitride composite layer (AlGaN) is grown on top of monocrystalline GaN.

As in silicon MOSFET devices, a surface charge builds at the interface of the two materials, leaving unmovable positive ionized atoms in the AlGaN layer and freely moving electrons in the surface layer in the GaN base, next to the interface.

In the GaN bulk, no dopants impede the motion of electrons; the freely moving carriers ensure high channel conductivity. This is reflected in the device name: high-electron-mobility transistor (HEMT).

A more detailed treatment of its physics is given in [1,8].

For producing normally off devices in power switching applications, two similar approaches are widely used, both based on inserting an acceptor-doped p-type layer (p-GaN) under the gate metallization (Figure 10 and Figure 11).

The p-GaN layer inserts two additional material interfaces (junctions) into the gate structure. The lower, depicted as 1 in Figure 11, forms between the p-GaN layer and the AlGaN.

The AlGaN layer is just a few rows of atoms deep; it falls fully into the depletion zone of 1.

At the upper junction, in certain cases, the contact potential between the gate metal and p-GaN accumulates charge carriers, which makes the junction of ohmic nature (shown as 2 in Figure 11). These devices are called gate-injection transistors (GIT). The gate voltage regulates the thickness of the depletion zone of the base GaN, resulting in three distinct operation modes:

• Blocking at low gate voltage when the channel vanishes.
• Classical field-effect operation when the channel appears but the voltage across the gate diode (junction 1) remains below the opening voltage (above 2 V for GaN material).
• Gate current mode when the gate diode opens and injects further charge carriers into the channel.

Doping of the p-GaN layer differently, at the upper junction, the contact potential between the gate metal and p-GaN depletes the p-GaN side, which forms a reverse Schottky diode (denoted by 3). These devices are named reverse Schottky gate HEMT, Schottky gate HEMT or p-GaN gate HEMT.

5.2. Thermal Transient Measurement Schemes of Power HEMTs

In an attempt to find a proper TSP, the temperature dependence of the R_DSON channel resistance or of the parasitic junction 1 in Figure 11 can be a good candidate.

5.2.1. Measuring with Heating and Sensing on the Channel

Figure 12 depicts a scheme in which both heating and sensing occur on the conducting channel, which is present in all HEMT types. As the R_DSON channel resistance is very low, high I_sense current is required for an adequate V_DS voltage drop and a detectable temperature-induced change.

Figure 12. A thermal transient measurement scheme, heating and sensing on the channel.

Figure 12. A thermal transient measurement scheme, heating and sensing on the channel.

Time variant effects can impose limitations on this measurement mode. For instance, when a movable charge is stored temporarily at trapping energy levels, its later release causes parasitic electrical transients [9]. These transients are hard to distinguish from the thermal response. Detailed analysis of the charge trapping mechanisms can be found in [10,11] for Schottky gate and GIT-type HEMT respectively.

5.2.2. Measuring with Continuous Gate Diode Current

As an alternative, the gate Schottky diode structure in GIT-type devices can be used for temperature sensing (Figure 13).

In this scheme, a small I_sense current opens the gate diode, offering a TSP of high sensitivity and low noise. Heating is applied on the channel, driven by many amperes.

Figure 13. A measurement scheme with heating on the channel resistance, sensing on the gate diode at continuous gate current.

Figure 13. A measurement scheme with heating on the channel resistance, sensing on the gate diode at continuous gate current.

The circuitry in Figure 13 is susceptible to external parasitic inductances and capacitances caused by the measurement wiring. To avoid any oscillations, which can fake the measurement results and destroy the component, it is recommended to monitor the measurement using an oscilloscope during the experiments and to use appropriate bypass capacitors (C_GS, C_DS) and ferrite beads if necessary.

5.2.3. Measuring with a Switched Gate Diode Current

When the maximum I_drive current is limited, the δP power step can be too low, even at the maximum rated current.

Figure 14 shows a way to resolve this contradiction. The scheme is based on the switched gate concept, first presented in [12]. During heating, V_G is of negative value, resulting in a thinner channel and higher V_DS. For the cooling, V_G is set to a positive voltage. Diode D₁ is reverse-biased; thus, V_G has no effect on the gate-source voltage, and I_sense can flow through the gate diode.

Further details on thermal transient testing of GaN structures are presented in [13,14].

5.3. Measuring with Dedicated Temperature Sensors

It can be observed that HEMT devices typically lack the parasitic structures of high thermal sensitivity, which allow comfortable measurement techniques in standard MOSFETs. Novel research proposes additional integrated sensors into GaN power modules for enabling accurate and easy thermal transient testing.

Fabrication process-compatible Schottky diode sensors exhibit about 4 mV/K temperature sensitivity and accurate capture of the thermal transient, without affecting the operation of the device [15]. The voltage of a Schottky diode at constant current as a temperature sensing parameter would make thermal transient testing of HEMT devices analog to their silicon counterparts, for which well-established instruments and methodologies have been available for more than three decades.

Chang et al. constructed an on-chip array of patterned Ti/Pt thermistor strips on the surface of a GaN HEMT device, in order to achieve real-time temperature monitoring at different positions of the chip [16].

Mutsafi et al. found that depletion-mode AlGaN/GaN HEMT’s drain current in subthreshold operation mode have extremely high, more than 8%/K, temperature coefficient [17].

Various easy-to-integrate monolithic sensor circuits have been reported, demonstrating robust, high-temperature operation while avoiding complex fabrication. In Ref. [18], a proportional-to-absolute-temperature (PTAT) sensor with a 0.35 mV/°C sensitivity has been reported; Ang Li et al. [19] increased the sensitivity nearly two orders of magnitude using a logic inverter as a voltage amplifier, achieving 32 mV/°C sensitivity. Despite the availability of monolithically integrated sensing solutions, at the time of writing this article, only a limited number of commercial modules provide dedicated thermal sensor output functionality. For example, the LMG3522R030 [20] smart power stage outputs a fixed 9 kHz pulsed waveform, in which the device temperature is encoded in the duty cycle. While this approach is generally sufficient for system-level monitoring, the effective sampling rate is inadequate for thermal transient analysis.

6. Case Study: Thermal Transient Measurement of a Power GIT Device

In an illustrative experiment, a mockup of a subsystem with a PCB hosting a power switching device was built for a series of thermal transient measurements. The device was an Infineon IGOT60R070D1 GIT device.

The device is packaged in a PG-DSO-20 package (Figure 15); characteristic data sheet values are 70 mΩ channel resistance and 31 A max, with continuous drain current at 25 °C.

This device was selected for the trials because it can be measured in all three modes presented in Section 5.2.

6.1. Measurement Planning

For studying the effects caused by internal wiring (bond wires in the package) and external segments (surface mount footprint, traces on the PCB, external cables belonging to the measurement setup), an appropriate circuit scheme (Figure 16a) and a wiring layout (Figure 16b) were designed.

To determine the power on the internal chip in the package, a complete 4W measurement arrangement would be optimal.

This is partly supported by the SS (source sense) Kelvin source pin, tied to an independent bond wire internally. For the drain, the best achievable approach is to separate a side pin from the main current path on the PCB (Dout in Figure 16b).

The assembly was mounted on the plate of a dry thermostat, with various thermal interface materials between the heat slug and the thermostat plate, as proposed in [4].

Appropriate currents for driving the gate, source and drain pins were applied from SIEMENS T3Ster Classic equipment, with booster extension, and it also provided recording the transient signals on its data acquisition channels.

The calibration and the actual tests were carried out in the arrangement in Figure 17.

An I_gate current (1 mA to 20 mA) turned the DUT into ON state when applied between the Gin and Wire_S access points.

From the measurement channels, Ch0 measured the V_GS voltage on the gate, Ch1 the voltage drop between the points nearest to the chip (best 4W, Dout to SS), and Ch2 also recorded the additional voltage drop on the PCB “force” traces.

A ferrite core, clamped on the cabling next to the drain driving point on the PCB, was necessary for dumping high-frequency oscillations at high current. Various resistors (R_test) inserted into the drain drive emulated further external wiring in a real system (0 Ω to 55 mΩ); channel Ch3 recorded the signal between farthermost D_DRive and S_ DRive points.

This arrangement enabled the simultaneous measurement of two “external” resistances; the difference between measurements on Ch2 and Ch1 yields an R_board quantity describing the effect of the PCB traces, while a similar difference between Ch3 and Ch1 yields an R_ext+ resistance, in which the external R_test resistor, mimicking a larger appliance, is also added.

6.2. Measurement Results

The calibration of all “sensors” occurred on the thermostat plate, at five temperatures from 20 °C to 60 °C. The PCB was separated from the plate by a few millimeters; the assumption that the series resistance related to it does not change with the plate temperature was approximately fulfilled.

As Figure 18 shows, linear interpolation fitted well the points for V_GS, with approximately −2.3 mV/K slope at I_gate = 10 mA.

The resistive sensors (Ch1 to Ch3) showed approximately 0.3%/K. 0.6%/K growth at I_sense = 2 A, similar to the trend assumed in Example 2, in Section 4.

The recorded voltages at the access points Ch1 to Ch3 are shown in Figure 19 after switching down from 10 A to 2 A at 80 s. After this timepoint, all thermal information is encoded into the seemingly constant voltage, a bit above 0.2 V for Ch3, and around 0.1 V for the other two channels.

For focusing on the relevant details, Figure 20 shows the voltage change after the switching, in logarithmic scale. The cooling process can be well observed on each channel.

The voltage transients were converted to temperature change through the calibration process. Figure 21 presents all ΔT_J temperature changes on all channels, with gate signal Ch0 also added, at I_H = 10 A, 8 A and 6 A.

The curves prove that the calibration on each channel was consistent, despite different temperature-dependent V_sense voltage being recorded on the channels at the same I_sense = 2 A, due to different R_ext in series. The voltage change curves are divided by the P_el power, which is calculated from the currents and channel voltages on each channel, to get Zth curves.

Figure 22 presents these Zth curves, namely, all channels at I_H = 10 A (in red), the ones taken at 8 A (green) and 6 A current (blue curves).

As expected, the curves derived with the best 4W access, which is Ch1, run the highest in the figure. The curves belonging to Ch2 are considered 2W result, compressed corresponding to the power on R_board = R__PCB1 + R__PCB2.

The external R_test adds 55 mΩ in series and shrinks the Ch3 curves further, below half of Ch1, as R_test is on the same scale as the HEMT channel resistance.

Figure 19 above presents how the voltages change when switching down from I_H = 10 A to I_sense = 2 A. Voltage difference of Ch2 and Ch1 divided by I_sense yields the “external” R_board value; from Ch3 and Ch1 voltages, R_ext+ = R_board + R_test can be calculated.

The R_DUT hot channel resistance is also calculated in the same way.

The part resistances from the voltage on hot resistors at all other I_H currents are listed in

Table 1. Applied currents and calculated resistances, 4 W.

Idrive [A]	Isense [A]	IH [A]	Rboard [mΩ]	R_test [mΩ]	Rext+ [mΩ]	RDUT [mΩ]
4	2	6	9.38	55.19	64.57	46.30
6	2	8	9.32	55.23	64.55	47.71
8	2	10	9.46	55.79	65.25	50.25

.

True 4W access can be rare in typical subassemblies. If the resistances in Table 1 cannot be obtained directly by Ohm’s law, other methods, like needle probe measurement or calculation from board trace layout, can still determine them.

Subtracting the power on an R_ext from δP_el should yield the true δP_real power change. Thus, R_board and R_ext+ values from Table 1 can be used to rescale the 2W curves Ch2 and Ch3 to their corresponding Z_threal curves, Ch2* and Ch3* (Figure 23).

If calculated R_board and R_ext+ are true, temperature-independent resistances, Ch2* and Ch3* must fit perfectly with the 4W measurement of Ch1. They do in the 100 μs to 10 s range, with only a small divergence observed after 10 s, possibly reflecting a minor heating effect of R_board and R_test.

As Equation (8) states, in a 2W arrangement, an estimation of external resistances and R_DUT can be obtained, too, based on the ratio of powers and temperatures at different current levels. Taking the values at I_H = 6 A as reference, and measuring at 8 A and 10 A currents, (8) yields the calculated part resistances in

Table 2. Applied currents and calculated resistances, 2 W.

Idrive [A]	Isense [A]	IH [A]	Rboard [mΩ]	R_test [mΩ]	Rext+ [mΩ]	RDUT [mΩ]
4	2	6	-	-	-	-
6	2	8	19.89	56.99	76.88	33.63
8	2	10	7.53	57.57	65.11	49.85

:

The calculated part resistances seem to be less consistent than the directly measured ones in Table 1, but the accuracy improves with a larger I_H current ratio. The obtained R_test is of the same value.

Similarly to Figure 23, the measured and normalized curves can also be rescaled to Z_threal by the power ratios calculated in Table 2, as shown in Figure 24:

The restored Ch3** is practically the same as its counterpart in Figure 23, as the power about the same 55 mΩ value was included in the correction. Rescaling of Ch2 is less exact, as the board resistance was extracted at lower precision; still, significant improvement is achieved in Ch2**, and even better is expected with a larger current ratio.

The elaborated test sequence also provided interesting results on the gate voltage change measured on Ch0; these results will be presented in the next paper.

7. Conclusions

With the advent of wide bandgap semiconductor devices, it became a must to adapt the existing thermal transient testing methodologies, originally developed for silicon material, to these new devices, such as GaN HEMT transistors.

First, proper heater and temperature sensor structures in HEMTs are to be found. Different constructions exist, and many of them lack the typical parasitic pn junctions, mostly used as sensors in similar silicon MOSFETs.

This way, the conductive channel in the HEMT became the typical heater and sensor used in thermal transient testing. It is of extremely low resistance, comparable to the wiring in test jigs, cabling and the package itself, which do not participate in the heating of the chips.

The fact that, in the test, a large portion of the applied power heats the external wiring rather than the device under test underlines remembering that the transient testing has two related but different targets. One is yielding peak system temperatures at various powering; the other is to provide partial thermal resistances and structural details near the active devices.

We have developed an analytical methodology to eliminate from the calculations of thermal descriptors those external resistances that distort the structural data gained from thermal tests. We have evaluated and demonstrated the validity of the method by measurements on actual samples. Application of the method demonstrated that restoration of true thermal properties became possible.