A Single-Phase Compact Size Asymmetrical Inverter Topology for Renewable Energy Application

Abstract

This paper presents an improved structure of an asymmetrical single-phase multilevel inverter topology with reduced device count. The proposed topology achieves 19 voltage levels at the output using only 12 power switches and 3 DC sources. The topology can be easily extended, resulting in a modular topology with more voltage levels at higher voltages. Moreover, the reliability analysis of the proposed converter results in a higher mean time to fault. The simulation is performed in MATLAB/Simulink, and a hardware prototype is developed to validate the circuit’s performance. A low-frequency Nearest Level Control PWM technique is implemented to generate switching signals and achieves 4.30% THD in output voltage. The PLECS software is used for power loss and efficiency analysis, resulting in a maximum efficiency of 99.08%. The proposed converter has been compared with other MLI topologies to demonstrate its superiority. The results indicate that the proposed topology has proven superior and outperformed other topologies in various parameters, making it suitable for renewable energy applications.

1. Introduction

Multilevel inverters (MLIs) are advanced versions of two-level inverters suitable for medium and high-power applications. They consist of a network of power semiconductors and capacitive voltage sources, which, when interconnected and regulated, can produce a stepped voltage waveform closer to sinusoidal [1,2]. The increasing interest in renewable energy sources, such as solar photovoltaic and wind energy, has prompted the development of innovative technologies that can integrate with these systems. MLIs offer higher power quality waveforms, reduced harmonic content, lower electromagnetic compatibility concerns, and a modular structure, making them attractive for various applications [3]. Their modular structure leads to a more economical life cycle, easier maintenance, easier scaling, and better fault tolerance. MLIs also find applications in various fields, including industrial drives, Flexible AC Transmission Systems, High-Voltage Direct Current transmission, marine propulsion, electric vehicles, and active filters [4,5].

The conventional topologies of the multilevel inverters, including Diode Clamped or Neutral Point Clamped, Flying Capacitor, and Cascaded H-bridge multilevel converter, have the disadvantage of having a large number of device counts as the output voltage increases. The exponential increase in device counts leads to a significant increase in the complexity and size of the MLI, potentially resulting in higher costs, increased losses, and more challenging control and thermal management [6]. However, having more levels allows for a smoother output voltage waveform, potentially reducing the size of the output filter [7]. The large number of device counts has drawn the focus of researchers to propose a topology having fewer DC sources, gate drivers, and switch requirements under the name of reduced switch count (RSC) MLIs [8]. The authors of [9] provide a thorough analysis and classification of RSC-MLI topologies, examining their structure, features, limitations, and suitability for specific applications. RSC-MLIs can be categorized as Generalized RSC-MLIs, stacked topologies, Unit-based MLIs, switched-capacitor (SC) RSC-MLIs, Transformer-based RSC-MLIs, and three three-phase topologies. Generalized RSC-MLIs include topologies having separate levels and polarity generators; there is a backend H-bridge converter, which limits their applications in high-voltage applications. Some of the topologies without a backend H-bridge converter are Envelope (E-type) type, Square T-type (ST-type), K-type, Packed U Cell (PUC) type, and Switched DC-sources (SDS). The E-type, ST-type, and K-type topologies are unit-based topologies that cannot be extended directly to generate higher levels but can be extended by cascading suitable modules. ST-type was derived from E-type, and there is a reduction in switch count in ST-type compared to E-type, while K-type topology utilizes capacitors to reduce the DC sources. The ST-type topology in [10] employs 4 DC sources, 2 of which are of the same variety, and 12 power switches to produce 17 levels at the output. The topology in [11] is a K-type (Kite Type) using 2 asymmetrical DC sources and 2 capacitors but also utilizing 14 power switches to generate 13 voltage levels. PUC and SDS are the topologies having ladder-based structures that come under Generalized RSC-MLI. The PUC topology in [12] and the SDS topology in [13] are the same except for the polarity of DC sources. In PUC, there is a consecutive addition and subtraction of DC sources in the conduction path. The limitation of PUC topology is that it always operates in buck mode, which means that the output voltage will always be less than the sum of the DC sources. SDS overcomes the disadvantages of PUC due to the opposite polarity of DC sources. Another class of MLI topology, known as Stacked inverters, enhances voltage levels by stacking MLIs, commonly used in three-phase and six-phase IM drives [14]. It produces 49 levels using three 17-level inverters, which involves cascading a Flying capacitor inverter with 3 cascaded H-bridges and stacking them using selector switches. In recent years, research on switched-capacitor topologies has gained significant attention due to their unique characteristics, including voltage boosting, self-balancing, and modular structure. These attributes have led to reductions in weight, size, and costs associated with such systems [15]. The authors of [16] have categorized SC MLIs based on (i) the number of levels in the output voltages, (ii) backend H-bridge (with or without H-bridge), (iii) DC supply (single/multiple DC supply), and (iv) capacitor balancing (Inherent capacitor voltage balancing or by using some switching techniques).

In [17], MLIs can also be classified into two main groups, transformer-less and transformer-based MLIs. The transformer-based reduced component count MLI produces 9 levels using eight switches, one transformer, and a single DC source. The transformer-less high-gain single DC source switched-capacitor multilevel inverter proposed in [18] generates a 13-level output voltage using 10 switches and three capacitors. Using a transformer in MLI enhances fault tolerance and decreases DC source usage but increases the weight and losses of the inverter. There is another way to categorize MLI topologies based on voltage ratio, which can be divided into symmetrical and asymmetrical MLI topologies. Symmetrical MLIs have an equal magnitude of DC voltage sources. The topologies that involve an unequal ratio of DC voltage sources are referred to as asymmetrical, and these are preferred to increase the output levels without increasing the device count. The topology in [19] generates 9 levels in symmetric operation and 17 levels in asymmetric mode by utilizing 10 power switches and 4 DC sources. The topology reported in [20] operates in both symmetrical and asymmetrical modes and produces 7 levels and 13 levels, respectively, by using 10 switches and 3 DC sources. This topology uses a backend H-bridge inverter as a polarity generator. The stress on the switches of a polarity generator is higher than that of a level generator. Topologies in [21,22] use capacitors to reduce the isolated DC voltage sources. The topology in [21] generates 17 levels using 4 capacitors, 2 DC sources, and 18 power switches, while the topology in [22] uses only 12 switches, keeping the number of DC sources and capacitors the same as in [21] with a lower per-unit total standing voltage.

The MLI topologies discussed above suffer from a high device count, increased system complexity, higher losses, and reduced reliability as the number of voltage levels increases. These limitations hinder their suitability for compact and cost-effective renewable energy applications. The objective of this work is to develop an improved structure of asymmetrical voltage source MLI topology with reduced component counts that can be easily cascaded to generate higher output voltage levels. Using fewer switches to generate multiple levels, MLI topology offers a more compact, cost-effective, and efficient solution for renewable energy applications. The main goal is to enhance the inverter efficiency by reducing switching losses, minimizing the switch count, and ensuring high power quality. The paper is organized into five sections. Section 2 presents the circuit description, switch ratings, generalized structure of the topology, modulation scheme, cost analysis, and reliability analysis of the converter. Section 3 provides the simulation and hardware results of the proposed topology for static and dynamic loading conditions. A detailed analysis of the power loss and efficiency is presented in Section 4. Section 5 provides a comparative analysis of the proposed topology with similar MLIs considering various parameters. Finally, the conclusion is given in Section 6.

2. Description of the Proposed Topology

2.1. Circuit Configuration

The circuit configuration of the proposed multilevel inverter topology is shown in Figure 1. It consists of 12 unidirectional IGBT switches and 3 DC sources in the ratio of V₁:V₂:V₃ = 1:2:6. The switches are unipolar, blocking voltage in one direction. There are nineteen different modes of operation, with

Table 1. Switching states of the proposed topology.

Vo	Switches States
	S1	S2	S3	S4	S5	S6	S7	S8	S9	S10	S11	S12
+1 V	1	0	1	0	0	0	0	0	1	1	0	1
+2 V	1	0	0	1	0	0	0	1	0	1	0	1
+3 V	1	0	1	1	0	0	0	0	0	1	0	1
+4 V	1	0	0	0	1	1	0	1	1	0	0	1
+5 V	1	0	1	0	1	1	0	0	1	0	0	1
+6 V	1	0	0	0	0	1	1	1	1	0	0	1
+7 V	1	0	1	1	1	1	0	0	0	0	0	1
+8 V	1	0	0	1	0	1	1	1	0	0	0	1
+9 V	1	0	1	1	0	1	1	0	0	0	0	1
0 V	1	0	0	0	0	0	0	1	1	1	0	1
−1 V	0	1	1	1	1	0	1	0	0	1	1	0
−2 V	0	1	0	1	0	0	0	1	0	1	1	0
−3 V	0	1	1	1	0	0	0	0	0	1	1	0
−4 V	0	1	0	0	1	1	0	1	1	0	1	0
−5 V	0	1	1	0	1	1	0	0	1	0	1	0
−6 V	0	1	0	0	0	1	1	1	1	0	1	0
−7 V	0	1	1	1	1	1	0	0	0	0	1	0
−8 V	0	1	0	1	0	1	1	1	0	0	1	0
−9 V	0	1	1	1	0	1	1	0	0	0	1	0

providing all switching combinations to achieve desired output voltage levels, where 1 indicates ‘’ON’’ and 0 indicates ‘’OFF’’ of a particular switch. The current conduction path for the positive half cycle is shown in Figure 2.

2.2. Voltage Rating of Switches

The voltage rating of the switch determines its capacity to handle maximum voltage stress in the OFF state. Total Standing Voltage (TSV) analysis is required to select appropriate switches. TSV is the cumulative value of the highest voltage stress across each switch and is crucial in determining converter cost. Higher TSV values require higher voltage ratings, potentially leading to higher costs. The value of the TSV for the proposed topology can be calculated as follows:

TSV = (V_S1 + V_S2 + V_S3 + V_S4 +… +V_S12)

(1)

For the proposed topology, the maximum voltage stress across each switch is given as follows:

V_S1 = V_S2 = V_S11 = V_S12 = (V₁ + V₂ + V₃) = 9 V

V_S10 = V₃ = 6 V

V_S6 = (V₃ − V₂) = 4 V

V_S4 = V_S5 = V_S7 = V_S9 = V₂ = 2 V

V_S3 = V_S8 = V₁ = 1 V

The value of TSV will be

TSV = 2 × (V₁) + 4 × (V₂) + V₃ + (V₃ − V₂) + 4 × (V₁ + V₂ + V₃) = 56 V

(2)

The maximum voltage stress across each switch is shown in Figure 3. The TSV per unit provides a convenient and effective method for analyzing and comparing the impact of voltage stresses. It is the ratio of TSV to the maximum output voltage.

$$\mathrm{T}\mathrm{S}\mathrm{V}\text{p.u.}\mathrm{ }=\mathrm{ }{\displaystyle \frac{56\mathrm{ }\mathrm{V}}{9\mathrm{ }\mathrm{V}}}=\mathrm{ }6.22$$

(3)

The proposed inverter achieves a slightly lower TSV. Importantly, most of the switches in the proposed circuit are subjected to relatively low blocking voltages (V, 2 V, or 4 V), and only a few devices are exposed to the full DC link stress. This favorable stress distribution enables the use of devices with lower voltage ratings for the majority of switches, thereby reducing conduction losses and overall inverter cost. The minimized TSV and selective use of high-voltage devices directly contribute to improved cost factor (CF) and efficiency of the proposed design.

2.3. Extended Generalized Structure

The proposed topology can be extended to achieve 19n-levels through cascaded operation. Its modular structure is shown in Figure 4. The total output voltage of the generalized structure, which is the sum of the voltages of all the basic units, can be written as

V_o = V_o,1 + V_o,2 + … + V_o,n

(4)

The relations for the generalized structure of the proposed topology for ‘n’ basic units are given as

N_L = 19n

(5)

N_IGBT = (N_L − 7n)

(6)

N_GD = (N_L − 7n)

(7)

N_DC = (N_L − n)/6

(8)

where N_L represents the number of output voltage levels, N_IGBT is the number of IGBT switches, N_GD is the number of gate driver circuits, and N_DC is the number of DC sources, respectively.

2.4. Modulation Strategy

Modulation techniques control the output voltage waveform, reduce harmonics, improve efficiency, and achieve better output quality [23]. This work uses a low-frequency Nearest Level Control (NLC) PWM technique for the switching operation of the proposed converter. Compared with Selective Harmonic Elimination (SHE), which can eliminate specific low-order harmonics but requires complex offline computation of switching angles, NLC is simpler, scalable, and easier to implement in real time. High-frequency modulation techniques such as sinusoidal or level-shifted PWM, which require higher switching frequencies, incur larger switching losses. The implementation of NLC, shown in Figure 5a, involves a sinusoidal reference wave N × M × Sin(ωt) is compared against the discrete DC voltage levels, where N is the number of positive voltage levels and M is the modulation index. When the reference wave crosses the constant level, the switching state changes, causing the inverter output to step to the nearest available voltage level. Figure 5b illustrates how the continuous reference is quantized into discrete levels, and the resulting logic outputs are mapped to gate driver signals for the corresponding switches. This ensures that each transition of the reference produces a well-defined switching event, enabling the inverter to synthesize a low-THD AC waveform with minimal switching frequency [24,25].

The choice of NLC is particularly motivated by its benefits for renewable energy systems. First, it operates with a very low switching frequency, which minimizes switching losses and thermal stress on the semiconductor devices, thereby enhancing efficiency and prolonging device lifetime. This is critical in photovoltaic and wind energy systems, where converters are required to run continuously with high reliability. Second, despite the low switching frequency, the proposed 19-level inverter produces a high-resolution staircase waveform, which results in a low THD, satisfying IEEE 519 harmonic standards. Thus, NLC achieves both efficiency and power quality simultaneously. Third, NLC reduces implementation complexity, requiring simpler hardware and control logic compared to high-frequency PWM techniques, which is advantageous for modular renewable energy inverters.

2.5. Cost Analysis

The cost factor is a crucial aspect in selecting the most suitable multilevel inverter (MLI) for optimal affordability. Reducing the number of IGBTs (N_IGBT), Driver Circuits (N_GD), Capacitors (N_C), Diodes (N_d), DC Sources (N_dc), and TSV_p.u. significantly decreases the circuit’s cost and complexity. The cost factor (CF) is formulated as [26]

Cost Factor (CF) = N_IGBT + N_GD + N_C + N_d + N_dc + αTSV_p.u.

(9)

where α represents the weighting factor and determines the emphasis on switch ratings, with the CF value calculated for α = 0.5 and α = 1.5 for the proposed topology.

CF (α = 0.5) = 30.11,

(10)

CF per level (α = 0.5) = 30.11/19 = 1.58

CF (α = 1.5) = 36.33,

(11)

CF per level (α = 1.5) = 36.33/19 = 1.91

2.6. Reliability Analysis

Reliability refers to the ability of power electronic converter systems to consistently perform their functions over a specified period and under various operating conditions. As the number of devices in MLI increases, it leads to an increase in converter faults. According to an industry-based survey, capacitors and power electronic switches are the most susceptible to faults [27]. A fault-tolerant MLI with a high device count is expected to be less reliable. The researchers use the following terms to determine the reliability of converters: Failure rate (λ), and mean time to failure (MTTF) [28]. The failure rate is a reliability index representing the rate at which the converter fails. It helps to determine the probability of failure over a specified period. The MTTF refers to the average expected time until the occurrence of the first failure in the converter. MTTF has an inverse relation with the failure rate. Two methods are used to estimate the reliability, including device count and device stress [29]. The precise method for estimating the reliability of the converter is the device stress method, which considers different factors of operating conditions. In this method, the failure rate of different components is calculated and then added to determine the failure rate of a complete circuit. The parameters for MTTF calculation are derived from the MIL-HDBK 217E standard [25], shown in

Table 2. Parameters for MTTF calculation (MIL-HDBK 217E standard).

Parameters	Values
${\mathsf{\lambda }}_{\mathrm{b}}$	0.00074
θjc	1 °C/W
θca	64 °C/W
Ta	30 °C/W
${\mathsf{\pi }}_{\mathrm{A}}$	1.5
${\mathsf{\pi }}_{\mathrm{Q}}$	1
${\mathsf{\pi }}_{\mathrm{E}}$	1
${\mathsf{\pi }}_{\mathrm{S}\mathrm{R}}$	1
Vs	0.6

. Since the proposed topology consists only of switches, the failure rate of the switch (λ_s) can be calculated as follows:

$${\mathsf{\lambda }}_{\mathrm{s}}=\mathrm{ }{\mathsf{\lambda }}_{\mathrm{b}}{\mathsf{\pi }}_{\mathrm{T}}{\mathsf{\pi }}_{\mathrm{A}}{\mathsf{\pi }}_{\mathrm{R}}{\mathsf{\pi }}_{\mathrm{S}}{\mathsf{\pi }}_{\mathrm{Q}}{\mathsf{\pi }}_{\mathrm{E}}· (\mathrm{F}\mathrm{a}\mathrm{i}\mathrm{l}\mathrm{u}\mathrm{r}\mathrm{e}\mathrm{s}/{10}^6·\mathrm{h})$$

(12)

where ${\mathsf{\lambda }}_{\mathrm{b}}$ is the base failure rate of the device and ${\mathsf{\pi }}_{\mathrm{T}}$ is a temperature coefficient that can be expressed as

$${\mathsf{\pi }}_{\mathrm{T}}={\mathrm{e}}^{-2114({\displaystyle \frac{1}{{\mathrm{T}}_{\mathrm{j}}+273}}-{\displaystyle \frac{1}{298}})}$$

(13)

where ${\mathrm{T}}_{\mathrm{j}}$ is the operating junction temperature of the switch that can be calculated as

$${\mathrm{T}}_{\mathrm{j}}={\mathrm{T}}_{\mathrm{c}}+{\mathsf{\theta }}_{\mathrm{j}\mathrm{i}}{\mathrm{P}}_{\mathrm{l}\mathrm{o}\mathrm{s}\mathrm{s}}$$

(14)

where ${\mathrm{T}}_{\mathrm{c}}$ and ${\mathsf{\theta }}_{\mathrm{j}\mathrm{i}}$ are represented as ambient temperature and junction to case and case to ambient thermal resistance, respectively. P_loss is the power loss, discussed in Section 4. The term ${\mathsf{\pi }}_{\mathrm{A}}$, ${\mathsf{\pi }}_{\mathrm{Q}}$, and ${\mathsf{\pi }}_{\mathrm{E}}$ is represented as the application factor, quality factor, and environmental factor, respectively. The term π_R is a power rating factor that has a relation with the power rating, ${\mathrm{P}}_{\mathrm{r}}$ of the switch and can be calculated as

$${\mathsf{\pi }}_{\mathrm{R}}={{\mathrm{P}}_{\mathrm{r}}}^{0.37}$$

(15)

Finally, the term ${\mathsf{\pi }}_{\mathrm{S}}$ is known as the voltage stress factor of the switch; it depends on V_s, which is the ratio of the applied collector-to-emitter voltage to the collector-to-emitter voltage in the OFF state of the switch. The ${\mathsf{\pi }}_{\mathrm{S}}$ can be estimated as

$${\pi }_s=0.0045e^{3.1V_s}$$

(16)

For the proposed topology, the calculated value of failure rate (λ_s) is 0.06216 Failures/hour, and the MTTF can be calculated as

$$\mathrm{M}\mathrm{T}\mathrm{T}\mathrm{F}={\displaystyle \frac{1}{{\mathsf{\lambda }}_{\mathrm{s}}}}=16.08·({10}^6\times \mathrm{h}\mathrm{o}\mathrm{u}\mathrm{r}\mathrm{s}/\mathrm{f}\mathrm{a}\mathrm{i}\mathrm{l}\mathrm{u}\mathrm{r}\mathrm{e})$$

(17)

The device failure rate and Mean Time to Failure (MTTF) are critical metrics for demonstrating the superiority of the proposed topology and optimizing its design. A lower failure rate indicates improved reliability, as it reduces component malfunction over time. A higher MTTF showcases the longevity of the proposed design. This indicates that the proposed topology can operate reliably for a longer duration before encountering failures. Furthermore, these reliability insights enable design optimization by guiding component selection, stress reduction, and thermal management techniques.

3. Results and Discussion

3.1. Simulation Results

The proposed topology was simulated in MATLAB/Simulink for both static and dynamic loading conditions with the parameters listed in

Table 3. Simulation Parameters.

Parameters	Values
Voltages	V1 = 50 V, V2 = 100 V, V3 = 300 V
Switching frequency	50 Hz
Switch	IGBT
Resistive load	50 Ω, 100 Ω
Inductive load	40 mH, 80 mH
Modulation index (MI)	1, 0.8, 0.6

. The output voltage and current waveform are in phase for a fixed R of 100 Ω, as depicted in Figure 6a. The resultant output voltage waveform has a 19-level with a peak voltage of 450 V and a current waveform with a peak of 4.5 A. As the load changes to 100 Ω + 40 mH, the current waveform becomes sinusoidal, and a phase difference appears due to the inductive nature of the load shown in Figure 6b. The harmonic spectrum of output voltage and current is depicted in Figure 6c. The output voltage and current have a THD of 4.30% and 0.47%, respectively.

Load conditions in real-world scenarios can fluctuate dynamically due to various applications like industrial machinery operations, renewable energy systems, household use, and electric vehicles. The inverter’s stability was evaluated by simulating load transitions to ensure its reliability across various applications. The output voltage and current waveform for variable R form No-load to 100 Ω and then to 50 Ω are shown in Figure 7a. For dynamic change in RL load from No-load to 100 Ω + 40 mH and then to 50 Ω + 40 mH, the output voltage and current waveform are shown in Figure 7b. The proposed circuit operates well under both dynamic conditions, as evidenced by the change in current voltage. The waveforms for variable Power Factor (PF) are shown in Figure 7c. In certain cases, the modulation index of the converter could change due to faults or control system errors. To assess the dynamic stability of the converter, simulations were conducted for different modulation indices ranging from 1 to 0.8, and subsequently to 0.6. Upon transitioning from a modulation index of 1 to 0.8, the voltage levels decreased from 19 to 15. Further reducing the modulation index from 0.8 to 0.6 led to a subsequent decrease in voltage levels from 15 to 11. Figure 7d displays voltage and current waveforms for varying modulation index (MI). Figure 8 shows the voltage stress waveform across different switches.

It is important to note that reducing the MI decreases the number of available output levels, which increases the step size in the staircase waveform. This results in a higher harmonic content and an increase in the total harmonic distortion (THD) of the output voltage. While the proposed topology produces low THD (4.3%) at MI = 1, the THD rises as MI decreases, reflecting a trade-off between DC source utilization and power quality. In renewable energy applications, especially in grid-connected systems, this drawback can affect compliance with harmonic standards if MI is significantly reduced. However, even at MI = 0.6, the proposed inverter still provides 11 levels, ensuring that the waveform quality remains superior compared to conventional two-level or three-level inverters. Additionally, filtering and control strategies can be employed to mitigate the negative impact on power quality when operating at reduced MI.

3.2. Hardware Results

The practical feasibility of the proposed topology has been verified by developing a hardware prototype in the laboratory, shown in Figure 9. The experimental setup utilizes a TMS320F28379D DSP board for gate pulse generation, which provides the required PWM channels, an IGBT FGA25N120 for the power switch, and a TLP250H optocoupler IC for the gate driver circuit. The magnitude of the DC source voltages selected for hardware testing is 4.5 V, 9 V, and 27 V. The parameters used for experimental testing are shown in

Table 4. Experimental Parameters.

Parameters/Device	Values
DC source voltages	V1 = 4.5 V, V2 = 9 V, V3 = 27 V
Switching frequency	NLC-PWM @ 50 Hz
Switch	IGBT/FGA25N120/1200 V, 25 A
Controller	TMS320F28379D
Gate Driver IC	TLP250H
Resistive load	40 Ω, 80 Ω
Inductive load	90 mH, 120 mH
Modulation index (MI)	1, 0.8, 0.6

.

It is important to note that the hardware prototype employs a fundamental switching frequency of 50 Hz. This is because the NLC generates the staircase waveform directly at the fundamental frequency, avoiding high-frequency PWM switching. The main advantage of this approach is a substantial reduction in switching losses and thermal stress, which enhances efficiency and device lifetime. Although 50 Hz is considered low compared to conventional PWM inverters operating in the kHz range, the trade-off is justified for medium- and high-power renewable energy applications where efficiency is prioritized. Furthermore, future implementations could take advantage of wide-bandgap (WBG) devices such as SiC or GaN. These devices offer faster switching capability, lower switching losses, and improved thermal performance, which would allow higher-frequency operation while maintaining efficiency and enabling more compact passive components.

For a fixed resistive load of 40 Ω, the output voltage and current waveform are shown in Figure 10a, resulting in 19 levels of staircase output voltage. Figure 10b shows the output voltage and current waveform for a fixed RL load of 40 Ω + 90 mH. The output current becomes sinusoidal when the nature of the load is inductive. The proposed topology is also verified in experimental testing for dynamic changes in load. The proposed circuit successfully handles dynamically changing loads, as shown in Figure 10c,d. The output voltage and current waveforms show satisfactory performance for variable R load from 80 Ω to 40 Ω and variable RL load from 80 Ω + 90 mH to 40 Ω + 120 mH. The topology is also varied for dynamic change in the modulation index (MI) from 1 to 0.8 and then 0.6, as shown in Figure 11.

4. Power Loss Analysis

Power loss analysis is crucial for designing topologies as it directly impacts converter efficiency and generates heat within components, leading to component degradation, reduced lifespan, and even failure. A power electronic switch operates in three modes: blocking mode, conduction mode, and switching mode. However, there are negligible losses in blocking mode. Therefore, losses mainly occur during switching mode and conduction mode. Switching losses occur during the transitions of the semiconductor devices in the converter, including turn-on and turn-off losses. Conduction losses occur when current flows through the ON-state semiconductor devices. These losses of IGBTs with antiparallel diodes are due to on-state voltage drop and turn-on resistance. These losses increase with the number of switches in the conduction state. Conduction losses (P_c) are more pronounced at low switching frequencies. The following equations can be used for the estimation of losses [25].

$${\mathrm{P}}_{\mathrm{c},\mathrm{I}\mathrm{G}\mathrm{B}\mathrm{T}}={\mathrm{V}}_{\mathrm{O}\mathrm{N},\mathrm{I}\mathrm{G}\mathrm{B}\mathrm{T}}\mathrm{i}\left(\mathrm{t}\right)+{\mathrm{R}}_{\mathrm{I}\mathrm{G}\mathrm{B}\mathrm{T}}{\mathrm{i}}^{\mathsf{\beta }}\left(\mathrm{t}\right)$$

(18)

$${\mathrm{P}}_{\mathrm{c},\mathrm{D}\mathrm{i}\mathrm{o}\mathrm{d}\mathrm{e}}={\mathrm{V}}_{\mathrm{O}\mathrm{N},\mathrm{D}\mathrm{i}\mathrm{o}\mathrm{d}\mathrm{e}}\mathrm{i}\left(\mathrm{t}\right)+{\mathrm{R}}_{\mathrm{D}\mathrm{i}\mathrm{o}\mathrm{d}\mathrm{e}}{\mathrm{i}}^2\left(\mathrm{t}\right)$$

(19)

where ${\mathrm{V}}_{\mathrm{O}\mathrm{N},\mathrm{I}\mathrm{G}\mathrm{B}\mathrm{T}}$ and ${\mathrm{V}}_{\mathrm{O}\mathrm{N},\mathrm{D}\mathrm{i}\mathrm{o}\mathrm{d}\mathrm{e}}$ represent the ON-state voltage drops of the IGBT and antiparallel diode, respectively. ${\mathrm{R}}_{\mathrm{I}\mathrm{G}\mathrm{B}\mathrm{T}}$ and ${\mathrm{R}}_{\mathrm{D}\mathrm{i}\mathrm{o}\mathrm{d}\mathrm{e}}$ denote the equivalent resistances of the IGBT and the diode, and i(t) is the conduction current. The term β is a constant determined by the datasheet of the switch. The total conduction losses of the converter can be estimated as

$${\mathrm{P}}_{\mathrm{c}}={\sum }_{\mathrm{j}=1}^{{\mathrm{N}}_{\mathrm{I}\mathrm{G}\mathrm{B}\mathrm{T}}}{\displaystyle \frac{1}{2\mathsf{\pi }}}{\int }_0^{2\mathsf{\pi }}\left\{{\mathrm{V}}_{\mathrm{O}\mathrm{N},\mathrm{I}\mathrm{G}\mathrm{B}\mathrm{T},\mathrm{j}}\mathrm{i}\left(\mathrm{t}\right)+{\mathrm{R}}_{\mathrm{I}\mathrm{G}\mathrm{B}\mathrm{T}}{\mathrm{i}}^{\mathsf{\beta }}\left(\mathrm{t}\right)\right\}\mathrm{d}\mathrm{t}+{\sum }_{\mathrm{k}=1}^{{\mathrm{N}}_{\mathrm{D}\mathrm{i}\mathrm{o}\mathrm{d}\mathrm{e}}}{\displaystyle \frac{1}{2\mathsf{\pi }}}{\int }_0^{2\mathsf{\pi }}\left\{{\mathrm{V}}_{\mathrm{O}\mathrm{N},\mathrm{D}\mathrm{i}\mathrm{o}\mathrm{d}\mathrm{e},\mathrm{k}}\mathrm{i}\left(\mathrm{t}\right)+{\mathrm{R}}_{\mathrm{D}\mathrm{i}\mathrm{o}\mathrm{d}\mathrm{e}}{\mathrm{i}}^2\left(\mathrm{t}\right)\right\}\mathrm{d}\mathrm{t}$$

(20)

Switching losses arise due to the delay in the time transition of switches. Ideally, the switch should instantaneously change its state, but practically, it takes a small duration to change its state, causing energy dissipation in the form of heat. These losses are higher at high switching frequencies. Assuming the variation in voltage and current to be linear during the transition, the switching loss (P_sw) for the fundamental frequency, f, can be determined by the given equation [30]:

$${\mathrm{P}}_{\mathrm{s}\mathrm{w}}=\left\{{\sum }_{\mathrm{k}=1}^{{\mathrm{N}}_{\mathrm{s}\mathrm{w}}}\left({\mathrm{E}}_{\mathrm{O}\mathrm{N},\mathrm{k}}{\mathrm{T}}_{\mathrm{O}\mathrm{N},\mathrm{k}}+{\mathrm{E}}_{\mathrm{O}\mathrm{F}\mathrm{F},\mathrm{k}}{\mathrm{T}}_{\mathrm{O}\mathrm{F}\mathrm{F},\mathrm{k}}\right)\right\}\times \mathrm{f}$$

(21)

Here, E_ON,k and E_OFF,k represents the energy loss during turn-on and turn-off in one cycle for the kth IGBT and diode, respectively. T_ON,k and T_OFF,k indicate the number of turn-on and turn-off cycles for the kth IGBT and diode, respectively. Now, total losses P_{Total Loss} are given by

P_{Total Loss} = P_c + P_sw

(22)

The efficiency of the converter gives an idea about its performance and can be calculated using the equation:

$$\mathsf{\eta }={\displaystyle \frac{{\mathrm{P}}_{\mathrm{o}\mathrm{u}\mathrm{t}}}{{\mathrm{P}}_{\mathrm{o}\mathrm{u}\mathrm{t}}+{\mathrm{P}}_{\mathrm{T}\mathrm{o}\mathrm{t}\mathrm{a}\mathrm{l}\mathrm{L}\mathrm{o}\mathrm{s}\mathrm{s}}}}\times 100\%$$

(23)

Thermal modeling was conducted using PLECS 4.1.2 software, utilizing IGBT/diode IKW75N65EL5 manufactured by Infineon. The manufacturer’s datasheet provides multi-dimensional lookup tables for accurately calculating losses in power semiconductor devices. The conduction and switching losses were evaluated for three different loading conditions, as shown in Figure 12a,b. The results indicate that switching losses are smaller than conduction losses since the circuit was implemented using a low switching frequency. Figure 12c shows the variation in efficiency with output power. The proposed converter achieves a maximum efficiency of 98.08% at an output voltage of 250 W.

5. Comparative Analysis

This section presents a comparative evaluation of the proposed topology with several reported asymmetrical multilevel topologies. The comparison considers the number of output levels (N_L), number of IGBTs (N_IGBT), number of gate drivers (N_gd), number of capacitors (N_C), number of DC sources (N_dc), per-unit Total Standing Voltage (TSV_p.u.), cost factor per level (CF/N_L) for α = 0.5 and α = 1.5, and N_IGBT/N_L. These parameters jointly determine the technical and economic suitability of an inverter topology.

Table 5. Comparison with other asymmetrical topologies.

Topology	NL	NIGBT	NIGBT/NL	Ngd	Ndc	TSVp.u.	NC	CF/NL (α = 0.5)	CF/NL (α = 1.5)
[31]	17	12	0.70	10	4	6	0	1.7	2.05
[32]	17	12	0.70	12	2	6.6	3	1.9	2.28
[33]	17	16	0.94	14	4	6.5	4	2.42	2.8
[34]	17	18	1.05	18	8	6.5	0	2.77	3.16
[31]	17	12	0.70	10	4	6	0	1.69	2.05
[35]	21	16	0.76	16	7	6.7	0	2.01	2.33
[36]	21	10	0.47	10	6	4	0	1.33	1.52
[37]	19	18	0.94	18	2	4.9	4	2.33	2.59
[38]	19	18	0.94	18	6	4	0	2.31	2.52
[39]	19	11	0.57	10	5	6.25	0	1.53	1.86
Proposed	19	12	0.63	12	3	6.22	0	1.58	1.91

highlights that asymmetrical topologies with 17 levels [31,32,33,34] employ a relatively large device count and generally exhibit higher TSV values. Such characteristics increase complexity, cost, and switching losses, limiting their practical scalability. In contrast, more recent designs such as [35,36] with 21 levels demonstrate improved performance: [35] reduces N_IGBT/N_L but requires 7 DC sources, which complicates implementation, whereas [36] achieves an excellent TSV_p.u. value of 4.0 along with favorable CF/N_L, but still relies on 6 DC sources. Thus, while [36] is attractive from a voltage stress perspective, its need for additional sources increases system cost and limits compactness. For 19-level inverters, topologies in [37,38] use 18 switches, leading to a high device-per-level ratio (0.94) and higher CF, though they achieve lower TSV_p.u. compared to our design. The topology in [39] offers a lower N_IGBT/N_L (0.57) and competitive CF/N_L, but this comes at the expense of requiring five DC sources and incurring a relatively high TSV_p.u. value of 6.25.

The proposed topology, generating 19 levels with only 12 switches and 3 DC sources, achieves a favorable balance across all metrics. Its N_IGBT/N_L ratio (0.63) and CF/N_L (1.58–1.91) compare well against alternatives, while its TSV_p.u. of 6.22 remains acceptable for practical device ratings. Although not the lowest TSV reported, the distribution of voltage stress, where most switches experience lower voltages (V, 2 V, or 4 V) enables the use of lower-rated and lower-cost devices for the majority of switches. This reduces conduction losses and improves overall efficiency.

In summary, the comparison reveals that no single topology dominates across all parameters. Designs like [36] excel in TSV reduction but require more DC sources, while others, such as [39], reduce the switch-to-level ratio but incur higher voltage stress. The strength of the proposed topology lies in offering a compact, modular, and cost-effective structure with reduced device count, competitive TSV, and low-cost factor, making it especially well-suited for renewable energy applications where simplicity, efficiency, and scalability are key priorities.

6. Application of the Proposed Topology

The proposed inverter topology is a key component in enhancing the efficiency and integration of renewable energy systems. It provides a flexible and reliable power supply by enabling the simultaneous connection of renewable energy sources like solar panels, wind turbines, and fuel cells, as shown in Figure 13. They convert the direct current (DC) from these sources into high-quality alternating current (AC) with multiple voltage levels, reducing harmonics and improving power quality. This is particularly beneficial for grid-connected systems, where the inverter can stabilize the power supply and improve overall efficiency [40]. In standalone systems, especially in remote areas without grid access, the proposed topology can combine different renewable sources to ensure a consistent power supply. Additionally, the proposed topology is essential in smart grids and electric vehicle charging stations [41,42,43]. The proposed converter optimizes the use of available renewable energy and reduces dependence on conventional power sources [44,45,46]. Despite challenges [47,48,49] such as complexity and cost, the benefits of improved power quality, scalability, and efficient energy management make the proposed topology a vital component in advancing renewable energy integration.

7. Conclusions

This paper presents an improved structure of a single-phase asymmetrical multilevel inverter topology with extension capability to produce higher levels in the output voltage waveforms. The proposed topology generates 19 levels at the output by using 12 unidirectional switches and 3 DC sources. The proposed MLI topology is thoroughly analyzed, and its performance is evaluated using MATLAB/Simulink and verified experimentally under different loading conditions. The proposed converter achieved a THD of 4.3% in output voltage, which complies with the IEEE 519 harmonic standard, ensuring high power quality. To demonstrate the practical applicability of the proposed topology for renewable energy applications. The dynamic performance under varying load conditions highlights its stability and reliability. The reliability analysis of the proposed topology reveals a higher mean time to fault value (MTTF), indicating robustness and suitability for long-term operation. Additionally, the power loss analysis shows a maximum efficiency of 99.08% with a detailed distribution of losses across all switches under different loading conditions. The results confirm that the proposed topologies offer high efficiency, low harmonic distortion, and robust performance under different loading conditions, making them a promising solution for various renewable energy applications.