C_OSS Losses in Resonant Converters

Abstract

High efficiency and high power density are key targets in modern power conversion. Operating power converters at high switching frequencies enables the use of smaller passive components, which, in turn, facilitate achieving high power density. However, the concurrent increase in switching frequency and power density leads to efficiency and overheating issues. Soft switching techniques are typically employed to minimize switching losses and significantly improve efficiency by reducing power losses. However, the hysteresis behavior of the power electronics devices’ output capacitance, C_OSS, is the cause of regrettable losses in Super-Junction (SJ) MOSFETs, SiC MOSFETs, and GaN HEMTs, which are usually adopted in soft switching-based conversion schemes. This paper reviews the techniques for measuring hysteresis traces and power losses, as well as the understanding of the phenomenon to identify current research trends and open problems. A few studies have reported that GaN HEMTs tend to exhibit the lowest hysteresis losses, while Si superjunction (SJ) MOSFETs often show the highest. However, this conclusion cannot be generalized by comparing the results from different works because they are typically made across devices with different (when the information is reported) breakdown voltages, on-state resistances, die sizes, and test conditions. Moreover, some recent investigations using advanced TCAD simulations have demonstrated that newer Si-SJ MOSFETs employing trench-filling epitaxial growth can achieve significantly reduced hysteresis losses. Similarly, while multiple studies confirm that hysteresis losses increase with increasing dv/dt and decreasing temperature, the extent of this dependence varies significantly with device structure and test methodology. This difficulty in obtaining a general conclusion is due to the lack of proper figures of merit that account for hysteresis losses, making it problematic to evaluate the suitability of different devices in resonant converters. This problem highlights the primary current challenge, which is the development of a standard and automated method for characterizing C_OSS hysteresis. Consequently, significant research effort must be invested in addressing this main challenge and the other challenges described in this study to enable power electronics researchers and practitioners to develop resonant converters properly.

1. Introduction

The industrial market is increasingly demanding high-efficiency and high-power density power electronics converters while minimizing electromagnetic interference issues to comply with electromagnetic compatibility standards [1]. In this case, typical hard-switching converters are unsuitable because they present huge switching losses, large size and weight of passive components, and significant electromagnetic emissions [2,3]. On the contrary, resonant converters are ideal candidates [4]. Wide-bandgap power devices exhibit features such as exceptional drift velocity, high breakdown fields, high-frequency operation, and the ability to withstand high temperatures, making them suitable for this field [5]. Silicon Super-Junction (SJ) MOSFETs can also achieve an efficiency of up to 94% in resonant converters, where they are widely used thanks to their good performance/cost ratio [6].

Zero-voltage switching (ZVS) is a key operating condition commonly employed in resonant converters to improve efficiency by reducing switching losses. ZVS occurs when the switching device turns on once the voltage across it is zero, eliminating the energy dissipated during switching [7]. In a resonant converter, the resonant tank components and the switching frequency are appropriately chosen to allow the discharge of the output capacitance, C_OSS, during the dead-time. More specifically, the switching frequency is determined to operate the tank in the inductive region, allowing the inductive current to discharge C_OSS before the device is turned on [8]. Therefore, the removal of C_OSS losses obtained by the ZVS condition has been a widely accepted assumption for a long time.

A decade ago, an energy loss phenomenon associated with the C_OSS of SJ MOSFETs used in ZVS converters was uncovered, which upset the common assumption [9]. Further investigations have proved that these unexpected switching losses are due to the C_OSS hysteresis phenomenon, which is not detectable with the standard small-signal measurement of C_OSS as a function of drain-source voltage, V_DS [10]. Consequently, this phenomenon cannot be accounted for by considering the parameters typically available in the datasheet [9,10]. Subsequent studies have shown similar losses in wide-bandgap power devices used in resonant converters [11,12,13].

This work analyzes all aspects of C_OSS losses in ZVS that have been investigated to date. In detail, Section 2 first recalls the standard techniques adopted to provide C_OSS information in manufacturers’ datasheets, then it analyzes the different measurement techniques and circuits adopted for tracing the C_OSS hysteresis trace. Section 3 first explains how to use the C_OSS hysteresis trace to evaluate C_OSS losses under ZVS and then describes other methods and circuits proposed so far for loss estimation. Section 4 presents the physical reasons behind the C_OSS hysteresis loss phenomenon based on studies that relate experimental results to simulations performed through technological computer-aided design (TCAD) tools. Finally, the main conclusions are reported in the last section.

2. C_OSS Hysteresis Measurement

2.1. Datasheet Information About C_OSS and Switching Losses

Figure 1a reports the MOSFET structure, highlighting the device’s parasitic capacitances. A typical picture of a MOSFET datasheet reporting the values of the C_ISS, C_OSS, and C_RSS parasitic capacitances as a function of V_DS is shown in Figure 1b [14]. In particular, the relation between the device parasitic capacitances and C_OSS is:

$$Coss=C_{GD}+C_{DS}$$

(1)

During C_OSS measurement, the curve tracer shorts the gate with the source to avoid any contribution from the gate-source capacitance, $C_{GS}$. To achieve the C_OSS value for a given V_DS value, $\widetilde{V_{DS}}$, first the curve tracer sets a DC bias voltage equal to $\widetilde{V_{DS}}$ [15]. Then, the curve tracer superimposes a small AC voltage (typically with an amplitude of tens of mV and a frequency, f, of 1 MHz). After that, the curve tracer acquires the AC current response due to the voltage perturbation [16]. The voltage and current phasors, $\dot{V}$ and $\dot{I}$, are used for estimating the device impedance and, consequently, the value of C_OSS, as follows:

$$Z_{OSS}\left(\widetilde{V_{DS}}\right)={\displaystyle \frac{\dot{V}}{\dot{I}}}$$

(2)

$$C_{OSS}\left(\widetilde{V_{DS}}\right)=\left|{\displaystyle \frac{1}{2\pi ·f·Z_{OSS}\left(\widetilde{V_{DS}}\right)}}\right|$$

(3)

In Equation (2), the impedance is almost an imaginary quantity as its real part is negligible. Once the C_OSS value is recorded, the curve tracer sets a new DC bias voltage and repeats the previous procedure. Usually, the bias is swept from 0 V up to a preset voltage.

The traces of C_OSS and the other parasitic capacitances are useful for predicting MOSFET behavior at the converter design stage. To this end, device manufacturers typically provide a SPICE netlist that models the parasitic capacitance and other device characteristics, enabling designers to foresee the converter behavior through circuit simulation [17]. However, as a first design step, it is helpful to adopt equivalent linear capacitance, such as energy-related and time-related capacitances [18,19].

The energy-equivalent capacitance, C_OSS,E, is the constant capacitance of a linear capacitor that stores the same energy of C_OSS charged from 0 V to a specific voltage, e.g., 80% of the breakdown voltage, V_DS,BR. Therefore, equating the energy stored by C_OSS,E with C_OSS, the value of the energy-equivalent capacitance is obtained as follows:

$$C_{OSS,E}={\displaystyle \frac{2}{{\left[0.8·V_{DS,BR}\right]}^2}}\underset{0}{\overset{0.8·V_{DS,BR}}{\int }}{C}_{OSS}\left(V_{DS}\right)·V_{DS}d{V}_{DS}$$

(4)

The time-equivalent capacitance, C_OSS,T, is the constant capacitance of a linear capacitor that lasts the same time as C_OSS to reach a voltage (e.g., 80% of V_DS,BR) from 0 V, with the test circuit and the associated waveforms proposed by International Rectifier usually adopted to compute it [18]:

$$C_{OSS,R}={\displaystyle \frac{1}{\mathit{ln}\left(0.2\right)}}\underset{0}{\overset{0.8·V_{DS,BR}}{\int }}{\displaystyle \frac{C_{OSS}\left(V_{DS}\right)}{V_{DS}-V_{DS,BR}}}d{V}_{DS}$$

(5)

As mentioned, C_OSS plays a key role in the different switching losses achieved in hard and soft switching, thus affecting the efficiency of power electronic converters. Figure 2 shows the different behavior of the C_OSS voltage in hard and soft switching [20].

In hard switching, the voltage (blue solid line) and the current (black dashed line) overlap during the turn-on transition, thereby causing high switching losses that reduce efficiency and increase temperature, which, in turn, leads to lower reliability. It is worth noting that the higher the switching losses, the higher the temperature leaps, and the lower the lifetime. During the off state, C_OSS is kept at a high voltage, the value of which depends on the application. This voltage provokes a power loss until the capacitance discharges when the driver turns on the MOSFET and the current increases (Figure 2—Hard Switching).

On the other hand, in the case of ZVS, the charge stored in C_OSS is discharged before the MOSFET turns on. This discharge is typically achieved by employing a resonant tank that allows the voltage across C_OSS to drop near zero before the driver turns on the MOSFET. Avoiding (or reducing) overlap between the voltage and the current implies dramatically abating the switching losses, thus improving efficiency and reliability.

The crucial difference between hard switching and ZVS lies in how they handle the energy stored in C_OSS at the turn-on. In hard switching, C_OSS discharges abruptly through the switch, causing heat. In ZVS, the stored energy is transferred to the circuit, thus minimizing energy loss. Therefore, the presence of power losses in ZVS is an unexpected and undesired event, and they are due to C_OSS hysteresis.

However, although C_OSS hysteresis plays a critical role in the performance of power MOSFETs, particularly in resonant converters, its associated hysteresis losses are not typically disclosed in manufacturer datasheets. Standard datasheets provide the aforementioned C_OSS values characterized at small-signal frequencies (1 MHz) as a function of the drain-source voltage. However, these values do not capture the energy dissipation due to charge–discharge asymmetry. This omission poses a challenge for accurate loss modeling and efficiency optimization in high-performance resonant converters. Although some manufacturers provide application notes or technical papers that discuss these losses qualitatively or offer indirect characterization under ZVS conditions, the lack of standardized reporting means that designers must often rely on empirical measurements, like those described in the following, to estimate hysteresis losses. Therefore, significant research effort must be focused on developing a standard for C_OSS hysteresis characterization.

2.2. Circuits for C_OSS Hysteresis Tracing

The Sawyer–Tower method is the only experimental method used to evaluate the hysteresis of C_OSS, which is represented by the Q_OSS–V_DS trace [10]. It has been proficiently used to characterize and investigate C_OSS hysteresis in Si-SJ MOSFET, SiC MOSFET, and GaN HEMT devices [11]. The Sawyer–Tower branch (STB) is the core of the measurement circuit [22]. Different approaches, discussed in the following, have been adopted to supply the STB. Figure 3 reports the STB and indicates the supply point in red.

Regardless of the supplying circuit, the STB is a voltage divider: the voltage drops across the linear (i.e., constant) capacitance, C_REF, and C_OSS of the device under test (DUT), which is always kept off by shorting the gate and source terminals. The linear capacitance functions as a charge sensor, enabling an easy estimate of the charge stored in the DUT’s C_OSS over time. More specifically, if the initial charge stored in C_REF and the DUT is null before the STB is supplied, and if they are fed with the same current, the charge variation is the same once the STB is supplied. Therefore, they always store the same amount of charge, that is:

$$Q_{OSS}=Q_{REF}=C_{REF}{V}_{REF}$$

(6)

The measurement setup is reported in Figure 4.

From Figure 4, it is apparent that:

$$\left\{\begin{array}{c}{V}_{REF}=V_X\\ V_{DS}=V_Y{ - V}_X\end{array}\right.$$

(7)

and then:

$$\left\{\begin{array}{c}{Q}_{OSS}=C_{REF}{V}_X\\ V_{DS}=V_Y{ - V}_X\end{array}\right.$$

(8)

thus, the Q_OSS–V_DS curve (see Figure 5) can be traced using an oscilloscope.

C_REF must be linear with low losses and an admissible voltage range equal to the amplitude of the voltage applied to the STB. Experimental tests have shown that the value must be 5–10 times larger than the maximum C_OSS value (which is achieved at V_DS = 0 V) [11,23,24]. In this way, the greatest fraction of the voltage applied to the STB drops across the DUT.

Three approaches have been proposed to supply the STB for characterizing the hysteresis. The first uses a sine wave generator with a power amplifier [10,11,13,22,23,25,26,27]. Another approach supplies the STB with a trapezoidal wave using a half-bridge topology [12,24]. Finally, a recent approach generates a pulse through a resonant topology thanks to an inductor and a switch to supply the STB [28]. All of the methods will be discussed in the following subsections.

Circuit modeling of C_OSS hysteresis is useful for simulating the device behavior in ZVS converters. These simulations are helpful for converter designers to predict the converter’s performance and to detect potential issues. However, device manufacturers usually provide a SPICE netlist that models the parasitic capacitance trend reported in the datasheet (e.g., Figure 1b).

A first circuit model [29] that enabled the emulation of energy losses due to C_OSS hysteresis is reported in Figure 6a. The hysteresis is modeled with the component inside the dotted area. The values of two non-linear capacitors, C_DS and C_DG, are obtained from the datasheet. By contrast, the values of the two linear resistors are appropriately set to match the energy losses due to the hysteresis. These values are found using a genetic algorithm. However, this circuit model is unable to predict the waveforms by simulation, thus presenting a key limitation of this approach. A better circuit model [30] capable of emulating the C_OSS hysteresis trace is shown in Figure 6b. A non-linear equivalent series resistor with C_OSS, as specified in the datasheet, is adopted. Figure 6c reports the hysteresis obtained using a circuit simulation, the experimental counterpart of which is reported in Figure 5b. From the comparison, it is apparent that a merit of this circuit model is that it qualitatively replicates the experimental result. On the other hand, the precision level is not enough for accurate prediction. Moreover, no SPICE netlist is provided.

The use of two different look-up tables, one for charge and one for discharge, has also been proposed [31] for SPICE modeling of C_OSS hysteresis in SJ-MOSFETs. Although this approach is widely used for modeling C_OSS reported in the datasheet, no details are provided about the application related to the look-up tables.

Given the importance of using accurate circuit models at the design stage and the limited availability of faithful and complete circuit models in literature, further research effort is necessary in this area.

2.2.1. Power Amplifier Sawyer–Tower Circuit

The first circuit adopted to achieve the Q_OSS–V_DS curve combined a sine wave generator with a power amplifier to supply the STB (Figure 7). In the achieved topology, i.e., the power amplifier Sawyer–Tower circuit (PASTC), the STB is subjected to a sinusoidal voltage amplified through the power amplifier [10].

However, to perform the measurement using an oscilloscope, it is necessary to introduce a decoupling capacitor, C_DIV, as shown in Figure 8. This capacitor involves a capacitive divider to protect the oscilloscope probe from the high voltages applied to the DUT drain. Typically, 1pF is the capacitance adopted [25].

Measurements are performed once steady-state conditions are met when the DC bias voltage across C_REF reaches one-half of the peak-to-peak input voltage (i.e., the voltage between the red point and ground in Figure 3) and the body diode of the MOSFET is reverse-biased. Figure 9 shows the first hysteresis curve reported in the literature, along with a comparison of the output capacitance values from the datasheet with those achieved using the PASTC, both the small-signal and large-signal ones. The equations for evaluating the small-signal, C_OSS,ST, and large-signal, C_OLS,ST, capacitances from the hysteresis curve achieved using an STB are:

$$C_{OSS,ST}\left(V_{DS}\right)={\displaystyle \frac{d{Q}_{OSS}}{d{V}_{DS}}}$$

(9)

$$C_{OLS,ST}\left(V_{DS}\right)={\displaystyle \frac{Q_{OSS}}{V_{DS}}}$$

(10)

The PASTC is easy to implement and can reach high frequencies of up to 35 MHz on SiC and GaN devices [13]. Furthermore, PASTC presents high accuracy since no current measurement is necessary, and only two voltage measurements are taken. The DUT and C_REF are the only components involved in the measurement; no external components, such as an inductor, switch, or control circuit, are used in the setup [22].

Although PASTC presents these good features and has been the most widely adopted approach, it is affected by the following disadvantages. The voltage slope (dv/dt) of the sinusoidal waveform cannot be precisely set since it varies during the sinusoid period. The sinusoidal waveform does not replicate the actual DUT operating conditions. This drawback renders the results helpful in investigating the phenomenon but useless for understanding the real impact in a given application. Therefore, if C_OSS obtained with PASTC is modeled with a SPICE netlist, simulating the converter would lead to misleading results at the design stage.

2.2.2. Half-Bridge Sawyer–Tower Circuit

The use of a half-bridge to supply the STB enables the emulation of the operating conditions of a DUT in an actual application because a trapezoidal voltage is generated across the STB (Figure 10).

The half-bridge Sawyer–Tower circuit (HBSTC) consists of a DC input connected to a half-bridge; in turn, the STB and an LC series branch are connected to the central node of the HB. Figure 11 reports the overall circuit, the decoupling capacitor, and the typical measurement scheme equivalent to the PASTC.

The series LC branch allows tuning the voltage slope of the trapezoidal voltage [11].

Concerning the component indicated in Figure 11, the following equation allows setting the voltage slope:

$${\displaystyle \frac{dv}{dt}}={\displaystyle \frac{V_{BUS}}{\sqrt{L_O{C}_{eq}}\left[\mathit{arcsin}\left(\frac{V_{BUS}}{2 \sqrt{\frac{L_O}{C_{eq}}{I}_O^2+\frac{V_{BUS}^2}{4}}}\right)-\alpha +\frac{\pi }{2} \right] }}$$

(11)

where:

$$\alpha =\mathit{arctan}\left({\displaystyle \frac{2 I_O\sqrt{\frac{L_O}{C_{eq}}}}{V_{BUS}}}\right)$$

(12)

$$I_O\approx {\displaystyle \frac{V_{BUS}}{8 L_{O }{f}_{SW}}}$$

(13)

$$C_{eq}=2 C_{OSS,HB}+C_{OSS}$$

(14)

where C_OSS,HB is the output capacitance of each HB switch, and f_SW is the switching frequency. The approximate Equation (13) is valid if the conduction time of the DUT is close to half of T_SW, where T_SW = 1/f_SW is the switching period of half-bridge MOSFETs.

The desired voltage slope is achieved by concurrently choosing the inductor, L_O, and the switching frequency, f_SW. The peak-to-peak current, I_O, of the current waveform, i_O, flowing in the LC branch also depends on them. The voltage slope and I_O decrease when the values of L_O or f_SW increase. Therefore, this topology allows us to analyze the dependence of the capacitive hysteresis on the voltage slope. Experimental results have achieved slopes equal to 30 V/ns [11] and up to 50 V/ns [24]. On the other hand, it is necessary to change the inductor to vary the voltage slope [13].

In summary, the HBSTC is the most effective approach for measuring hysteresis under actual operating conditions in resonant converters. Moreover, it enables achieving a high voltage slope (up to 50 V/ns). Finally, the ability to differentiate hysteresis losses from other loss mechanisms is an additional good feature of this approach [24].

2.2.3. Resonant Sawyer–Tower Circuit

Recently, a new topology has been proposed to measure the hysteresis curve. The STB is subjected to a voltage pulse generated by the joint action of an inductor, L, a DC voltage generator, and a switch, Q₁, as shown in Figure 12.

Figure 13 reports the resonant Sawyer–Tower circuit (RSTC) and its associated switching waveforms. As is apparent from the figure, the voltage across the STB is equal to V_DS1, the drain-source voltage of Q₁. At t0, Q1 is on, thus the inductor is charged. At t1, Q₁ is turned off, generating a half-sine pulse voltage due to the resonance between the inductor and the equivalent capacitance C_eq(V_DS1) at the STB connection:

$$C_{eq}\left(V_{DS1}\right)=C_{OSS1}\left(V_{DS1}\right)+{\displaystyle \frac{C_{OSS}\left(V_{DUT}\right)C_{REF}}{C_{OSS}\left(V_{DUT}\right)+C_{REF}}}\approx C_{OSS1}\left(V_{DS1}\right)+C_{OSS}\left(V_{DUT}\right)$$

(15)

where C_OSS1(V_DS1) is the output capacitance of Q1 that depends on V_DS1, and C_OSS(V_DUT) is the output capacitance of the DUT, which is much smaller than the reference capacitance C_REG.

In this way, a voltage pulse is obtained at the drain of the DUT, whose amplitude, Vm, and duration, Tr, depend on the value of the input DC source, Vin, the inductor, L, and the switch on-time, T_ON:

$$V_m\approx {\displaystyle \frac{V_{in}{T}_{ON}}{2\sqrt{L{C}_{eq}}}}$$

(16)

$$T_r\approx \pi \sqrt{L{C}_{eq}}$$

(17)

The main advantage of adopting the RSTC is the use of a single voltage pulse to extract the hysteresis curve, thus avoiding self-heating. However, this solution presents a more complex extraction of the curve since the calculation must account for the presence of the output capacitance of Q1.

An approach similar to the RSTC was proposed in [31]. The key difference between the RSTC and previous circuits is the lack of reference capacitance. This implies that C_OSS hysteresis evaluation related to the charging and discharging phases can be performed using only Equation (9).

Table 1. Comparison among different Sawyer–Tower circuits.

Circuit	Measurement Range Analyzed So Far	Reproducibility	Sensitivity	Feasibility in the Lab
PASTC	VDS amplitude and frequency upper limits determined by the power amplifier (until 800 V and 35 MHz)	High Controlled and stable signal ensures repeatable conditions	Medium to High Depending on the power amplifier bandwidth and the signal amplitude	Medium Moderate realization difficulty. Results are limited by power amplifier specifications Large size of power amplifier could be problematic
HBSTC	VDS until 600 V and frequency range between 100 kHz and 3.8 MHz	Low to Medium Parasitics and component tolerances affect repeatability Operating conditions reiteration is not easy	High Dynamic characterization under realistic high switching conditions	Low to Medium Necessary PCB, driver, and overall converter proper design
RSTC	VDS until 400 V and frequency until 10 MHz	Low to Medium Parasitics and component tolerances affect repeatability Control condition repeatability is not easy	High Good for fast voltage swings	Low to Medium Need proper design circuit and control implementation

reports the main features of the various Sawyer–Tower circuits described above. As mentioned before, an open problem is the definition of a standard. Moreover, the implementation of automated tools for extracting hysteresis parameters must be considered. A system integrating a hybrid class D converter, a control algorithm, and signal generation system, along with programmable test equipment, was proposed for automation purposes [32]. More specifically, in order to simulate the Sawyer–Tower system’s power amplifier, a hybrid class D converter was created, which is a less expensive solution. A wideband operational amplifier is used to amplify the low-amplitude sine wave produced by a direct digital synthesizer. A high-speed comparator is then used to compare the amplified sine wave to a DC reference signal from the microcontroller in order to produce a square wave output. Depending on the intended waveform to be applied across the DUT, the control algorithm determines the reference voltage. Two complementary gate drive signal pairs are produced using the comparator’s output square wave. A control algorithm integrates the previous two subsystems, and this system measures Coss losses based on user inputs to a Python script. Although it is a first step toward the large-scale characterization of Coss loss, further research effort is necessary.

3. Analysis of Coss Losses Under ZVS Operating Conditions

3.1. Coss Losses Evaluation

Using the STB to measure the Q_OSS–V_DS curve has the merit of enabling a direct evaluation of losses from the hysteresis curve itself. More specifically, the energy accumulated during the charging interval, E_OSS,CH, and released during the discharging interval, E_OSS,DI, can be determined by the Q_OSS–V_DS curve by calculating the areas under charging, V_DS,CH, and discharging, V_DS,DI, curves (Figure 9a), as follows:

$$E_{OSS,CH}={\int }_0^{Qmax}{V}_{DS,CH}\left(Q_{OSS}\right)d{Q}_{OSS}$$

(18)

$$E_{OSS,DI}={\int }_0^{Qmax}{V}_{DS,DI}\left(Q_{OSS}\right)d{Q}_{OSS}$$

(19)

The energy dissipated by the hysteresis, E_DISS, is the difference between them:

$$E_{DISS}=E_{OSS,CH}-E_{OSS,DI}$$

(20)

Power losses, P_DISS, due to hysteresis in resonant converters can be evaluated from the E_DISS estimation, as follows:

$$P_{DISS}=E_{DISS}{f}_{SW}$$

(21)

Other techniques have been proposed to evaluate hysteresis losses without considering Q_OSS–V_DS curve. These techniques employ unclamped inductive switching [33,34,35], combine half-bridges with on-state voltage measurement circuits (OVMCs) [12], or use thermal methods [10,24,28].

The unclamped inductive switching (UIS) method is based on the standard circuit of an inductor in series with the DUT, as illustrated in Figure 14.

The method exploits the resonance between C_OSS and the inductor. The main difference with circuits using the STB is the DUT state: it is not kept permanently off, but it starts from an initial on-state condition, and then the gate driver turns off the DUT after a given time interval, ∆T. In detail, considering Figure 15a, the DUT is initially on, thus charging the inductor until time t₀, when the DUT is turned off. Then, the inductor and C_OSS resonate, hence generating a voltage pulse across the DUT (red line in Figure 15a). This voltage pulse causes charging and subsequent discharging of C_OSS capacitance.

Different methods to calculate the energy dissipated by C_OSS using the UIS have been proposed. In [34], E_DISS is determined by measuring the inductor currents at the beginning and end of the pulse. The energy accumulated by the inductor is released to C_OSS in the interval [t₀; 0], as reported in Figure 15b. Subsequently, a portion of this energy returns to the inductor in the interval [0; t₁]. Therefore, E_DISS is assumed to be equal to the difference between the energy released by the inductor and that returned by C_OSS (Figure 15b). The inductor losses must be considered to evaluate the actual energy dissipated by C_OSS. These losses have been modeled with a series of parasitic resistances. According to this discussion and considering Figure 15, charging and discharging C_OSS energy can be computed as follows [34]:

$$E_{OSS,CH}=\left(1-{\displaystyle \frac{\pi }{Q}}\right)E_0$$

(22)

$$E_{OSS,DI}=E_1+{\displaystyle \frac{\mathsf{\pi }}{\mathrm{Q}}} E_0$$

(23)

where Q is the quality factor of the inductor, while E₀ and E₁ are the energies stored in the inductor at t₀ and t₁, respectively. Therefore, combining Equations (20), (22), and (23), it follows that [34]:

$$E_{DISS}=\left(1-{\displaystyle \frac{2\pi }{Q}}\right)E_0-E_1$$

(24)

If this process were loss-less, E_DISS would be zero since there would be an equal energy exchange between the two components.

A similar approach to calculating E_DISS using the UIS is proposed in [35]. This approach evaluates this energy from the waveforms, as depicted in Figure 16.

More specifically, the energy dissipated by C_OSS is determined by calculating the total energy dissipated by the overall system, E_TOT, which depends on the initial and final current through the inductor, indicated as, respectively, I_DS(max) and I_DS(min) in Figure 16:

$$E_{TOT}={\displaystyle \frac{1}{2}} L \left(I_{DS\left(max\right)}^2-I_{DS\left(min\right)}^2\right)$$

(25)

This energy includes C_OSS losses, inductor winding losses, E_IND, DUT switching losses, E_SW, and losses due to the PCB parasitic components, E_PCB:

$$E_{TOT}=E_{DISS}+E_{IND}+E_{SW}+E_{PCB}$$

(26)

The inductor winding losses are computed considering an equivalent series resistance, R_L, and the time of the half resonance cycle T:

$$E_{IND}={\displaystyle \frac{I_{DS\left(max\right)}^2}{4}} R_{L }T$$

(27)

The PCB losses are computed similarly by considering the PCB parasitic resistance. The DUT switching losses are calculated by integrating the I–V switching waveforms in Figure 16. However, it has been proven that at high voltage these contributions are negligible [35]. Therefore, considering Equations (25)–(27), E_DISS can be computed as follows:

$$E_{DISS}={\displaystyle \frac{1}{2}} L \left(I_{DS\left(max\right)}^2-I_{DS\left(min\right)}^2\right)-{\displaystyle \frac{I_{DS\left(max\right)}^2}{4}} R_{L }T$$

(28)

Finally, the work [33] proposes a different UIS approach for E_DISS evaluation that does not rely on any current measurement. The voltage across the DUT, V_DS, is integrated along the charging–discharging period, shown in Figure 17, to evaluate E_DISS:

$$E_{DISS}={\displaystyle \frac{1}{2L}} \left(S_1^2-S_2^2\right)={\displaystyle \frac{1}{2L}}\left({\left({\int }_{t_0}^0{V}_{DS}\left(t\right)dt \right)}^2-{\left({\int }_0^{t_1}{V}_{DS}\left(t\right)dt \right)}^2\right)$$

(29)

The UIS approach for E_DISS measurement enables the achievement of high voltage slopes (>120 V/ns), high resonance peak voltages (about 1 kV), and high frequencies (>40 MHz) [33]. The use of a single resonance pulse on the DUT to perform the measurement is another advantage because it avoids device overheating [33]. On the other hand, the DUT is initially on, and the measurement is performed as it is turned off, thus introducing hard switching losses that overlap with E_DISS, making the measurement inaccurate [28].

As mentioned, another approach utilizes a half-bridge that helps emulate the capacitive soft switching losses associated with C_OSS charging and discharging without tracing the hysteresis curve. To evaluate E_DISS, a topology (Figure 18) based on a half-bridge and on-state voltage measurement circuits (OVMCs) was proposed [12].

The circuit consists of an input DC voltage source; an input filter, whose components are (Figure 18) L_dc,h, L_dc,l, C_dc,h, C_dc,l, and C_dc,hf; two switches (T1 and T2) with two antiparallel diodes (D1 and D2); an inductor (load), L_LOAD; and two OVMCs. The inductors L_dc,h, and L_dc,l protect the DC source from high-frequency current harmonics. The capacitors C_dc,h and C_dc,l present an equal large capacitance to keep their central node voltage constant, which is half of the DC input voltage. Finally, C_dc,hf is introduced to prevent overvoltage and voltage oscillations. Diodes D1 and D2 enable the reduction of conduction losses during the half-bridge dead-times. The OVMC placed across devices T1 and T2 is used to measure the V_DS accurately.

It is necessary to simultaneously measure the I_D current and V_DS to calculate the power dissipated by the DUT. The V_DS varies from hundreds of Volt to mV during ZVS. Therefore, voltage measurement is difficult because a probe with a wide voltage range and resolution would be necessary. Consequently, the OVMC is used to measure the on-state V_DS with precision while limiting the maximum input voltage to the oscilloscope when the DUT is off [12]. Therefore, the OVMCs placed across the transistors in Figure 18 are necessary to accurately measure the dissipated power and evaluate C_OSS hysteresis losses. Figure 19 reports the key waveforms measured for this aim. Once the voltage and current are measured, the switching power losses are obtained, and then E_DISS is computed.

The thermal approach [10] is based on using temperature overheating to compute E_DISS. This common approach exploits the thermal resistance, Rth (Figure 20), of the device and its overheating to estimate the power losses, regardless of the specific power electronics application.

In Figure 20, Rth_(j-c), Rth_(c-h), and Rth_(h-a) represent the thermal resistance between the device’s die and the package, the package and the heatsink, and the heatsink and the ambient, respectively. The thermal resistance Rth_(c-a), between the package and ambient directly relates the device overheating to the power dissipated. It can be evaluated [9] by forcing a given current, I_F, and measuring V_DS and the steady-state case temperature, T_C, and the ambient temperature, T_A, as follows:

$$R_{th(c-a)}={\displaystyle \frac{T_C-T_A}{I_F{V}_{DS}}}$$

(30)

Once it is evaluated, it can be used to measure E_DISS by measuring the temperature under the device operating conditions, provided that there are no other losses into the device:

$$E_{DISS}={\displaystyle \frac{T_C-T_A}{R_{th(c-a)}{f}_{SW}}}$$

(31)

This approach has been frequently used to validate the other techniques.

3.2. Analysis of Circuit Quantities’ Impact on Coss Losses

Various experimental studies have revealed that the dissipated energy produced by the capacitive hysteresis of C_OSS depends on the slope and amplitude of the voltage waveform applied to the STB [10,11,13,24,26,27].

The PASTC does not allow for the distinction between the effect of the slope and amplitude of the applied voltage. More specifically, in the PASTC, the STB is subjected to a sinusoidal voltage, and a variation in its amplitude (while keeping the frequency constant) implies a concurrent change in both the amplitude and slope of the applied voltage. Vice versa, a modification in the waveform frequency (while keeping the amplitude constant), even if it affects the voltage slope only, does not allow a constant slope value since a sinusoidal waveform does not have a constant slope during a period.

The HBSTC is the best topology because it enables the desired amplitude and slope of the applied voltage to be set separately. Figure 21 shows the dependence of the dissipated energy vs. the supply voltage V_BUS of the half-bridge (Figure 21a) for a fixed peak current and vs. the STB peak current (Figure 21b) for a fixed supply voltage for three different devices [24]. It is worth noting that increasing the STB peak current is equivalent to raising the voltage slope (dv/dt). Therefore, Figure 21b reports the effect of the voltage slope on C_OSS losses. The blue, green, and red curves refer to the E_DISS of a Si-SJ MOSFET, a SiC MOSFET, and a GaN HEMT device, respectively. The solid lines represent the values achieved using the hysteresis trace, while the dashed ones indicate the dissipated energy estimated through the thermal method described before. The results of this study [24] highlight that the C_OSS hysteresis losses of all devices increase for both increasing voltage amplitude and slope. Moreover, the Si-SJ MOSFET device suffers from greater hysteresis losses than wide-bandgap devices. Finally, it is noteworthy that the two approaches for loss evaluation yield similar results.

These results were confirmed in another study [11] where a SiC MOSFET device was tested in the HBSTC by varying the voltage amplitude and slope of the trapezoidal waveform up to 30 V/ns. Figure 22a reports the increment of C_OSS losses with increasing voltage amplitude. Moreover, the tests were performed at different frequencies (400 kHz represented by circles and 10 MHz represented by triangles) and at different temperatures (on the right of Figure 22a is reported the temperature color map). The results showed that energy losses increase with frequency and, consequently, considering Equation (21), power losses strongly increase with frequency. Moreover, energy losses increase as the temperature decreases. However, the temperature effect almost vanishes as the frequency increases, as apparent from the proximity of the two curves at 10 MHz in Figure 22a. Finally, the results in Figure 22b evaluate the impact of the voltage slope, confirming that its increment leads to a greater E_DISS [11].

The studies [13,26] used the PASTC to test a more significant number of Si-SJ and SiC MOSFETs and GaN HEMT devices, analyzing their dissipated energy as the amplitude of the sinusoidal input voltage varied. Figure 23 reports the results achieved in these studies. Figure 23a shows that whatever the Si-SJ MOSFET, the E_DISS increases as the amplitude of the sinusoidal input voltage increases. Moreover, an increase in frequency also leads to increased energy losses. These considerations are also applicable to GaN HEMTs, as shown in Figure 23b, and to SiC MOSFETs, as shown in Figure 23c, thereby confirming previous results. Similar results are also reported in [28] for GaN HEMTs, although adopting the resonant Sawyer–Tower circuit.

In conclusion, various power loss mechanisms affect semiconductor devices in resonant converters, such as conduction losses due to the drain-source on-resistance and the intrinsic body diode, gate driving losses, and switching losses mainly due to C_OSS hysteresis. In particular, switching losses are ideally null. However, the presence of C_OSS hysteresis in real applications can lead to excessive switching losses, potentially impairing the efficiency of the converter. As reported in [24], measurements on a Si-SJ MOSFET operating at 400 V indicated hysteresis energy losses in the range of 2 to 4 µJ per switching cycle (see Figure 21b). When such a device was employed in a ZVS converter operating at a switching frequency between 100 and 200 kHz, along with a switching current of 4 to 8 A, the power dissipation due to C_OSS hysteresis could reach 0.5 W. This estimation was corroborated by the findings in [37], which analyzed switching losses in resonant LLC converters. The study emphasizes that hysteresis losses scale with the silicon die area, implying that suboptimal device selection, particularly in terms of die size and capacitance characteristics, can substantially impair system efficiency. Moreover, as switching power losses scale linearly with switching frequency, these losses can become dominant in high-frequency designs, potentially exceeding 1 W. This value is particularly critical under light load conditions, where conduction losses are relatively low. Under such scenarios, excessive switching losses may prevent the converter from meeting high-efficiency performance standards, such as the 80 Plus Titanium specification, especially at 20% load levels. Therefore, C_OSS hysteresis losses must be considered in high-frequency ZVS converters that persistently operate at low-level conditions. With this in mind, analyzing the influence of circuit quantities on Coss losses can be helpful for research studies aimed to devise countermeasures that mitigate their impact.

4. Physical Reasons for Coss Hysteresis Losses

The works analyzed in the previous sections have the merit of providing solutions for measuring C_OSS hysteresis and highlighting how circuit quantities affect the related energy losses in resonant applications. Although accurate circuit models do not currently exist, the previous information provides valuable guidelines for power converter designers. However, to fully exploit the advantages of resonant converters, it would be beneficial to develop devices without (or with minimal) Coss hysteresis losses. To this aim, the device designers must be aware of the origins of the phenomenon to devise new solutions that would mitigate or, in the best case, eliminate Coss hysteresis losses in ZVS applications. Keeping this in mind, this section analyzes studies on the physical reasons behind the phenomena and the solutions proposed in the literature.

The studies use mixed-mode simulations where the physical models of the power devices are combined with circuit models of the overall power converter to understand the physical origin of hysteresis. These simulations require simulators based on the technology computer-aided design (TCAD) paradigm. These tools enable the simulation of what happens inside the device while it operates in one of the test topologies, such as HBSTC, for measuring hysteresis.

4.1. SuperJunction MOSFETs

Coss hysteresis in power Si-SJ MOSFETs is mainly due to the asymmetric behavior of the depletion region in the n- and p-type regions during the charging and discharging processes. The difference primarily depends on the technological and geometric parameters of the cell, which involve a different evolution of the depletion region during the two phases.

Observing the path of the electron and hole flows during the charging and discharging phases is useful in understanding the reasons behind the asymmetric behavior. During Coss charging (Figure 24a), V_DS increases, and the electrons of the n-region (in green in Figure 24a) flow toward the drain, while the holes of the p-region (in yellow in Figure 24a) flow toward the source. During this phase, the boundaries of the depletion region (red dashed lines in Figure 24) expand, depleting the n- and p-regions of their majority of carriers. During the discharging phase, as the V_DS decreases, the electrons and holes follow along opposite paths while the depletion region shrinks (Figure 24b). The key quantities related to the cell are reported in Figure 25a.

The technology usually adopted for manufacturing Si-SJ power MOSFETs is multi-implant multi-epitaxy (MEMI, Figure 25b) and trench-filling epitaxial growth (TFEG, Figure 25c). The different behaviors, in terms of the evolution of the depletion region and potential lines, is shown in Figure 26. The figure illustrates TCAD simulations of the time evolution of the electric potential distribution (black lines) during the discharging phase of MEMI and TFEG cells [39]. The white lines represent the boundaries of the depletion region, which reduces as the device discharges over time. The key quantities related to the cell are reported in Figure 25a.

Looking at the MEMI cell (Figure 26a), it is evident that the potential distribution is irregular over time. Moreover, an atypical phenomenon emerges: the confinement of electron and hole charges.

In detail, the depletion region is not continuous, thus provoking stranded charges, Q_STR, which are represented by charge islands delimited by the white lines [39].

These charges are stored in undepleted regions located along the central axes of both the n- and p-pillars. As mentioned earlier, during discharge, the electrons in the n-region flow toward the source while the holes flow toward the drain in the p-pillar. However, the lack of continuity has for these stranded charges the same effect as the shrinking that can be observed in SJ field-effect transistors during quasi-saturation conduction. In this case, the pinched-off current is the C_OSS discharge current rather than the channel current. Thus, the highly resistive path created by the lack of continuity leads to losses, which are, consequently, hysteresis losses [39].

Differently, in the TFEG cell (Figure 26b), the distribution of potential lines is almost regular, and the evolution of the depletion region does not show stranded charges because the limits are continuous (white lines). TCAD simulations have been experimentally confirmed [39], proving that MOSFETs adopting MEMI cells exhibit significantly greater losses than their TFEG counterparts.

Electrothermal analyses have been performed to gain a better understanding of the physical mechanism of capacitive hysteresis, identifying a contribution of lost energy not only during the discharging phase but also during the charging phase [40]. Figure 27 shows the density current in a MEMI (a and b) and a TFEG (c and d) cell during the charging (a and c) and discharging (b and d) phases. The key quantities related to the cell are reported in Figure 25a. In Figure 27, the depletion region boundaries are drawn in white. The presence of the stranded charge in the MEMI cell is apparent when comparing the conditions of MEMI and TFEG at time t₄. However, these stranded charges are formed during the charging phase, thus provoking losses [40].

Mixed-mode simulations also confirmed that C_OSS hysteresis losses increase as the voltage slope rises [40]. Moreover, they confirmed that the MEMI cell exhibits more significant losses than the TFEG one. However, considering that TFEG is affected by this issue, some studies have analyzed different cell structures to find more insightful outcomes. In [39], the effect of the p-column inclination, β, was investigated. In the TFEG structures observed so far, the inclination is zero (β = 0). In structures with β > 0, the p-column width reduces as it moves away from the source terminal, while it increases if β < 0. The results, as shown by the solid blue line in Figure 28, indicate that losses decrease as β increases, while reducing β leads to performance worse than that of MEMI technology.

This study also analyzed the effect of increasing the cell pitch, and the results are shown by the dashed blue line in Figure 28. It emerged that a wider n-region, which maintains a constant number of electrons in the region (by doping reduction), enables loss reduction, especially when β > 0.

4.2. Wide-Bandgap Devices

In SiC MOSFETs, TCAD simulations have highlighted that the termination region is involved in C_OSS hysteresis losses [11]. The typical termination regions are reported in Figure 29. In vertical devices, the termination region surrounds the active cells to reduce the electric field thanks to this extension of the p–n junction at the edges of the cell.

To understand its impact, it is necessary to recall the following aspects. In Si material, at room temperature, considering a doping concentration equal to 10¹⁶ cm⁻³, almost all of the doping atoms are ionized. Thus, the numbers of free electrons and holes can be approximated by the concentrations of donor and acceptor atoms, respectively. On the other hand, under the same conditions, only 40% of the doping atoms in SiC material ionize. This phenomenon is defined as incomplete ionization. These considerations are valid under steady-state conditions only.

Instead, when fast excitations occur, a more accurate analysis must consider the ionization time, τ_p, which is the time an atom takes to release or capture a carrier:

$${\tau }_p={\displaystyle \frac{1}{e_p}} , e_p={\displaystyle \frac{{\sigma }_p{v}_{th}{N}_D}{g_A}}{e}^{-{\displaystyle \frac{E_A-E_V}{kT}}}$$

(32)

where σ_p is the acceptor cross-section, vth is the hole thermal velocity, N_D is the effective state density in the valence band with top edge energy E_v, g_A is the degeneracy factor, E_A is the acceptor energy level, k is the Boltzmann constant, and T is the temperature. The ionization time affects the extension of the depletion region during the voltage rise. When a reverse voltage is applied to the p–n junction, the depleted region has a larger width than that obtained after the ionization time (Figure 30, longest arrow) since the depletion region must be wide enough to support the external electric field before ionization occurs. Over time, it gradually reduces until it stabilizes at the width shown in steady-state conditions reached at time τ (shortest arrow in Figure 30). This phenomenon is responsible for switching losses and also occurs in the termination region. It has been proven that the termination contribution is about 50% [41]. TCAD simulations have highlighted that C_OSS losses in SiC MOSFETs are primarily due to the termination losses in soft switching applications up to 10 MHz. These results have also been confirmed by experimental measurements performed using the Sawyer–Tower circuit [11].

In the crystalline structure of GaN HEMT materials, the manufacturing process introduces imperfections that can interact with electrons and holes, capturing and emitting them. These imperfections are called traps, whose states can be shallow or deep, depending on the energy required to bring the electron back to the conduction band. The traps become negative ions when they capture free electrons, thereby reducing the electron density of the 2DEG layer, which, in turn, decreases its conductivity and negatively impacts the on-state resistance of the device. This effect is denoted as current collapse or dynamic on-state resistance [42]. A further consequence of these crystalline lattice imperfections would be the capacitive hysteresis of C_OSS in GaN HEMTs. When the device is turned on, the trapped charges might not have sufficient time to leave the traps, resulting in a different charging and discharging processes of C_OSS capacitance, which leads to losses [43]. However, although the trapping and de-trapping of electrons would seem to be the key element in the origin of the phenomenon, the actual reasons for Coss hysteresis in GaN HEMTs are not yet completely clear [28].

In the GaN HEMT device, C_OSS is the sum of C_DS, C_GD, and C_D,SUB (drain-substrate capacitance), as shown in Figure 31 [44]. C_OSS losses are almost entirely due to C_D,SUB. This capacitance depends on the characteristics of the buffer layer, which is involved in the trapping and de-trapping phenomenon. For these reasons, this phenomenon should cause the hysteresis losses [12]. Experimental results have also supported this thesis. The comparison of soft switching losses between two GaN HEMTs differing only in the buffer layer has shown that losses can be more than halved when the trapping and de-trapping phenomena are mitigated [12].

The central role of the buffer in C_OSS hysteresis losses was further confirmed in [44], where the effect of the substrate voltage, V_SUB, on these losses was analyzed. The PASTC was adopted for this aim, considering different amplitudes of the sinusoidal input of the STB and V_SUB. Figure 32 confirms that C_OSS hysteresis losses increase as the STB input voltage increases. Additionally, it shows that the losses can be mitigated by applying negative V_SUB with increasing amplitude.

The trapping–detrapping mechanism is significantly influenced by temperature. When the temperature increases, the carriers can be more easily de-trapped, thus mitigating C_OSS hysteresis losses in GaN HEMTs. With this in mind, the impact of temperature on losses has been investigated at different STB input voltages [45]. The results showed that losses reduce as the temperature increases, regardless of the input voltage value. Finally, it was reconfirmed that C_OSS hysteresis losses increase as the amplitude of the input voltage increases.

Table 2. Main features and key outcomes of the studies on COSS hysteresis.

Work	Device Technology	Analysis	Tool for Hysteresis Losses Estimation	Key Outcomes
[10,27]	Si-SJ	Experimental	PASTC	EDISS increases with VDS amplitude
[12]	GaN		VDS-ID waveforms
[13,45]	Si-SJ, SiC, GaN		PASTC
[22,25]	GaN		PASTC
[28]	GaN		RSTC
[31]	Si-SJ		VDS-ID waveforms
[33]	GaN		VDS waveform
[34]	Si-SJ, SiC, GaN		IL inductor current
[26]	GaN	Experimental	PASTC	EDISS increases with dv/dt EDISS increases with VDS amplitude
[11,41]	SiC	Experimental and TCAD simulation	PASTC/HBSTC	EDISS increases with dv/dt Losses occur in termination regions
[24]	Si-SJ, SiC, GaN	Experimental	HBSTC	EDISS increases with VDS amplitude and inductor peak current GaN HEMT devices present the smallest losses
[38,39,40]	Si-SJ	TCAD simulation	VDS-ID waveforms	TFEG mitigates EDISS EDISS increases with dv/dt
[44]	GaN	Experimental	PASTC	EDISS increases with VDS amplitude EDISS decreases for higher imposed temperatures

summarizes the main features and key outcomes of the studies on C_OSS hysteresis.

5. Conclusions and Future Trends

Soft switching techniques and high-efficiency power electronics switches are fundamental to achieving high efficiency and enabling high power density. In this framework, C_OSS hysteresis losses under the ZVS condition have emerged as a key hindering factor. The analysis of the phenomenon has highlighted that these losses increase when the input voltage amplitude and slope across C_OSS increase. In SJ MOSFETs, the MEMI structure presents more significant losses than the TFEG one due to the presence of stranded charges. The increment of the cell pitch and a p-column with a wide reduction from the source onward (see Figure 28) further mitigate the losses in TFEG structures. In SiC MOSFET, the termination region leads to losses due to the phenomenon of incomplete ionization. In GaN HEMTs, the losses are probably caused by the trapping–detrapping mechanism of the carriers, which is typically responsible for the increase in on-state losses (current collapse). The phenomenon is mitigated by improving the buffer layer and setting a negative voltage to the substrate. Finally, C_OSS hysteresis losses decrease with temperature increment in SiC MOSFETs and GaN HEMTs. However, no study analyzed the effect of the imposed temperature on hysteresis losses in Si-SJ MOSFETs. Thus, future research should investigate this aspect.

Comparing Si-SJ, SiC, and GaN devices, considering the results obtained from various papers that employ different device technologies, breakdown voltages, on-state resistances, and so on, is not straightforward. However, in a few cases, interesting information can be achieved. For example, Figure 21 shows that GaN HEMTs provide the lowest hysteresis losses, while Si-SJ MOSFETs present the highest losses. However, also considering the previous discussion about MEMI and TFEG structures, as well as the specificity of this comparison, these results cannot be generalized.

The analysis of research works on C_OSS hysteresis losses has highlighted the need for more in-depth studies in the field of wide-bandgap devices to better understand and evidence the origin of the losses, and especially to provide new designs and countermeasures. Different techniques and methods for measuring C_OSS hysteresis traces and losses have been presented in the literature; however, manufacturers do not provide this information in their datasheets. The problem is due to the lack of a standard and automated method for characterizing C_OSS hysteresis. Thus, further research efforts must be invested in addressing this challenge, as designers and developers require information on device suitability for soft switching applications. The literature analysis has pinpointed that the half-bridge Sawyer–Tower circuit could be the best solution. A related issue is the definition of a figure of merit that facilitates the classification of devices according to their soft switching losses. A figure of merit can also enable the identification of the most suitable device for a given ZVS application. Lastly, examining the possible effects of C_OSS hysteresis on power converter stability and the possibility of causing parasitic oscillations is a significant and unsolved task. Despite its practical relevance, especially in high-frequency or high-performance applications, this aspect remains largely unexplored in the existing literature. A deeper understanding of this phenomenon could have meaningful implications for converter design and control strategies, and thus represents a promising direction for future research.