Dual-Coupled-Inductor-Based High-Step-Up Boost Converter with Active-Clamping and Zero-Voltage Switching

Abstract

Many applications, such as photovoltaic systems, uninterruptible power supplies, and automobile headlamps, need a high step-up DC–DC converter without isolation. The conventional boost converter has the advantages of simple topology and easy control. However, it has some shortcomings, such as insufficient step-up voltage ratio and poor efficiency when operating at large duty-cycle conditions. One of the popular topologies used to overcome these problems is the coupled-inductor boost converter. It utilizes the turn ratio of the coupled inductor to realize a higher step-up voltage ratio. The drawback is that the leakage inductance of the coupled inductor causes a huge voltage spike when the power switches are turned off. Moreover, because coupled inductors are characterized by their large volume and high profile, a conventional coupled-inductor boost converter is unsuited for photovoltaic systems, such as the solar microinverter. This study proposes a novel high-step-up boost converter to solve these problems. This proposed converter uses dual coupled inductors instead of the conventional coupled-inductor boost converter. The secondary side of the coupled inductor is connected in series to increase the step-up voltage ratio. The proposed converter utilizes active clamping to achieve zero-voltage switching (ZVS) for suppressing voltage spike and improving conversion efficiency. In addition, low-profile designs can be fulfilled easily for solar microinverters. The proposed converter and its control method are introduced. The operation principle, circuit characteristics, and circuit analysis are presented. A prototype converter with 300 W output power 25–40 VDC input voltage and 200 VDC output voltage was tested. All functions, including high step-up voltage ratio, ZVS, and active clamping, were achieved, and the highest efficiency was around at 94.7%.

1. Introduction

At present, many applications, such as photovoltaic systems [1,2,3], uninterruptible power supplies [4,5], automobile headlamps [6,7,8], and other telecommunication systems [9,10,11], still require a high-step-up DC–DC converter as the power supply. Moreover, most solar microinverters require cooling through free air convection and a lower profile, which translates to the need for high conversion efficiency and lower-profile magnetic components. The conventional boost converter is widely used in voltage step-up applications [12]. However, it has some shortcomings that cause difficulties in practical applications. The voltage gain ratio is limited to about five times because the non-ideal resistance of the line, inductor, and diode limit the maximum practical output voltage [12]. The method of integrated magnetic boost converter (IMBC) with both input/output current ripple cancellation and right-half-plane (RHP) zero elimination has been proposed [13]. IMBC has many advantages, such as small ripple, increased bandwidth, and reduced weight. Nevertheless, IMBC has a wide-duty-cycle problem when it is applied to high step-up conversion conditions. The high step-up voltage gain requires a wide duty cycle, but the duty cycle causes poor control and instability when it is close to one. The voltage and current stress of the main power components (switches and diodes) are determined by output voltage and input current. When the duty cycle is operating at large conditions, a larger root-mean-square (RMS) current flows through the power switch, thereby causing great conduction losses. The selection of a power switch becomes more difficult, and the conversion efficiency is remarkably decreased. The development of high-step-up voltage-gain-ratio converters is important to solve these problems.

Figure 1 shows the basic coupled-inductor boost converter [14]. This boost converter uses the coupled inductor to replace the conventional inductor and utilizes the turn ratio to greatly increase the output voltage [15,16,17,18,19]. The basic coupled-inductor boost converter still has a critical disadvantage, where the leakage inductance of coupled inductor causes a high voltage spike when the power switch is turned off. Although increasing the turn ratio can increase the voltage gain, the leakage inductance is also increased. A lossless clamped circuit can reduce the voltage stress on the main switch as the circuit cannot realize ZVS of the main switch. The active clamp method utilizes resonance of the clamp capacitor and resonant inductor to recover energy. This method not only absorbs voltage spikes on power switches but also enables power switches to achieve ZVS [20,21,22]. Although increasing the duty cycle of power switch in the conventional coupled-inductor boost converter can achieve a higher voltage gain ratio, the power switch experiences a larger conduction loss due to the increase in turned-on time. Furthermore, the coupled inductor volume is larger than the inductor of the conventional boost converter because the coupled inductor has extra added due to the winding of the secondary side. Therefore, it is unsuitable for application in the solar microinverter. This method has a large DC current flows through the primary side of the coupled inductor. Finally, the passive components are increased, and the topology composition becomes more complex.

The cascaded coupled-inductor method is presented; this is different to the conventional boost converter [23,24]. This method can alleviate the voltage spike problem and recycle the leakage energy, but the clamping circuit causes extra losses. The stacked coupled inductor utilizes the flyback output directly to augment the boost output [25,26]. However an extra voltage balance control is required because the output terminal is divided into two capacitors. Similar to the stacked coupled inductor, a synchronous rectifier switch replaces the power diode in [27], allowing the main power switch to achieve ZVS, thereby improving conversion efficiency. Similar to the cascaded coupled-inductor method, the multi-winding coupled-inductor method uses additional windings to improve voltage gain and reduce power-diode voltage stress [28,29]. However, this approach increases passive component count and complicates the topology. The integrated coupled-inductor method [30,31,32] utilizes the characteristics of a boost or SEPIC converter to minimize input current ripple and reduce winding inductor core losses. This method exhibits higher topology complexity than the multi-winding coupled-inductor method and fails to achieve ZVS in the power switch. The above method has the problem of a large DC current flowing through the input inductor, and this problem remains unaddressed. The interleaved coupled-inductor method uses multiple converters operating in tandem to alleviate the current stress at the primary side of coupled inductors, but it does not increase the voltage gain [33,34]. Unfortunately, using multiple converter sets causes the circuit volume to increase and poses challenges in switch control for the interleaved method.

A dual-coupled-inductor-based high-step-up boost converter with active-clamping and zero-voltage switching is proposed. This method uses a stabilizing capacitor loop and dual coupled inductor, which is an innovative coupled-inductor converter and is different from existing inductor converter topology. The stabilizing capacitor voltage at stable conditions is equivalent to the input voltage; the energy of the dual coupled inductors is provided by the input voltage and stabilizing capacitor. The dual coupled inductors share the large input current at the primary side of coupled inductors and the secondary side of coupled inductors is connected in series to achieve high step-up voltage ratio. It extends the voltage gain dramatically and decreases the switch voltage stress. In addition, the active clamp method can transfer the energy released by the leakage inductance to the output load. Thus, the proposed topology can have more efficient performance.

Figure 2 shows that the primary side of the present topology is different from the basic coupled-inductor boost converter and interleaved method. Compared with basic coupled-inductor boost converters, the use of dual coupled inductors enables shared energy storage, allowing for the use of smaller magnetic components. Additionally, connecting the secondary sides of coupled inductors in series achieves a high step-up voltage ratio and the presented converter effectively reduces the duty cycle, thereby decreasing conduction losses in the main power switch because of reduced turn-on time. The proposed converter uses active clamping to suppress the voltage spikes and utilizes the leakage inductance of coupled inductors for ZVS operation in the power switches. Compared with the interleaved coupled-inductor converters and multiple coupled-inductor converters, it not only requires fewer circuit components but also features simpler switch control.

In Section 2, analyses of the circuit operations, operation waveform, and time domain are provided. In Section 3, analysis of circuit characteristics, component stress, and DC gain is outlined. This includes circuit design, which is discussed and calculated. In Section 4, testing of a prototype converter with 300 W output power, 25–40 V_DC input voltage, and 200 V_DC output voltage is described; the highest efficiency was around 94.7%.

2. Operation of the Proposed Converter

Figure 3 shows the schematic of the proposed boost converter using dual coupled inductors to achieve a high step-up ratio while implementing active clamping for ZVS. This topology comprises two identical coupled inductors CI₁ and CI₂, the main switch S₁, the auxiliary switch S₂, a resonant inductor L_r, a clamp capacitor C_a, a stabilizing capacitor C_b, and the output diode D_o. Both coupled inductors share identical characteristics, and the ideal coupling coefficient is one. A transformer T model is used to describe the coupled inductors. The resonant inductor L_r was designed to enable ZVS for the S₁ and S₂ operations. The control method is pulse-width modulation (PWM). In this study, the v_s signal is obtained by dividing the output voltage. The v_s signal is compared with V_ref, and the digital value is converted by the analog-to-digital converter (ADC) of the DSP. The CMPx value is derived after executing the proportional integral differential (PID) in the z-domain. Finally, intelligent EPWM generates the gate signal. PWM control maintains a fixed frequency while adjusting the pulse width to ensure a stable output voltage, as illustrated in Figure 4.

To analyze the proposed boost converter with dual coupled inductors and a high step-up ratio, the following assumptions are made:

• The turn ratio of the two coupled inductors is the same, which is 1:n.
• The magnetizing inductance of both coupled inductors is the same, which is L_m (L_m1 = L_m2 = L_m).
• The clamping capacitors C_a and C_b and the output capacitor C_o are much larger than the output capacitance of power switches C_r1 and C_r2. Their steady-state voltages can be viewed as constant voltage sources, dependent on the input voltage and duty cycle.
• The on times of S₁ and S₂ are DT_s and (1 − D)T_s, respectively, where D is the duty cycle of main switch S₁, T_s is the switching period, and the dead time is assumed to be smaller than other conduction times.
• All components are considered ideal such that the conduction losses of all switches and diodes are ignored.

From the above assumptions, C_a and C_b in the steady state can be calculated. When the main switch S₁ is turned on, the voltage across the primary side of CI₁ approximates the input voltage V_in. On the contrary, when the main switch S₁ is turned off, the voltage across the primary side of CI₁ is approximately −v_Ca. From the flux balance of magnetizing inductance L_m under the steady state, v_Ca can be expressed as

$$v_{Ca}=\frac{D}{\left(1-D\right)}{V}_{in}$$

(1)

The voltage across the primary side of CI₂ approximates −v_Cb when S₁ is turned on, and the voltage across the primary side of CI₂ is V_in + v_Ca − v_Cb when main switch S₁ is turned off. In accordance with Equation (1) and to maintain flux balance, the steady-state value of v_Cb can be determined as

$$v_{Cb}=V_{in}$$

(2)

The definitions of the direction of voltage and current are shown in Figure 3. i_DS1 and i_DS2 are the currents of switches, i_Lr is the resonant inductor current, i_Lm1 and i_Lm2 are the magnetizing inductor currents, i_Lp1 and i_Lp2 are the currents of coupled inductors at the primary side, and i_Do is the output diode current. Figure 5 shows the operation waveform of the proposed topology. The waveform can be divided into six parts in one cycle. The descriptions of each state are given below. Figure 6 provides a visual representation of these six operation states.

-

State 1 (t₀–t₁)

In this state, auxiliary switch S₂ is turned off at t₀, whereas the main switch S₁ remains off. The resonant inductor L_r has two parasitic capacitors C_r1 and C_r2, and the direction of resonant inductor current i_Lr is negative. This state ends when capacitor C_r1 is discharged to zero and capacitor C_r2 is charged to V_in + v_Ca. The values of C_r1 and C_r2 are extremely small, so this state is extremely short. The resonant inductor L_r must meet the following conditions to achieve ZVS:

$$L_r\ge \frac{\left(C_{r1}+C_{r2}\right){\left[v_{DS1}\left(t_0\right)\right]}^2}{{\left[i_{Lr}\left(t_0\right)\right]}^2}$$

(3)

-

State 2 (t₁–t₂)

At t₁, C_r1 is discharged to zero, the body diode operates across S₁, and S₁ is turned on to achieve ZVS. At the same time, both coupled inductors still provide energy to the output side, and the output diode current i_Do continually decreases linearly until it reaches zero. i_Lr changes from negative to positive until it is equal to the sum of absolute value of magnetizing inductor currents i_Lm1 and i_Lm2, and this stage ends. The node voltage v_x and the magnetizing inductor voltages v_Lm1 and v_Lm2 can be expressed as

$$v_x=\frac{2n{V}_{in}+V_o}{2n+1}$$

(4)

$$v_{Lm1}=\frac{V_{in}-V_o}{2n+1}$$

(5)

$$v_{Lm2}=\frac{-(V_{in}-V_o)}{2n+1}$$

(6)

The magnetizing inductor currents i_Lm1(t) and i_Lm2(t), resonant inductor current i_Lr(t), and diode current i_Do(t) can be expressed as

$$i_{Lm1}\left(t\right)=\frac{V_{in}-V_o}{\left(2n+1\right)L_m}\left(t\right)+i_{Lm1}\left(t_1\right)$$

(7)

$$i_{Lm2}(t)=\frac{-(V_{in}-V_o)}{\left(2n+1\right)L_m}\left(t\right)+i_{Lm2}\left(t_1\right)$$

(8)

$$i_{Lr}(t)=\frac{2n{V}_{in}+v_o}{(2n+1)L_r}\left(t\right)+i_{Lr}\left(t_1\right)$$

(9)

$$i_{Do}(t)=\frac{i_{Lm1}\left(t\right)-i_{Lm2}\left(t\right)-i_{Lr}\left(t\right)}{2n+1}$$

(10)

-

State 3 (t₂–t₃)

In state 3, S₁ remains on and carries the resonant inductor current i_Lr, and i_Lr is equal to the sum of the absolute value of magnetizing inductor currents i_Lm1 and i_Lm2. S₂ is remains off, v_Lm1 is approximately equal to the input voltage V_in, and v_Lm2 is approximately equal to the negative input voltage −V_in, so the input energy is shared between the two primary magnetizing inductances of coupled inductor. This interval ends when S₁ is turned off. The output diode is reverse biased, and the output current is supplied only by the output capacitor C_o. The node voltage v_x and the magnetizing inductor voltages v_Lm1 and v_Lm2 can be expressed as

$$v_x=V_{in}\frac{2L_r}{L_m+2L_r}$$

(11)

$$v_{Lm1}=V_{in}\frac{L_m}{L_m+2L_r}$$

(12)

$$v_{Lm2}=-V_{in}\frac{L_m}{L_m+2L_r}$$

(13)

The magnetizing inductor currents i_Lm1(t) and i_Lm2(t) and resonant inductor current i_Lr(t) can be expressed as

$$i_{Lm1}\left(t\right)=\frac{V_{in}}{L_m}\frac{L_m}{L_m+2L_r}t+i_{Lm1}\left(t_2\right)$$

(14)

$$i_{Lm2}\left(t\right)=\frac{V_{in}}{L_m}\frac{-L_m}{L_m+2L_r}t+i_{Lm2}\left(t_2\right)$$

(15)

$$i_{Lr}\left(t\right)=V_{in}\frac{2L_r}{L_m+2L_r}t+i_{Lr}\left(t_2\right)$$

(16)

-

State 4 (t₃–t₄)

At t₃, S₁ and S₂ are turned off. The resonant inductor L_r is resonant with parasitic capacitors C_r1 and C_r2. This stage ends when capacitor C_r1 is charged to V_in + v_Ca and capacitor C_r2 is discharged to zero. This stage is extremely short because the values of capacitances C_r1 and C_r2 are extremely small. The ZVS condition is expressed as

$$L_r\ge \frac{\left(C_{r1}+C_{r2}\right){\left[v_{DS2}\left(t_3\right)\right]}^2}{{\left[i_{Lr}\left(t_3\right)\right]}^2}$$

(17)

-

State 5 (t₄–t₅)

Figure 6e shows the operation station at this state, where the voltage v_DS1 is to be charged to V_in + v_Ca. The resonant inductor current i_Lr flows through the body diode of S₂, and S₂ is turned on to achieve ZVS. Given that v_Lm1 is approximately equal to the negative v_Ca and v_Lm2 is approximately equal to v_Ca, the output diode D_o is forward biased and starts to operate. The energies stored in the magnetizing inductors L_m1 and L_m2 are transferred to the output load. The diode current i_Do starts to increase linearly, and clamp capacitor voltage v_Ca begins to rise. This stage ends when the resonant inductor current i_Lr decreases to zero. The node voltage v_x and the magnetizing inductor voltages v_Lm1 and v_Lm2 can be expressed as

$$v_x=\frac{2n{V}_{in}+V_o}{2n+1}$$

(18)

$$v_{Lm1}=\frac{V_{in}-V_o}{2n+1}$$

(19)

$$v_{Lm2}=\frac{-(V_{in}-V_o)}{2n+1}$$

(20)

The currents i_Lm1, i_Lm2, i_Lr, and i_Do are given as

$$i_{Lm1}\left(t\right)=\frac{V_{in}-V_o}{\left(2n+1\right)L_m}\left(t\right)+i_{Lm1}\left(t_4\right)$$

(21)

$$i_{Lm2}(t)=\frac{-(V_{in}-V_o)}{\left(2n+1\right)L_m}\left(t\right)+i_{Lm2}\left(t_4\right)$$

(22)

$$i_{Lr}(t)=\frac{2n{V}_{in}+v_o}{(2n+1)L_r}\left(t\right)+i_{Lr}\left(t_4\right)$$

(23)

$$i_{Do}(t)=\frac{i_{Lm1}\left(t\right)-i_{Lm2}\left(t\right)-i_{Lr}\left(t\right)}{2n+1}$$

(24)

-

State 6 (t₅–t₆)

The circuit operations in this interval are the same as those in State 5, except for the directions of i_Lr. The capacitor voltage v_Ca starts to decrease, and the ampere-second balance is completed in States 5 and 6.

3. Analysis of the Proposed Converter

Figure 7 ignores the intervals t₀–t₁ and t₃–t₄ of Figure 3. The intervals t₀–t₁ and t₃–t₄ can be ignored because the time is extremely short. Simplifications are needed to derive the ideal transfer function of the proposed topology. Figure 5 shows the simplified waveform, where D is the duty cycle of metal–oxide–semiconductor field-effect transistor (MOSFET) S₁, and D_er is the duty loss. The resonant inductor current i_Lr can be divided into stages A, B, and C, in accordance with its shape.

3.1. Clamped Voltage v_Ca

As shown in Equation (1), v_Ca is determined by D and V_in. As depicted in Figure 8, the clamp capacitor voltage v_Ca will be higher than the input voltage V_in if duty cycle D is higher than 0.5. If duty cycle D is close to 1, then the clamp capacitor voltage v_Ca will be extremely high. Therefore, in applications, the duty cycle should be designed around 0.5.

3.2. Voltage Transfer Ratio

In accordance with the simplified waveform at Figure 6, the volt-second balance equation of magnetizing inductor L_m1 is

$$\frac{V_{in}-V_o}{2n+1}{D}_{er}+V_{in}\frac{\frac{1}{2}{L}_{m1}}{\frac{1}{2}{L}_{m1}+L_r}\left(D-D_{er}\right)+\frac{V_{in}-V_o}{2n+1}(1-D)=0$$

(25)

In general, resonant inductor L_r is smaller than magnetizing inductors L_m1 and L_m2. If the effects of duty loss D_er and resonant inductor L_r are ignored, then Equation (25) can be simplified as Equation (26), and ideal transfer function M_ideal is derived as Equation (27).

$$V_{in}D+\frac{V_{in}-V_o}{2n+1}(1-D)=0$$

(26)

$$M_{ideal}=\frac{2nD+1}{1-D}$$

(27)

Figure 9 shows the comparison of ideal transfer ratio M_ideal and conventional boost converter transfer ratio M = 1/(1 − D). The proposed topology has a relatively higher transfer ratio. The transfer gain increases relatively because the transformer turn ratio is higher. In accordance with Equation (27), if the transfer ratio is around 10 times, then the turn ratio n = 1 is unsuitable.

Figure 10 shows the transfer ratio comparison of the proposed topology and coupled-inductor boost converter, where the transfer ratio of the proposed topology is (nD + 1)/(1 − D). From Figure 10, the transfer ratio of the proposed topology is higher than coupled-inductor boost converter when the turn ratio is the same.

The voltage of the magnetizing inductor L_m1 is inconsistent in duty cycle D due to the influence of duty loss D_er. The effect of the inductor is also reconsidered, so Equation (28) is rederived, and the transfer ratio M = V_o/V_in can be expressed as

$$\frac{V_o}{V_{in}}=\frac{\frac{L_m}{L_m+2L_r}(D-D_{er})(2n+1)}{1-(D-D_{er})}$$

(28)

Equation (25) is used to derive duty loss D_er as follows:

$$D_{er}=\frac{-i_{D{o}_{Max}}(2n+1)}{T_s}\frac{1}{(\frac{v_{Lm1}\left(A\right)}{L_{m1}}-\frac{v_{Lm2}\left(A\right)}{L_{m2}}-\frac{v_{Lr}\left(A\right)}{L_r})}$$

(29)

where i_{Do_Max} is the peak current of diode, and the value can be derived as

$$i_{Do\_Max}=\frac{\left(1-D\right)T_s}{2n+1}(\frac{v_{Lm1}\left(C\right)}{L_{m1}}-\frac{v_{Lm2}\left(C\right)}{L_{m2}}-\frac{v_{Lr}\left(C\right)}{L_r})$$

(30)

In accordance with the current waveform in Figure 5, the output current I_o can be expressed as

$$I_o=\frac{i_{Do\_Max}}{2}[1-\left(D-D_{er}\right)]$$

(31)

Figure 11 shows the relationship between transfer ratio M, output current I_o, and duty cycle D, plotted using Equations (28)–(31). The transfer ratio M is affected by output current I_o and duty cycle D. Duty loss D_er increases with the increase in load current, which indicates that more duty cycle D is required to reach the required voltage. Assuming that the transfer ratio M is 8, duty cycle D changes from 0.52 to 0.69 if the output current I_o changes from 0 to 3.

3.3. Voltage and Current Stress

In accordance with Section 2, the voltage stresses of switches S₁ and S₂, and diode D_o can be derived as Equations (32) and (33). Resonant inductor L_r is smaller than magnetizing inductors L_m1 and L_m2, so voltage stress v_Do can be simplified to facilitate subsequent comparison.

$$v_{DS1}=v_{DS2}=V_{in}+v_{Ca}=\frac{1}{\left(1-D\right)}{V}_{in}$$

(32)

$$V_{Do}=V_{in}\frac{2n{L}_m}{L_m+2L_r}-V_{in}\frac{2L_r}{L_m+2L_r}+V_o$$

(33)

Figure 12 shows the relationship of magnetizing inductor currents i_Lm1 and i_Lm2, diode current i_Do, and output current I_o. From Equation (30), the value of output current I_o is the average of diode current i_Do. From Section 2, the diode current i_Do is composed of magnetizing inductor currents i_Lm1 and i_Lm2 and resonant inductor current i_Lr. Two transformers provide current to the output, so the current stress of the transformer is lower.

Table 1. Comparison of the conventional boost converter and the proposed topology.

Topologies	Propose Converter	[21]	[26]	[29]	[34]
Number of coupled inductors	2	1	1	1	2
Number of switches	2	2	2	1	2
Number of diodes	1	2	4	4	4
Voltage gain	$\frac{2nD+1}{1-D}$	$\frac{1+n}{1-D}$	$\frac{1+\left(1+D\right)n}{1-D}$	$\frac{2-D+n}{1-D}+n$	$\frac{2n+1}{1-D}$
Control method	PWM	PWM	PWM	PWM	Interleave
Soft-switching performance	ZVS	ZVS	Hard switching	Hard switching	Hard switching
Input-current stress	Medium	High	High	High	Medium
Diode-voltage stress	High	High	Low	Low	Medium
Conduction losses	Low	High	High	High	High

compares the modern topology and the proposed topology, which includes the number of components, voltage gain, control method, input current stress, diode voltage stress, and efficiency. Comparison is made under the same output load and current ripple conditions and the same output load conditions. The cascade coupled-inductor method increases the number of turns. As a result, the winding area of the magnetic components is increased, requiring the use of larger iron cores. Therefore, the voltage stress on the output diode also increases [21]. The stacked coupled inductor approach requires redundant rectifier diodes to control the output capacitor voltage [26]. Similar to stacked coupled inductors, the multi-winding coupled inductor approach uses additional windings to increase the voltage gain. The additional windings require magnetic components to be designed using larger cores [29]. However, the approach of stacked and multi-winding increases passive component count and complicates the topology. In the above method, the problem of a large DC current flowing through the input inductor remains unaddressed. The interleaved coupled-inductor method uses multiple converters operating in tandem to alleviate the current stress at the primary side of the coupled inductors [34]. Unfortunately, using multiple converter sets causes the circuit volume to increase and poses challenges in switch control for the interleaved method. Compared with previous studies, the primary side of the coupled inductor has a lower current stress under the same output load conditions. Considering the high output transfer ratio condition, the voltage stress of the proposed topology is around V_in, and the voltage stress of the conventional boost converter is higher than V_in.

4. Experimental Results

A 300 W prototype was designed and built to verify the feasibility of the proposed topology, as shown in Figure 13. The dimensions were approximately $120\times 100\times c {\mathrm{m}\mathrm{m}}^3$. The specifications of the prototype are shown in

Table 2. Specification of Prototype.

Item	Value
$V_{in}$	25–40 V
$V_o$	200 V
$I_{o\_MAX}$	1.5 A
$P_{o\_MAX}$	300 W
$\mathrm{Switching}\mathrm{frequency}{f}_s$	100 kHz

, and the selection of components is shown in

Table 3. Component Selection.

Item	Value
$\mathrm{MOSFET}{S}_1$$/S_2$	FDP2614
$\mathrm{Diode}{D}_o$	BYC200-600P
Transformer turn ratio	1:3
Core material/type	PC 40/PQ35-35

. In addition, to verify the assumptions in Section 2, the parameters are listed in

Table 4. Parameters of Components.

Item	Value
Resonant inductor Lr	1 μH
Magnetizing inductance Lm	15 μH
Parasitic capacitor Cr	500 pF
Voltage-stable capacitor Ca	66 μF
Clamping capacitor Cb	8 μF

.

The inductance of resonant inductor was designed in accordance with Equations (3) and (29). The magnetizing inductance was based on Equations (12), (19) and (29). The parasitic capacitor was the output capacitance of MOSFET. Efficiency data were obtained from the experimental results. The DC power source utilized was the Keysight E35234A, the DC load was the Chroma 63108A, and the power meter was the HIOKI PW3337.

Figure 14, Figure 15 and Figure 16 show the operation waveforms at 25 V V_in and full load condition. The voltage stress of v_DS2 mostly conformed to Equation (31). The voltage stress of v_DS1 was slightly higher than the calculation because the capacitance v_Ca was small (this phenomenon can be referred to as State C in Figure 5). Figure 14 illustrates the ZVS waveforms. Before v_gs1 and v_gs2 were turned on, the drain-to-source voltages v_DS1 and v_DS2 were clamped at zero. Therefore, ZVS operations for S₁ and S₂ were achieved. Figure 15 and Figure 16 show the current waveform of resonant inductor i_Lr, diode i_Do, and two switches i_DS2 and i_DS2.

Figure 17 illustrates the waveforms of the gate signals, v_gs1 and v_gs2, and the couple inductors voltage, v_Lm1 and v_Lm2 at 40 V V_in and full load condition. Both v_Lm1 and v_Lm2 had the identical voltage level through one complete switching cycle, and the operating condition was at 40 V V_in and full-load.

Figure 18 shows the waveforms of the gate-to-source v_gs1, the secondary side’s voltage of the coupled inductors v_LS1 and v_LS2, and the current of the output diode i_Do at 40 V V_in and full load condition. v_LS1 and v_LS2, had the identical voltage level through the one complete switching cycle, and when the output diode D_o was to be forward-bias, the output current i_Do was flowing through the secondary side of the coupled inductors L_S1 and L_S2 This meant that the dual coupled inductors provided energy to output capacitor C_o and load.

Figure 19 and Figure 20 show the voltage levels of capacitors C_a and C_a at 25 V V_in, 40 V V_in, and 100% load. The average voltage value of v_Ca was approximately 53.3 V, which is similar to the result of Equation (1).

Figure 21 shows the efficiency curves at 25 V and 40 V V_in. The highest efficiency point was at 40 V V_in under 40% load.

The loss analysis is obtained by recording the stress of the components experimentally and bringing it into the loss Equation (34). P_{S_sw} is the switching loss of the main switch S₁ and the auxiliary switch S₂. P_{S_con} is the conduction loss of the main switch S₁ and the auxiliary switch S₂. P_{D_con} is the conduction loss of the output diode. P_{Tr_core} is the core loss of the two coupled inductors. P_{Tr_core} is the core loss of the two coupled inductors. P_{Lr_core} is the core loss of the resonant inductor. P_{Lr_core} is the core loss of the resonant inductor. The loss obtained by the component parameters and the stress equations was consistent with the actual efficiency. Figure 22 shows the loss distribution at 50% and 100% loads. The highest power loss was the coupled inductor core loss. Although the two switches reached ZVS, the turn-off loss remained high and was the second highest power loss.

$$\begin{gathered} {Loss}_{total}=P_{S_{sw1}}+P_{S_{con1}}+P_{S_{sw2}}+P_{S_{con2}}+P_{D_{con}} \\ +2\left(P_{Tr\_core}+P_{Tr\_copper}\right)+{P_{Lr\_core}+P}_{Lr\_copper} \end{gathered}$$

(34)

5. Conclusions

This study introduces an innovative high-step-up boost converter design featuring two separate coupled inductors. This approach enables the creation of a low-profile implementation, with the secondary side of coupled inductors connected in series to increase the step-up voltage ratio. An active clamp is also incorporated to achieve ZVS, making it particularly well-suited for the design of low-profile solar microinverters. Operating modes throughout a complete switching cycle are described, and key equations are derived. The experimental results on a 300 W, input voltage 25–40 V, and output voltage 200 V prototype are recorded to verify the theoretical analysis. The maximum efficiency was around 94.7%. The proposed converter not only facilitates low-profile designs but also meets the stringent requirements of high step-up voltage ratios.