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14 pages, 3189 KiB

Open AccessArticle

A Novel DNU Self-Recoverable and SET Pulse Filterable Latch Design for Aerospace Applications

by Shixin Wang, Lixin Wang, Min Guo, Yuanzhe Li and Bowang Li

Electronics 2023, 12(5), 1193; https://doi.org/10.3390/electronics12051193 - 1 Mar 2023

Cited by 1 | Viewed by 2151

This paper presents a novel double node upset (DNU) self-recoverable and single event transient (SET) pulse filterable latch design in 28 nm CMOS technology. The loop structure formed by C-elements (CEs) ensures that the latch can self-recover from the DNUs. A Schmitt trigger at the output can filter out transient pulses from anywhere in the circuit. A clock-controlled inverter channel that connects the input to the output reduces the transmission latency. The simulation results show that the proposed design is completely immune to DNUs, and the delay power area product (DPAP) is reduced by more than 50% compared with the previous design. Full article

(This article belongs to the Section Microelectronics)

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13 pages, 1845 KiB

Open AccessArticle

Evaluation of Dynamic Triple Modular Redundancy in an Interleaved-Multi-Threading RISC-V Core

by Marcello Barbirotta, Abdallah Cheikh, Antonio Mastrandrea, Francesco Menichelli, Marco Ottavi and Mauro Olivieri

J. Low Power Electron. Appl. 2023, 13(1), 2; https://doi.org/10.3390/jlpea13010002 - 28 Dec 2022

Cited by 21 | Viewed by 5109

Abstract

Functional safety is a key requirement in several application domains in which microprocessors are an essential part. A number of redundancy techniques have been developed with the common purpose of protecting circuits against single event upset (SEU) faults. In microprocessors, functional redundancy may be achieved through multi-core or simultaneous-multi-threading architectures, with techniques that are broadly classifiable as Double Modular Redundancy (DMR) and Triple Modular Redundancy (TMR), involving the duplication or triplication of architecture units, respectively. RISC-V plays an interesting role in this context for its inherent extendability and the availability of open-source microarchitecture designs. In this work, we present a novel way to exploit the advantages of both DMR and TMR techniques in an Interleaved-Multi-Threading (IMT) microprocessor architecture, leveraging its replicated threads for redundancy, and obtaining a system that can dynamically switch from DMR to TMR in the case of faults. We demonstrated the approach for a specific family of RISC-V cores, modifying the microarchitecture and proving its effectiveness with an extensive RTL fault-injection simulation campaign. Full article

(This article belongs to the Special Issue RISC-V Architectures and Systems: Hardware and Software Perspectives)

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12 pages, 2021 KiB

Open AccessArticle

A Fully Polarity-Aware Double-Node-Upset-Resilient Latch Design

by Jung-Jin Park, Young-Min Kang, Geon-Hak Kim, Ik-Joon Chang and Jinsang Kim

Electronics 2022, 11(15), 2465; https://doi.org/10.3390/electronics11152465 - 8 Aug 2022

Cited by 7 | Viewed by 2776

Abstract

Due to aggressive scaling down, multiple-node-upset hardened design has become a major concern regarding radiation hardening. The proposed latch overcomes the architecture and performance limitations of state-of-the-art double-node-upset (DNU)-resilient latches. A novel stacked latch element is developed with multiple thresholds, regular architecture, increased number of single-event upset (SEU)-insensitive nodes, low power dissipation, and high robustness. The radiation-aware layout considering layout-level issues is also proposed. Compared with state-of-the-art DNU-resilient latches, simulation results show that the proposed latch exhibits up to 92% delay and 80% power reduction in data activity ratio (DAR) of 100%. The radiation simulation using the dual-double exponential current source model shows that the proposed latch has the strongest radiation-hardening capability among the other DNU-resilient latches. Full article

(This article belongs to the Special Issue Radiation Tolerant Electronics, Volume II)

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11 pages, 7528 KiB

Open AccessArticle

Design, Application, and Verification of the Novel SEU Tolerant Abacus-Type Layouts

by Yi Sun, Zhi Li, Ze He and Yaqing Chi

Electronics 2021, 10(23), 3017; https://doi.org/10.3390/electronics10233017 - 3 Dec 2021

Cited by 2 | Viewed by 1953

Abstract

Radiation tolerance improvements for advanced technologies have attracted considerable interests in space application. In this paper, the single event upset (SEU) hardened double interlocked storage cell (DICE) D-type flip-flops (DFFs) with abacus-type time-delay cell are proposed and successfully implemented in our test chips. The layout structures of two kinds of abacus-type time-delay cells are illustrated, and their hardening effectiveness are verified by our simulations and heavy ion irradiations. The systematic heavy ion experimental results show that the applied abacus-type time-delay cells can reduce the SEU cross sections of DICE DFFs significantly, and even the SEU immune is observed for the full “0” data pattern. Besides, an apparent test mode dependency of the abacus-type hardened circuits is also observed. The results indicate that the nanoscale abacus structure may be suitable for space application in harsh radiation environment. Full article

(This article belongs to the Special Issue Extreme-Environment Electronics: Challenges and Solutions)

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15 pages, 34443 KiB

Open AccessArticle

LIHL: Design of a Novel Loop Interlocked Hardened Latch

by Hui Xu, Xuan Liu, Guo Yu, Huaguo Liang and Zhengfeng Huang

Electronics 2021, 10(17), 2090; https://doi.org/10.3390/electronics10172090 - 28 Aug 2021

Cited by 4 | Viewed by 2603

Abstract

A single event causing a double-node upset is likely to occur in nanometric complementary metal-oxide-semiconductor (CMOS). Contemporary hardened latch designs are insufficient in meeting high reliability, low power consumption, and low delay. This paper presents a novel soft error hardened latch, known as a loop interlocked hardened latch (LIHL). This latch consists of four modified cross-coupled elements, based on dual interlocked storage cell (DICE) latch. The use of these elements hardens the proposed LIHL to soft errors. The simulation results showed that the LIHL has single-event double upset (SEDU) self-recoverability and single-event transient (SET) pulse filterability. This latch also reduces power dissipation and propagation delay, compared to other SEDU or SET-tolerant latches. Full article

(This article belongs to the Section Semiconductor Devices)

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15 pages, 2163 KiB

Open AccessArticle

Research on EDAC Schemes for Memory in Space Applications

by Mengfu Chen, Chenguang Guo, Lei Chen, Wenjie Li, Fan Zhang, Xiaoxiang Hu and Jiancheng Xu

Electronics 2021, 10(5), 533; https://doi.org/10.3390/electronics10050533 - 25 Feb 2021

Cited by 6 | Viewed by 3246

Abstract

Memory used for storing the configuration bitstream of field programmable gate array in space applications often encounters single event upset problems, which may disrupt the integrity of data in memory and lead to unpredictable failures. For commercial memories used in low Earth orbit (LEO), single-bit errors and double-byte errors account for a large proportion. Meanwhile, error detection and correction (EDAC) schemes, e.g., triple modular redundancy, linear block codes, memory scrubbing, and the combination of these schemes, are very popular in LEO missions. To further these works, a novel EDAC scheme with cascaded “Bose–Chaudhuri–Hocquenghem and cyclic redundancy check” codes and a proper scrubbing method is presented in this paper. The performance of the proposed design is measured and compared with state-of-the-art EDAC schemes in terms of hardware overhead, time overhead and error correction and detection capabilities. It is concluded that the proposed EDAC scheme is better suited for memory in space applications. Full article

(This article belongs to the Section Circuit and Signal Processing)

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8 pages, 1039 KiB

Open AccessArticle

A Novel High-Performance Low-Cost Double-Upset Tolerant Latch Design

by Jianwei Jiang, Wenyi Zhu, Jun Xiao and Shichang Zou

Electronics 2018, 7(10), 247; https://doi.org/10.3390/electronics7100247 - 12 Oct 2018

Cited by 15 | Viewed by 3631

Abstract

Single event double upsets (SEDUs) caused by charge sharing have been an important contributor to the soft error in integrated circuits. Most of the up-to-date double-upset (DU) tolerant latches suffer from high costs in terms of delay, power and area. In this paper, we propose a novel high-performance low-cost double-upset tolerant (HLDUT) latch. Simulation waveforms have validated the double-upset tolerance of the proposed latch. Besides, detailed comparisons demonstrate that our design saves 805.24% delay-power-area product (DPAP) on average compared with other considered up-to-date double-upset tolerant latches, which means the proposed latch is a promising candidate for future highly reliable low-cost applications. Full article

(This article belongs to the Section Microwave and Wireless Communications)

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