Research on EDAC Schemes for Memory in Space Applications

Abstract

Memory used for storing the configuration bitstream of field programmable gate array in space applications often encounters single event upset problems, which may disrupt the integrity of data in memory and lead to unpredictable failures. For commercial memories used in low Earth orbit (LEO), single-bit errors and double-byte errors account for a large proportion. Meanwhile, error detection and correction (EDAC) schemes, e.g., triple modular redundancy, linear block codes, memory scrubbing, and the combination of these schemes, are very popular in LEO missions. To further these works, a novel EDAC scheme with cascaded “Bose–Chaudhuri–Hocquenghem and cyclic redundancy check” codes and a proper scrubbing method is presented in this paper. The performance of the proposed design is measured and compared with state-of-the-art EDAC schemes in terms of hardware overhead, time overhead and error correction and detection capabilities. It is concluded that the proposed EDAC scheme is better suited for memory in space applications.

1. Introduction

It is well known that data stored in memory chips suffer from single event upsets (SEUs) in space applications. Bit-flips are induced naturally by cosmic radiation, extreme temperature, electromagnetic radiation, etc. There is a famous experiment of SEU observations for commercial memories based on the Alsat-1 satellite in low Earth orbit (LEO). The Alsat-1 was launched on November 2002 and the experiment lasted over eight years.

Table 1. Single event upset (SEU) observations for Alsat-1.

System Monitored	Parameters
Memory Size	32 M-Bytes
Observation period	2622 days, 29 November 2002–14 August 2010
Bits monitored	268,435,456
Total number of errors	265,649
No. of Single-bit errors	261,905 (98.59%)
No. of Double-byte errors	3249 (1.223%)
No. of Severe errors	247 (0.093%)
No. of Multiple-bit errors	233 (0.087%)
No. of Hardware errors	15 (0.005%)

shows a summary of 32 MBytes Ramdisk of SEU observations [1]. The probability of single-bit errors is the highest, which is 98.59%, followed by the probability of double-byte errors, which is 1.223% and is dominated by double-bit error in single-byte.

Error detection and correction (EDAC) technologies which can detect and correct errors in a certain degree are very popular in improving the reliability of memory devices. For the transmission of secure data between devices and its local memory, triple modular redundancy (TMR) is widely used for anti-SEU design, but its probabilistic error correction ability can cause cumulative error [2,3]. Another disadvantage of TMR is its large memory overhead (200%) [4]. Linear block codes are also well-known and widely used. However, for the error correction requirements in Table 1, these famous linear block codes, e.g., Hamming code, Parity code, Berger code, are not available because of the limitation of their error-correcting capabilities [5,6]. In addition, linear block codes with excessive error-correcting capabilities (e.g., LDPC, Reed–Solomon Code) are not necessary because they will increase design complexity and cause large hardware overhead [7,8]. For scrubbing methods which are also famous in space applications, it is too time-consuming to rewrite the entire memory [9]. Besides, some researchers have found a transistor-level EDAC method with small hardware overhead, which helps design the radiation-hardened memory cell library but is not suitable for error correction, in Table 1 [10,11,12].

Figure 1 shows the block diagram of an SRAM-based field programmable gate array (FPGA) in space applications. Once SEU occurs, it will lead to data flipping of the memory chip, which will affect the logical state of the FPGA, or even threaten the safety of the FPGA, resulting in irreparable failures [13]. An in-orbit controller acts as a bridge for the FPGA and its configuration memories. Programmable read-only memory (PROM) which is immune to SEU can be programmed only once. The bitstream stored in the PROM is usually used for the initialization of the FPGA, while the bitstream stored in the memory array is usually used for the functional reconfiguration of the FPGA. In addition, the bitstream stored in the memory array has the function of in-orbit maintenance and update through universal asynchronous receiver/transmitter (UART).

In order to improve the reliability of data in the memory array, the in-orbit controller is usually designed to detect and correct the configuration bitstream that may be affected by SEU. The corresponding steps are as follows:

(1)

Data encoding: The configuration data are received through the UART, and then redundant encoding is performed by EDAC method.

(2)

Periodic readback checking: Check the data stored in the memory array periodically through the FPGA readback function.

(3)

Periodic scrubbing: According to the scrub interval set in advance, the memory array can be rewritten unconditionally by continuous scrubbing.

This paper focuses on hardware implemented EDAC schemes for memory in space applications. Section 2 presents the state-of-the-art EDAC schemes for memory in space applications. Then, a novel proposed EDAC scheme is given in Section 3. Section 4 analyzes experimental results. Finally, conclusions are drawn in Section 5.

2. Present State-of-the-Art EDAC Schemes

EDAC is committed to adding redundant bits to data in a specific way. When the data is corrupted, the redundant bits can help to identify and eliminate the corruption in a certain range. There are many EDAC schemes that meet the design purpose of this paper [14,15,16]. At present, the EDAC schemes that have been applied to space applications include TMR, linear block codes, memory scrubbing, and the combination of these schemes.

2.1. TMR

TMR is widely used for anti-SEU design. The implementation consists of three identical memories storing the same data and a voter [2,3], as shown in Figure 2. The voter outputs the majority of the data from the three memories, so that when SEU occurs in one of the memories, the output remains valid. Since the probability of error events occurring simultaneously in two memories is minimal, the error correction ability of the circuit can be improved by the TMR.

However, there is still a certain probability of error decoding, resulting in cumulative error after subsequent propagation. Furthermore, as can be seen from Figure 2, memory overhead is a major drawback of the TMR. It wastes twice the required memory.

2.2. Linear Block Code Schemes

The EDAC circuit for memory array including an encoder and a decoder is shown in Figure 3. The encoder generates redundant data bits based on input data, while the decoder uses redundant data bits to detect and eliminate errors in a certain range. For linear block code (n, k), the number of codeword data bits, encoded data bits and redundant data bits are n, k and c ($c=n-k$), respectively. Therefore, the encoder has k-bit input and n-bit output, while the decoder has n-bit input and k-bit output. However, for the data bus of the memory array, a DDR ×8 chip with a bit width of eight is one of the most common options.

Typically, there are four parameters used to measure the performance of linear block codes, i.e., error correction capacity ($t_c$), error detection capacity ($t_d$), code rate and bit overhead. They are expressed by

$$\begin{array}{cc}\hfill & t_c=\frac{d-1}{2}\hfill \end{array}$$

(1)

$$\begin{array}{cc}\hfill & t_d=d-1\hfill \end{array}$$

(2)

$$\begin{array}{cc}\hfill & CodeRate=\frac{k}{n}\hfill \end{array}$$

(3)

$$\begin{array}{cc}\hfill & BitOverhead=\frac{c}{k}\hfill \end{array}$$

(4)

where d is the minimum Hamming distance. In addition, time and space complexity needs to be considered to measure the efficiency of coding schemes.

According to the data in Table 1, it is necessary to select the coding scheme with proper Hamming distance so that $t_c$ is equal to two or slightly higher. Therefore, some of the schemes, such as Hamming code, Parity code, Berger code, etc., do not meet this requirement [5,6]. In addition, Reed–Solomon code which is good at correcting non-binary codes is not considered in this paper [17].

Table 2. Linear block code schemes with proper $t_c$.

Code	Scheme (n,k,d)	${\mathit{t}}_{\mathit{d}}$	${\mathit{t}}_{\mathit{c}}$	Code Rate	Bit Overhead	Complexity
						Time	Space
Hadamard	(16,5,8)	7	3	31.25%	220%	$O\left(nlo{g}_{2}n\right)$	$O\left(nlo{g}_{2}n\right)$
Binary Golay	(23,12,7)	6	3	52.17%	91.66%	$O\left(pq\right)$	$O(2^q$)
Ternary Golay	(11,6,5)	4	2	54.54%	83%	$O\left(pq\right)$	$O(2^q$)
BCH	(15,7,5)	-	2	46.67%	114.29%	$O\left(q^2\right)$	$O\left(pn\right)$
	(31,21,5)	-	2	67.74%	47.62%
	(63,51,5)	-	2	80.95%	23.53%
	(127,113,5)	-	2	88.98%	12.39%
	(255,239,5)	-	2	93.73%	6.69%
4D Parity	(561,560)	-	2	84.21%	18.56%	$O\left(pn\right)$	$O\left(pn\right)$
	(2193,2048)	-	2	87.67%	13.28%

shows linear block code schemes with proper error correction capabilities, where $p\times q$ means the size of memory block.

As can be seen from Table 2, Hadamard code has the lowest time and space complexity, but the ratio of code rate to bit overhead (C2B) is also the lowest, which means that the coding overhead is too high. Compared to Hadamard code, Golay codes have better coding overhead, but they are still not good enough. As the length of the Bose–Chaudhuri–Hocquenghem (BCH) code increases, the size of the corresponding memory block increases and the C2B ratio becomes better, but the time complexity increases exponentially [18]. 4D Parity codes have great C2B ratio and great time and space complexity. A big problem of 4D Parity codes is that it is applicable to the whole memory block, and its error correction and detection capability needs to be applied to the whole memory block, which means that the error correction and error detection time will be sacrificed in a certain degree [19,20].

2.3. TMR Based EDAC

To further improve the reliability of data in memory array, the combination of TMR and linear block code is very effective [4,21,22], as shown in Figure 4 and Figure 5.

Both circuits inherit the error correction and detection function of the linear block code and the redundancy of TMR technology. However, the circuit shown in Figure 4 requires an additional two times the required memory, while the circuit shown in Figure 5 requires an additional eight times the required EDAC module and one time the required memory.

2.4. Memory Scrubbing

There are two kinds of scrubbing operation, one is scrubbing based on the UART in a fixed interval, the other is scrubbing based on the EDAC circuit [23,24]. For the former, the memory is rewritten unconditionally and the scrubbing interval is set according to the SEU rate. For the latter, the SEU is scrubbed out sequentially by decoding and rewriting operations. Since the EDAC circuit has inherent error correction and detection capabilities, potential errors can be automatically corrected and overridden. Memory scrubbing is also an effective EDAC solution, but the problem is that rewriting all data in memory is extremely time-consuming.

3. A New Proposed EDAC Scheme

For the purpose of reducing hardware and time overhead while meeting the anti-SEU requirements shown in Table 1, this section presents a new EDAC scheme by designing a cascaded code scheme and an improved scrubbing method.

3.1. Cascaded Code Scheme

Taking into account the time and space complexity and the C2B ratio in Table 2, BCH and 4D parity codes are suitable for data protection of memory in space applications. However, 4D parity codes have greater time overhead than BCH in response to errors, which can adversely affect memory scrubbing. Accordingly, this paper prefers BCH codes with similar C2B ratios to 4D parity codes.

Figure 6 illustrates the effect of increasing code length on C2B ratio of BCH and 4D parity codes. Greater code length means greater space complexity and greater hardware overhead. Therefore, the middle BCH(63, 51, 5) which has similar C2B ratio to 4D parity codes is more appropriate for single-bit and double-bit error correction. For other error cases with less error probability in Table 1, this paper uses cyclic redundancy check 32 (CRC32) code which has high error detection ability for error checking.

Figure 7 shows the block diagram of the proposed EDAC system. Because the data bit width of the memory array in this paper is 8 bits, in byte, the calculation parallelism of the encoders (i.e., CRC_EN and BCH_EN) and decoders (i.e., CRC_DE and BCH_DE) designed below is eight bits.

3.2. BCH

For BCH(63, 51, 5) over GF(2) and GF($2^6$), the data polynomial $m\left(x\right)$ and the generator polynomial $g\left(x\right)$ are defined as

$$\begin{array}{cc}\hfill & m\left(x\right)=m_0+m_{1}x+\cdots +m_{50}{x}^{50}\hfill \end{array}$$

(5)

$$\begin{array}{cc}\hfill & g\left(x\right)=x^{12}+x^{10}+x^8+x^5+x^4+x^3+1\hfill \end{array}$$

(6)

3.2.1. Encoding

The codeword polynomial $c\left(x\right)$ is given by

$$\begin{array}{cc}\hfill & c\left(x\right)=p\left(x\right)+x^{12}m\left(x\right)\hfill \end{array}$$

(7)

where the remainder is

$$\begin{array}{cc}\hfill & p\left(x\right)=x^{12}m\left(x\right)modg\left(x\right)\hfill \end{array}$$

(8)

Let

$$\begin{array}{cc}\hfill M_i=& m_{8i+7}{x}^7+m_{8i+6}{x}^6+\cdots +m_{8i+1}x+m_{8i},\hfill \\ \hfill i=& 0,1,\cdots ,6.\hfill \end{array}$$

(9)

where $m_{55}$,$m_{54}$,…,and $m_{51}$ are zeros. Then

$$\begin{array}{cc}\hfill p\left(x\right)=& x^{12}m\left(x\right)modg\left(x\right)\hfill \\ \hfill =& \left(\right((((((M_6{x}^8+M_5)x^8+M_4)x^8+M_3)x^8+M_2)x^8\hfill \\ \hfill & +M_1)x^8+M_0)x^8+0)x^{4}modg\left(x\right)\hfill \end{array}$$

(10)

Since the encoded data bits cannot be divisible by eight, the formula for the first eight iterations of the encoder is

$$\begin{array}{cc}\hfill p_i{\left(x\right)}_1=& (p_{i-1}\left(x\right)x^8+M_i)modg\left(x\right)\hfill \\ \hfill =& p_{i-1}\left(x\right)x^{8}modg\left(x\right)+M_i\hfill \end{array}$$

(11)

and the formula for the last iteration of the encoder is

$$p_i{\left(x\right)}_2=p_{i-1}\left(x\right)x^{4}modg\left(x\right)$$

(12)

Accordingly, the schematic of the 8-bit parallel BCH(63, 51, 5) encoder is shown in Figure 8.

Then the codeword vector is given by

$$\begin{array}{cc}\hfill (c_{62},c_{61},\cdots ,c_1,c_0)=& (m_{50},m_{49},\cdots ,m_1,m_0,\hfill \\ \hfill & p_{11},p_{10},\cdots ,p_1,p_0)\hfill \end{array}$$

(13)

3.2.2. Decoding

The decoding process of BCH includes three steps:

(1)

Computing the syndrome polynomial $s\left(x\right)$ based on the input $r\left(x\right)$ to the decoder.

(2)

Calculating the error location polynomial $\Lambda \left(x\right)$ by the key equation.

(3)

Calculating the roots ($e\left(x\right)$) of $\Lambda \left(x\right)$ by Chien search algorithm, and correcting errors based on the roots:

$$\widehat{c}\left(x\right)=r\left(x\right)-e\left(x\right)$$

(14)

The flow of BCH decoding is shown in Figure 9.

(1) Syndrome

For BCH codes that can correct two bits errors, the number of syndrome values $s_i$ should be four. $s_i$ is defined as

$$s_i=\sum _{j=0}^{n-1}{r}_j{\left({\alpha }^i\right)}^j=r_0{\left({\alpha }^i\right)}^0+r_1{\left({\alpha }^i\right)}^1+\cdots +r_{n-1}{\left({\alpha }^i\right)}^{n-1}$$

(15)

where $\alpha$ is the primitive element of GF($2^6$).

For 8-bit parallel computing, the above formula can be derived as

$$\begin{array}{cc}\hfill s_i=& \left(0{\alpha }^7+r_{62}{\alpha }^6+\cdots +r_{56}\right){\alpha }^{56}+\left(r_{55}{\alpha }^7+r_{54}{\alpha }^6+\cdots \right.\hfill \\ \hfill & \left.+r_{48}\right){\alpha }^{48}+\cdots +\left(r_7{\alpha }^7+r_6{\alpha }^6+\cdots +r_0\right)\hfill \end{array}$$

(16)

The corresponding calculation circuit is shown in Figure 10.

(2) Key equation

The error location polynomial $\Lambda \left(x\right)$ for the BCH(63, 51, 5) is defined as

$$\Lambda \left(x\right)={\lambda }_0+{\lambda }_{1}x+{\lambda }_2{x}^2$$

(17)

and can be calculated by the SiBM algorithm through the key equation

$$s\left(x\right)\Lambda \left(x\right)=\Omega \left(x\right)mod{x}^4$$

(18)

where $\Omega \left(x\right)$ is the error value polynomial. The SiBM algorithm and its formula derivation process are described in detail in Ref. [25].

Figure 11 and Figure 12 show the implementation of the SiBM algorithm for the BCH(63, 51, 5) and its basic processing element (PE), respectively.

After two iterations, the output of the registers ($R_0\sim R_2$) shown in Figure 11 is the coefficients (${\lambda }_0\sim {\lambda }_2$) of the error location polynomial $\Lambda \left(x\right)$.

(3) Chien search

The Chien search algorithm searches the error location by checking whether $\Lambda \left({\alpha }^i\right)$ is zero. $\Lambda \left({\alpha }^i\right)$ can be written as

$$\begin{array}{cc}\hfill \Lambda \left({\alpha }^i\right)=& \sum _{j=0}^2{\lambda }_j{\alpha }^{ij}=\sum _{j=1}^2{\lambda }_j{\alpha }^{ij}+{\lambda }_0,\hfill \\ \hfill i=& 0,1,\cdots ,62.\hfill \end{array}$$

(19)

If $\Lambda \left({\alpha }^i\right)$ is equal to zero, it means that the input data $r_i$ has an error, otherwise there is no error. For 8-bit parallel computing, eight of the above formulas are calculated simultaneously, as shown in Figure 13.

After Chien search, the roots ($e\left(x\right)$) of $\Lambda \left(x\right)$ are calculated. Then errors in the decoded codeword $\widehat{c}\left(x\right)$ can be corrected by Formula (14).

3.3. CRC

Since the BCH(63, 51, 5) is not sensitive to errors greater than two bits, CRC code can be used as a supplement for error detection of other error cases shown in Table 1. The probability of missed detection of the CRC32 is $2^{-32}$, which can cover almost all error cases in Table 1.

CRC code is mainly used for the binary data. The data polynomial $m\left(x\right)$ and the generator polynomial $g\left(x\right)$ of the CRC32 are defined as

$$\begin{array}{cc}\hfill m\left(x\right)=& m_0+m_{1}x+\cdots +m_{63}{x}^{63}\hfill \end{array}$$

(20)

$$\begin{array}{c}\hfill \begin{array}{cc}\hfill g\left(x\right)=& x^{32}+x^{26}+x^{23}+x^{22}+x^{16}+x^{12}+x^{11}\hfill \\ \hfill & +x^{10}+x^8+x^7+x^5+x^4+x^2+x+1\hfill \end{array}\end{array}$$

(21)

where $m_{63}$ is zero.

3.3.1. Encoding

The encoding process of the CRC32 is similar to the BCH(63, 51, 5). The codeword polynomial $c\left(x\right)$ is given by

$$\begin{array}{cc}\hfill & c\left(x\right)=p\left(x\right)+x^{32}m\left(x\right)\hfill \end{array}$$

(22)

where the remainder is

$$\begin{array}{cc}\hfill & p\left(x\right)=x^{32}m\left(x\right)modg\left(x\right)\hfill \end{array}$$

(23)

Let

$$\begin{array}{cc}\hfill M_i=& m_{8i+7}{x}^7+m_{8i+6}{x}^6+\cdots +m_{8i+1}x+m_{8i},\hfill \\ \hfill i=& 0,1,\cdots ,7.\hfill \end{array}$$

(24)

Then

$$\begin{array}{cc}\hfill p\left(x\right)=& x^{32}m\left(x\right)modg\left(x\right)\hfill \\ \hfill =& \left(\right(\left(\right(\left(\right(((((M_7{x}^8+M_6)x^8+M_5)x^8+M_4)x^8\hfill \\ \hfill & +M_3)x^8+M_2)x^8+M_1)x^8+M_0)x^8\hfill \\ \hfill & +0)x^8+0)x^8+0)x^{8}modg\left(x\right)\hfill \end{array}$$

(25)

The formula for the iterations of the encoder is

$$\begin{array}{cc}\hfill p_i\left(x\right)=& (p_{i-1}\left(x\right)x^8+M_i)modg\left(x\right)\hfill \\ \hfill =& p_{i-1}\left(x\right)x^{8}modg\left(x\right)+M_i\hfill \end{array}$$

(26)

Accordingly, the schematic of the 8-bit parallel CRC32 encoder is shown in Figure 14.

After 13 iterations, the codeword vector is given by

$$\begin{array}{cc}\hfill (c_{95},c_{94},\cdots ,c_1,c_0)=& (m_{63},m_{62},\cdots ,m_1,m_0,\hfill \\ \hfill & p_{31},p_{10},\cdots ,p_1,p_0)\hfill \end{array}$$

(27)

3.3.2. Decoding

The decoding process of the CRC32 is similar to its encoding process. The novel remainder is

$$\begin{array}{cc}\hfill & \widehat{p}\left(x\right)=r\left(x\right)modg\left(x\right)\hfill \end{array}$$

(28)

where $r\left(x\right)$ is the received input data from memory.

The schematic of the 8-bit parallel CRC32 decoder is shown in Figure 15.

After 13 iterations, if the bitwise-OR result of $\widehat{p}\left(x\right)$ is equal to zero, it indicates that the input $r\left(x\right)$ has no error, otherwise an error is detected.

3.4. Proposed EDAC Process

The proposed EDAC process includes data encoding, periodic readback checking and scrubbing, respectively.

(1) Data encoding: Each 51 bits of data received through the UART is encoded by the BCH_EN to 63 bits. After adding one bit zero, the new 64 bits data are encoded by the CRC_EN to 96 bits. The codeword vector stored in memory array is

$$\begin{array}{cc}\hfill (c_{95},c_{94},\cdots ,c_1,c_0)=& (0,m_{50},m_{49},\cdots ,m_1,m_0,\hfill \\ \hfill & p_{b11},p_{b10},\cdots ,p_{b1},p_{b0},\hfill \\ \hfill & p_{c31},p_{c30},\cdots ,p_{c1},p_{c0}),\hfill \end{array}$$

(29)

where $p_{bi}$ and $p_{ci}$ means that the remainder values of the BCH_EN and the CRC_EN, respectively. In addition, as each 51 bits of data are compiled to 96 bits, the memory overhead of the proposed scheme will increase by 88.24%.

(2) Periodic readback checking: Check the data stored in memory array periodically through the FPGA readback function. The errors in Table 1 are divided into three cases, i.e., no errors, single-bit or double-bit errors and multiple-bit errors which have more than two bits errors. The corresponding decoding process are:

• No errors: Both the BCH_DE and the CRC_DE indicate that there are no errors.
• Single-bit or double-bit errors: If the decoding result of the BCH_DE is wrong, the decoded 51 bits data are encoded again by the BCH_EN and written to the blank area of the memory array. Using new encoded data and the old CRC redundant bits, the CRC_DE can identify whether the error has been corrected by the BCH_DE. If yes, overwrite the original data in the memory array with the new encoded data. Otherwise, it means that there are multiple-bit errors and the corresponding memory address should be marked.
• Multiple-bit errors: Other than the above multiple-bit errors, if the decoding result of the BCH_DE is right and the decoding result of the CRC_DE is wrong, it also means that there are multiple-bit errors and the corresponding memory address should be marked.

(3) Scrubbing: According to the marked memory addresses, memory array can be partially rewritten through the UART.

Obviously, the probability of the multiple-bit errors in Table 1 is relatively small, which means that the scrubbing step is rarely implemented. Therefore, the proposed memory scrubbing method is very time-saving.

4. Experimental Results

The proposed EDAC scheme was implemented in an In-orbit controller chip (Bsv5cbrh) of Beijing Microelectronics Technology Institute as described in Section 3. The EDAC system shown in Figure 7 was verified both in function and timing. Meanwhile, a PCB-level fault injection system based on Figure 1 was developed to validate the proposed scheme, including Bsv5cbrh, Xq5vsx95t, Xcf32p, etc., as shown in Figure 16. The proposed approach of the in-orbit controller was implemented based on the process described in Section 3.4. Correspondingly, the relationship between EDAC capability and the use of EDAC resources is shown in

Table 3. Relationship between EDAC capability and the use of EDAC resources.

	No Errors	SED	SEC	DED	DEC	MED		MEC
BCH_EN		✓	✓	✓	✓		✓	✓	✓
BCH_DE	✓	✓	✓	✓	✓	✓	✓	✓	✓
CRC_EN								✓	✓
CRC_DE	✓	✓	✓	✓	✓	✓	✓	✓	✓
Scrubbing								✓	✓

Note: SED: single error detection, SEC: single error correction, DED: double error detection, DEC: double error correction, MED: multiple error detection, MEC: multiple error correction.

.

Based on the description of Section 3.4, it can be indicated from the results of the BCH_DE and the CRC_DE if there were no errors. For single-bit errors, all the locations in the memory were simulated to ensure 100% fault coverage. The result of the CRC_DE should be correct in this case. The BCH_EN was used to encode the decoded data from the BCH_DE, and the BCH_DE was used twice to check whether the error can be corrected or not. For double-bit errors in each 63-bit, pseudo-random sequence (i.e., Pseudo-Noise Code) to simulate the fault injection address was used, in which case the corresponding 32-bit data checked by the CRC_DE should also be correct. The use of EDAC resources in this case was the same as the use of EDAC resources to handle single-bit errors. For multiple-bit error detection, there was no need to rewrite the whole memory or the memory corresponding to the marked address, it could be judged by the combination of the results from the BCH_DE and the CRC_DE. Accordingly, the uses of EDAC resources were similar to the two cases described earlier (i.e., no errors and single-bit errors). For multiple-bit error correction, in addition to the previous case, memory scrubbing function was triggered to ensure 100% error correction, in which case all EDAC resources were used.

To measure the performance of the proposed EDAC, a comparison between the state-of-the-art EDAC schemes and the proposed EDAC scheme is shown in

Table 4. Comparison of experimental results.

EDAC Type	TMR	EDAC-TMR 1 [4]	EDAC-TMR 2 [26]	The Proposed EDAC
EDAC overhead	0	0	800%	100%
Memory overhead	200%	200%	100%	88.24%
Time overhead	$t_V$	$t_E+t_V$	$t_E+2t_V$	$t_E$
EDAC Capability	MEC-MED	DEC-DED	DEC-DED	MEC-MED
Severe errors correction	NO	YES	YES	YES
Corrected in-orbit errors	98.7%	100%	100%	100%

Note: t_E: EDAC delay time, t_V: Voter delay time.

. The overall memory overhead is an increase of 88.24% in stored data, which is smaller than when using TMR or EDAC-TMR methods. The overall EDAC overhead is an increase of 100% in EDAC module, which is significantly smaller than when using EDAC-TMR method shown in Ref. [26]. The time overhead of the proposed EDAC is greater than the time overhead of TMR but less than the time overhead of EDAC-TMR methods shown in Table 4. Furthermore, since it inherited the error correction and detection capability of the cascaded “BCH(63, 51, 5) and CRC32” codes, the proposed EDAC scheme could correct single-bit and double-bit errors and detect multiple-bit errors. By memory scrubbing circuit, the proposed EDAC scheme could also correct multiple-bit errors. Hence, the proposed EDAC scheme had the highest error detection and correction capability shown in Table 4.

Based on the proposed EDAC scheme, the encoding delay for the cascaded “BCH_EN and CRC _EN” was only 21 clock cycles, while the decoding delays for the BCH_DE and the CRC_DE were 20 clock cycles and 13 clock cycles, respectively. In addition, instead of rewriting all data in memory in a certain interval, the proposed EDAC scheme automatically scrubbed out single-bit errors and double-bit errors through the proposed EDAC circuit, and overrode the data through the UART with the marked memory addresses. For memory scrubbing based on the EDAC circuit, the proposed design could correct errors after 96 bits data were detected, while the design based on 4D parity codes must correct errors after a whole memory block was detected. For memory scrubbing through the UART, the memory addresses were marked only if there were multiple-bit errors in each 96-bit block, severe errors, and hardware errors shown in Table 1, which meant that the probability of memory scrubbing through the UART was less than 1.408%. Therefore, compared to the error-correcting time based on the EDAC circuit using 4D parity codes and the rewriting time for the whole memory, the proposed scrubbing method was relatively time-saving.

5. Conclusions

This paper has presented a novel EDAC scheme of the In-orbit controller chip (Bsv5cb rh) for memory in space applications. The EDAC scheme is based on the combination of the cascaded “BCH(63, 51, 5) and CRC32” codes and an improved scrubbing method. This scheme is sufficient to handle the typical SEU rate at LEO environment. The design is verified both in function and timing. The overall system cost is significantly smaller than the present state-of-the-art EDAC schemes. Experiments to simulate the error cases in Table 1 have shown that 100% of the errors can be detected and corrected.