Search Results (405)

Cell degradation in second-life battery packs introduces heterogeneous capacity and internal resistance mismatch, reducing the effectiveness of conventional balancing approaches and limiting available pack runtime. Although equal state of charge (SoC) does not necessarily imply equal usable capacity, SoC-based control remains attractive for runtime-oriented operation. This paper proposes a target-mean controller for heterogeneous reconfigurable battery packs under constant-bus constraints that aims to improve runtime and achieve the cutoff-defined theoretical maximum capacity utilization limit. Using only real-time cell SoC measurements and legal switching actions, the controller selects the configuration that best reduces deviation from the pack-average SoC while preferentially loading cells above the mean. The online action selection requires no active balancing hardware, no explicit capacity or state of health (SoH) estimation, and no offline optimization; experimentally measured capacities are used only for calibrated Coulomb-counting SoC estimation. Simulation results on a heterogeneous five-cell reconfigurable battery pack show that the proposed controller reaches the cutoff-defined 90% theoretical utilization limit in the full-initial-SoC cases, while also extending runtime and reducing switching activity by up to 11.75% relative to the comparison methods. Hardware validation on a five-cell prototype further confirms this trend, achieving 89.12% experimental utilization, zero final SoC spread, and higher delivered energy than both comparison methods. A stepped-load hardware test further achieved 88.19% utilization from current integration, corresponding to 97.99% of the cutoff-defined 90% theoretical limit. The results suggest that, for heterogeneous second-life packs, SoC-based reconfiguration control can achieve both runtime improvement and near-maximum utilization without the added complexity of explicit SoH-aware balancing. Full article

Field-programmable gate array (FPGA)-based reconfigurable system-on-chip (SoC) platforms are increasingly deployed in safety-critical domains such as autonomous driving and industrial automation, yet the existing literature lacks a systematic assessment of how these designs address functional safety requirements. This paper presents a systematic review of 36 peer-reviewed studies (core period 2010–2024, with historical context from 1998) on FPGA-based reconfigurable parallel processing SoCs, analyzed through three frameworks: a convergence–divergence analysis (CDA) that provides a structured exploratory lens for identifying research trajectory trends and informing hypothesis generation; a safety-critical gap analysis benchmarked against a three-layer standard framework comprising ISO 26262 (functional safety), ISO 21448/SOTIF (safety of the intended functionality), and ISO/PAS 8800 (AI safety properties); and a four-dimensional design space taxonomy spanning reconfigurability granularity, parallelism exploitation, design automation level, and safety criticality. The analysis reveals that 33 of the 36 surveyed studies (92%) ignore safety certification entirely. While recent work has begun establishing worst-case execution time (WCET) bounds for FPGA SoC platforms, none of the surveyed FPGA-based AI accelerator studies provide WCET bounds, although recent analytical models for multi-DPU architectures demonstrate the feasibility of such analysis. FPGA CNN accelerators achieve energy efficiencies of up to 60 GOPS/W, and dynamic partial reconfiguration (DPR) yields 2–5× throughput improvements, yet these gains remain unsupported by the formal verification or uncertainty quantification mandated for safety certification. The CDA framework reveals strong convergence between DPR, network-on-chip (NoC), and high-level synthesis research threads (scores 0.72–0.91), indicating maturation toward integrated design flows. We identify conformal prediction as a distribution-free hardware-compatible framework for uncertainty quantification on resource-constrained FPGAs, motivated by requirements from ISO 21448 (triggering event identification) and ISO/PAS 8800 (runtime confidence monitoring), and propose a prioritized research agenda to bridge the gap between FPGA performance optimization and safety-certified deployment in transportation systems. Full article

A Bayesian convolutional neural network (BCNN) quantifies prediction uncertainty by introducing randomness into weights or activations, which is important for safety-critical applications such as medical diagnosis and autonomous driving. However, BCNN inference typically relies on Monte Carlo sampling requiring multiple forward passes, leading to computation and energy consumption far beyond standard CNN hardware acceleration. FPGA, with its parallel processing, reconfigurability, and high-energy efficiency, are ideal platforms for dedicated BCNN accelerators. This paper designs and implements an FPGA acceleration method for BCNN-using high-level synthesis. First, convolution, pooling, and fully connected modules are individually optimized. Then, a mean/variance dual-path parallel expansion is adopted, combined with mixed-precision quantization and global scaling compensation, local reparameterization sampling, parameter reordering, and ping-pong buffering, achieving low resource usage and high-energy efficiency while enabling uncertainty evaluation. Experimental results on Bayes VGG16 show resource utilization of 24,776 LUT, 23,378 FF, 115 BRAM, and 129 DSP, with total power of 2.049 W. Compared with an unoptimized Bayesian implementation, the proposed design reduces inference latency to about one-third, and its latency is only 17% higher than that of the classical VGG16. Compared with PC-based floating-point models, the accuracy loss on four BCNN models (tested on CIFAR-10) is within 1%. The predictive entropy effectively distinguishes normal, noisy, and out-of-distribution (OOD) samples, validating the uncertainty quantification capability of the BCNN FPGA accelerator. Full article

To support Industry 5.0 smart factories that require ultra-low latency and high reliability, this paper proposes a three-layer Intent-Based Zero-Touch Networking (IBZTN) pipeline. Existing Intent-Based Networking (IBN)/Zero-Touch Networking (ZTN) studies often remain conceptual, while Graph Neural Network (GNN)-based Quality of Service (QoS) prediction and Deep Reinforcement Learning (DRL)-based reconfiguration are usually developed as separate modules. The proposed pipeline connects natural-language intent translation, feasibility prediction, and minimal-modification reconfiguration through a validated QoS contract and feasibility-aware closed-loop structure. Layer 1 converts intents into quantitative QoS profiles by combining Retrieval-Augmented Generation (RAG) with schema- and rule-based validation. Layer 2 evaluates feasibility using a Graph Isomorphism Network with Edge features (GINE)-based binary classifier. Layer 3 recovers infeasible states using a Behavior Cloning (BC) Proximal Policy Optimization (PPO) agent with Smart Traffic Engineering (TE) masking. In experiments with 300 natural language intents, RAG+Validator reduced Layer 1 constraint violations to 0.0% for most evaluated cloud and local Large Language Models (LLMs). The Layer 2 predictor achieved a 93.9% F1-score, and Layer 3 achieved an 87.8% recovery success rate with 9.8 average modifications and 5.56 ms inference latency. These results demonstrate the simulation-level potential of IBZTN and motivate future hardware-in-the-loop validation in industrial networks. Full article

This paper presents a modular FPGA-based Smart Multi-Functional Display (SMFD) architecture designed for low-power and real-time avionics applications. Conventional SMFD systems are typically based on tightly coupled monolithic architectures, which limit scalability, maintainability, and subsystem flexibility while increasing system complexity and power consumption. To address these limitations, the proposed architecture separates processing, display, and communication functions into independent hardware modules, enabling flexible system integration and subsystem-level optimization. It consists of four primary modules: an FPGA-based Programmable Logic Device (PLD) module for deterministic video processing and display timing control, an NXP i.MX8X CPU module for application-level management, a high-resolution LCD module, and a dedicated I/O module supporting avionics communication interfaces, including AFDX and RS422. The architecture combines FPGA-assisted real-time processing with power-aware task partitioning strategies to improve both timing predictability and energy efficiency. Experimental evaluation performed on the implemented hardware prototype demonstrates that the proposed architecture achieves approximately 40% reduction in power consumption compared to a conventional baseline configuration while maintaining real-time operational capability with an average processing latency of 12.7 ms. In addition, the FPGA-based implementation enables dynamic display reconfiguration with a measured switching time of approximately 235 ms. The results indicate that the proposed modular architecture provides an effective balance between power efficiency, real-time performance, scalability, and system flexibility for next-generation avionics display applications. Full article

Wireless links in underground coal mines suffer from severe attenuation, blockage, and limited spatial coverage. To improve link quality under these conditions, we study a simultaneously transmitting and reflecting reconfigurable intelligent surface (STAR-RIS)-assisted system with multiple movable antennas (MAs) installed at the base station (BS) panel. Unlike prior models that assume a continuous movement box, we explicitly account for practical panel constraints: mechanical supports and RF feed lines partition the BS panel into non-overlapping irregular feasible subregions. This turns the BS-side antenna-positioning task into a mixed-integer nonlinear program (MINLP). We formulate a joint optimization problem that couples BS beamforming, STAR-RIS transmission/reflection coefficients, BS-side MA positions, and MA-to-subregion assignment with collision-avoidance constraints. To solve it, we adopt a block coordinate descent (BCD) framework: successive convex approximation (SCA) for beamforming, semidefinite relaxation (SDR)-based updates for STAR-RIS coefficients, and a penalty-based continuous relaxation for MINLP handling. The MA solver further integrates Hungarian initialization, cross-region jump updates, and reassignment corrections to escape poor local subregions. Simulation results in coal mine channel settings show that the proposed method yields a 66.7% sum-rate gain over fixed-antenna baselines and reduces required transmit power by 16.8 dB at the target-rate operating point. Compared with a regular-region BS-MA baseline, the irregular-partition design achieves an additional 5.6 dB power saving, demonstrating the practical value of hardware-aware geometry modeling. Full article

The objective of this paper is to introduce the application of quantum annealing (QA) to electromagnetic (EM) engineering. We demonstrate that numerous EM design and inverse problems naturally admit a mathematical formulation in terms of binary quadratic interactions. By utilizing didactic, simplified examples, we illustrate how this underlying physical structure allows for a direct mapping of EM problems onto Quadratic Unconstrained Binary Optimization (QUBO) models and equivalent Ising Hamiltonians. All numerical experiments are conducted using Simulated Annealing as a classical proxy, since the primary contribution of this work is the QUBO formulation itself rather than its execution on quantum hardware. Our results suggest that a broad class of EM problems—including array thinning, reconfigurable intelligent surface optimization, subarray partitioning, and electromagnetic inverse scattering—are suitable candidates for optimization using near-future quantum annealing architectures, once hardware connectivity and noise floors reach the required specifications. Full article

The rapid integration of photovoltaic (PV) generation into active distribution networks (ADNs) creates a fundamental tension between maintaining tight voltage regulation and accommodating high distributed energy resource (DER) penetration levels. Conventional voltage control methods such as the droop control operate locally without coordination, while centralized optimal power flow requires full network observability and reliable real-time communication. Multi-agent deep reinforcement learning (MADRL) methods provide adaptive coordination but suffer from long training times and algorithmic complexity that prevent direct deployment on embedded inverter hardware. This paper proposes the Optimal Historical Selection and Forecasting (OHSF) scheme: a physics-informed long short-term memory (LSTM) network combined with an online sensitivity-based correction loop for medium-voltage ADNs. A composite loss function incorporating data-driven regression, an inter-PV voltage sensitivity penalty, and an inverter capability constraint produces reactive power setpoints that are inherently aware of physical limits, while the correction loop refines the predictions using real-time AC power flow feedback. The OHSF scheme supports a centralized full-network mode and a decentralized fallback mode in which the trained weights run locally on each inverter. Simulations under worst-case PV placement and network reconfiguration on the modified IEEE 33-bus and 69-bus test systems achieve an average voltage deviation across all PV buses of $0.701\%$ and $0.601\%$ at $172\%$ DER penetration on the 33-bus system, and $0.804\%$ and $0.806\%$ at $242\%$ DER penetration on the 69-bus system, while training 32 to 49 times faster than state-of-the-art MADRL methods. Full article

With the rapid deployment of deep neural networks (DNNs) on edge devices, traditional hardware accelerators face significant challenges in terms of data security, computational redundancy caused by sparsity, and uneven utilization of on-chip resources. This paper proposes SaE-FPGA, a secure and efficient DNN accelerator designed specifically for edge FPGA platforms. The architecture introduces three core innovations: (1) Hash-Bypass Processing Unit (HBPU): Integrating a high-speed SHA-256 hardware engine with a hash-sparse bitmap mechanism, it enables real-time data integrity verification within a single clock cycle while skipping computations for redundant zero-value data. (2) Flexible Mixed-Precision Processing Element (FMP): By reconfiguring idle BRAM and LUT resources into an active lookup table multiplication engine, it overcomes the physical bit-width limitations of DSP blocks and supports INT8/INT6/INT4 mixed-precision multiplication. (3) Multi-mode Reconfigurable Streaming Frame (MRSF): A sparse-aware, elastic load balancing and data routing mechanism designed to mask long memory access latencies and ensure high hardware resource utilization. Experimental results on the Zynq 7045 platform demonstrate that SaE-FPGA reduces redundant computations by 23.2% while maintaining high precision and minimizing precision loss. The system effectively mitigates the risk of physical tampering. When tested on ResNet-50, it achieved a 27.2% improvement in energy efficiency and a 2.97× speedup compared to DSP-based FPGA solutions. Furthermore, by fully exploiting the hybrid BRAM-LUT and DSP configuration, the proposed accelerator achieves a remarkable peak throughput of 782.4 GOPS. Full article

The transition toward environmentally sustainable 6G networks requires mitigating the high-power consumption of traditional active base stations and relay nodes currently used to overcome signal path loss. This paper introduces Reconfigurable Intelligent Surfaces (RIS) as a paradigm-shifting, inherently passive alternative that alters the wireless propagation environment without requiring power-intensive radio frequency (RF) chains. Rather than focusing solely on spectral efficiency, this research aims to maximize Energy Efficiency (EE) to achieve a critical equilibrium between network performance and power consumption. MATLAB-based analytical models demonstrate that received signal power scales quadratically with the number of reflecting elements via constructive interference. Furthermore, systematic evaluations reveal that a 64-element RIS panel imposes a negligible hardware load consuming merely 0.005 Watts per element, offering a highly sustainable alternative to the massive transmit power (up to 40 dBm) frequently required by unassisted networks in noisy environments. By defining a mathematical “Green Operating Point,” this study demonstrates that integrating lightweight RIS panels significantly enhances Signal-to-Noise Ratio (SNR) and data rates, steering next-generation telecommunications toward highly sustainable, low-power operations. Full article

With the rapid development of software-defined radio (SDR) technology, a digital, software-reconfigurable, and flexible solution is provided for microwave radiometers, particularly suitable for atmospheric water vapor and oxygen detection with wideband, multi-channel requirements, significantly improving system efficiency. Meanwhile, digitization helps improve channel consistency and address nonlinearity issues, while the digital zero-balancing mechanism implemented through adaptive integration is more suitable for digital platforms. This paper proposes a digital Dicke-type radiometer system based on an SDR platform, using Xilinx RFSoC XCZU47DR (AMD, San Jose, CA, USA) as the core hardware to achieve single-chip integration of RF signal sampling, digital local oscillator generation, and signal processing. The system implements a 46-channel channelized receiver (23 channels each for K-band and V-band) on an FPGA using a polyphase filter bank. The prototype filters achieve 70 dB stopband attenuation and 0.5 dB passband ripple, with each polyphase branch requiring only 25 coefficients, significantly reducing hardware resource consumption. An adaptive integration method is proposed, where an adaptive switch controller dynamically adjusts the hot source injection time ratio by calculating the power difference between adjacent integration periods, enabling the Dicke zero-balancing mechanism to operate entirely in the digital domain. Furthermore, a complete hardware transfer model is established for three signal branches (antenna, hot source, and matched load), and full-chain calibration of all 46 channels is performed using a liquid nitrogen cold source, with calibration reliability verified through blackbody measurements. Experimental results demonstrate brightness temperature consistency better than 0.7 K, with a sensitivity of less than 0.15 K for the K-band and less than 0.21 K for the V-band at 1 s integration time. Full article

To address the loss of closed-loop nozzle control caused by failures in the nozzle throat angle sensor or the nozzle oil separator valve displacement sensor, a fault-tolerant control method for the aeroengine nozzle actuator based on dynamic control loop reconfiguration is proposed. When either sensor fails, the control structure is reconfigured by removing the corresponding servo loop that can no longer form a closed loop, thereby preserving the remaining effective control loops and maintaining nozzle controllability. The proposed method is validated through full-digital simulation, hardware-in-the-loop simulation, and bench testing. The results show that the method ensures the stable operation of the digital control system over the representative operating conditions across the flight envelope and maintains satisfactory steady-state and dynamic performance under sensor fault conditions. The steady-state fluctuations before and after faults remain comparable. Although transient overshoot and droop increase after fault occurrence, the deterioration is limited: the fan speed overshoot and droop remain within 3% and 4%, respectively, while those of the compressor speed remain within 1% and 3%, respectively. Overall, the proposed method mitigates post-fault performance degradation and improves the fault tolerance of the nozzle control system. These results show that the method provides a feasible technical approach for enhancing the reliability of aeroengine digital control systems. Full article

Today, access control systems are used in almost every institution and building. This is because they are an effective solution that provides a high level of security. There are many commercially available systems that provide security-related access features for buildings, including biometric options. Most use a centralized architecture, where each building can be remotely controlled via an Internet connection. This paper presents a completely different system from those on the market, a decentralized system with clone-detection and data-integrity verification mechanisms that allows access to buildings. The overall architecture includes hardware encoding of the access system’s location, and access is granted based on information written to the RFID card by the card-issuing center. This allows the system to be easily reconfigured at the hardware level prior to installation in the access area. The proposed system uses a confidential RFID card data integrity algorithm that uses the card data and immutable UID to determine a checksum in order to validate the RFID card data. As a result, any unwanted modification of at least one bit invalidates the card and blocks access to the building. The system was implemented, validated, and extensively tested over a one-year period with no reported operational issues. Full article

Precise 3D positioning in GPS-denied environments is a critical enabler of autonomous robotics, industrial automation, and smart logistics within the emerging cyber-physical landscape. This paper presents a distributed and reconfigurable architecture designed to benchmark and provide unified multimodal indoor localization for mobile edge nodes. Unlike rigid commercial solutions, our architecture employs a distributed, reconfigurable framework that allows the rapid interchange of Absolute Localization Methods (UWB, External RGB-D Vision) and Relative Localization Methods (Inertial Odometry, Visual Odometry). We evaluate these modalities individually and in hybrid configurations using a custom low-cost mobile edge node. Experimental results in a controlled environment demonstrate that while all-optical systems offer high precision, a cost-effective fusion of Ultra-Wideband (UWB) and Inertial Measurement Unit (IMU) data provides a robust balance of accuracy and reliability. Conversely, we identify significant limitations in monocular visual odometry within feature-poor indoor spaces. The developed platform serves as a reproducible foundation for researchers to prototype hybrid localization algorithms and assess the trade-offs between hardware cost and operational accuracy within complex cyber-physical ecosystems. Full article

Lightweight Unmanned Aerial Vehicles (UAVs) have limited space, low payload capacity, and constrained power supply capabilities. Therefore, their payloads are constrained by size, weight, and power (SWaP). Thus, designing edge-side signal processing architectures for the payloads of UAVs faces severe challenges. Traditional ASIC design based on manual optimization struggles to meet the demands of low latency and low resource occupancy in edge-side applications. To address this challenge, this paper proposes a signal processing hardware accelerator architecture design framework with algorithm-hardware co-design. The framework employs a cross-level dataflow graph representation to formally capture task characteristics. Reconfigurable dataflow templates and reusable operator IP components are systematically constructed based on this representation. Through multi-objective design space exploration, the framework achieves Pareto-optimal mapping from algorithmic specifications to hardware implementations. Finally, automatic generation of top-level hardware descriptions enables rapid FPGA-based prototyping and functional validation. Taking synthetic aperture radar (SAR) imaging as a study example, compared with non-reconfigurable architectures, this scheme reduces the equivalent gate count by 51.4% without increasing processing latency. Compared with a conventional reconfigurable dataflow architecture, the design improves energy efficiency from 12.8 MS/J to 16.0 MS/J, representing a 25.4% enhancement, while also scaling the supported data processing size by a factor of 4×. It provides a high-performance and scalable hardware acceleration solution for lightweight edge-side computing platforms. Full article