Search Results (13)

Photoplethysmography (PPG) is a widely adopted optical technique for cardiovascular monitoring, but its accuracy is often compromised by skin pigmentation, which attenuates the signal in individuals with darker skin tones. This research addresses the challenge of skin pigmentation by developing a PPG sensor system with a novel gain calibration strategy. We present a hardware prototype integrating a programmable gain amplifier (PGA), specifically the OPA3S328 operational amplifier, controlled by a microcontroller. The system performs a one-time gain adjustment at initialization based on the user’s skin tone, which is quantified using RGB image analysis. This “set-and-hold” approach normalizes the signal amplitude across various skin tones while effectively preserving the native morphology of the PPG waveform, which is essential for advanced cardiovascular diagnostics. Experimental validation with over 70 human volunteers demonstrated the PGA’s ability to apply calibrated gain levels, derived from a first-degree polynomial relationship between skin pigmentation and red light absorption. This approach significantly improved signal consistency across different skin tones. The findings highlight the efficacy of pre-measurement gain correction for achieving reliable PPG sensing in diverse populations and lay the groundwork for future optimization of PPG sensor designs to improve reliability in wearable health monitoring devices. Full article

This paper presents a low-power, fully differential, programmable gain amplifier (PGA) for ultrasound receiver analog front-ends (AFE). It consists of a programmable attenuator implemented by a capacitive voltage divider and a closed-loop amplifier based on a differential difference amplifier (DDA). A suitable sizing strategy provides orthogonal control over gain and bandwidth. The PGA was designed using a standard 180 nm CMOS process. The gain value can be set between −18 dB and +20 dB in 2 dB steps; the bandwidth can be programmed independently of gain, to values from 5 MHz to 20 MHz, in 5 MHz steps; it draws 600 µA from a 1.8 V supply line. It achieves a differential output swing of 0.8 V peak-to-peak differential with no more than 1.7% total harmonic distortion (THD) and an input-referred noise density of 22 nV/√Hz at 10 MHz, measured at the gain of 20 dB. The PGA exhibits high input impedance and low output resistance for easy integration within the AFE signal chain. The digitally controlled gain and bandwidth make this PGA suitable for ultrasound imaging applications requiring precise time gain compensation and adjustable frequency response and/or additional anti-aliasing filtering. Full article

A programmable gain amplifier (PGA) is commonly used to optimize the input dynamic range of high-performance systems such as headphones and biomedical sensors. But PGA is rather sensitive to electromagnetic interference (EMI), which limits the precision of these systems. Many capacitor-less low-dropout regulator (LDO) schemes with high power supply rejection have been proposed to act as the independent power supply for PGA, which consumes additional power and area. This paper proposed a PGA with a high power supply rejection ratio (PSRR) and low power consumption, which serves as the analog front-end amplifier in the 20-bit sigma-delta ADC. The PGA is a two-stage amplifier with hybrid compensation. The first stage is the recycling folded cascode amplifier with the gain-boost technique, while the second stage is the class-AB output stage. The PGA was implemented in the 0.18 μm CMOS technology and achieved a 9.44 MHz unity-gain bandwidth (UGBW) and a 57.8° phase margin when driving the capacitor of 5.9 pF. An optimum figure-of-merit (FoM) value of 905.67 has been achieved with the proposed PGA. As the front-end amplifier of a high-precision ADC, it delivers a DC gain of 162.1 dB, the equivalent input noise voltage of 301.6 nV and an offset voltage of 1.61 μV. Within the frequency range below 60 MHz, the measured PSRR of ADC is below −70 dB with an effective number of bits (ENOB), namely 20 bits. Full article

This paper presents a 35 nV/√Hz analog front-end (AFE) circuitdesigned in the UMC 40 nm CMOS technology for the acquisition of biopotential signal. The proposed AFE consists of a capacitive-coupled instrumentation amplifier (CCIA) and a combination of a programmable gain amplifier (PGA) and a low-pass filter (LPF). The CCIA includes a DC servo loop (DSL) to eliminate electrode DC offset (EDO) and a ripple rejection loop (RRL) with self-zeroing technology to suppress high-frequency ripples caused by the chopper. The PGA-LPF is realized using switched-capacitor circuits, enabling adjustable gain and bandwidth. Implemented in theUMC 40 nm CMOS process, the AFE achieves an input impedance of 368 MΩ at 50 Hz, a common-mode rejection ratio (CMRR) of 111 dB, an equivalent input noise of 1.04 μVrms over the 0.5–1 kHz range, and a maximum elimination of 50 mV electrode DC offset voltage. It occupies an area of only 0.39 × 0.47 mm² on the chip, with a power consumption of 8.96 μW. Full article

Over the past few decades, there has been a significant rise in wearable healthcare technologies that have been playing a major role all over the world in monitoring health, alerting individuals during deviations from their normal health conditions and assisting them to stay fit and healthy. Due to the modern lifestyle and consumption of unhealthy food products, there has been an adverse effect on digestive health standards. In this work, a wearable device with textile electrodes is designed and developed to analyze the digestive conditions, namely, pre-prandial and post-prandial, using Electrogastrogram (EGG) signals. Further, the proposed device is comprised of textile electrodes as a sensor, an Analog-to-Digital Converter (ADC) with a Programmable Gain Amplifier (PGA), a Microcontroller with an inbuilt WirelessFidelity (WiFi) module, and an Internet of Things (IoT) cloud platform. Also, the EGG signals are acquired under two different conditions, namely, pre-prandial and post-prandial conditions, and then the Long Short Term Memory (LSTM) deep learning model is utilized to classify pre-prandial and post-prandial EGG signals to identify the eating habits of normal individuals. Results demonstrate that the proposed approach is capable of classifying the pre-prandial and post-prandial EGG signals, which, in turn, identify the fasting or ingestion state of normal individuals. Full article

This paper presents a novel analog front-end for EMG sensor signal processing powered by 1 V. Such a low supply voltage requires specific design steps enabled using the 28 nm fully depleted silicon on insulator (FDSOI) technology from STMicroelectronics. An active ground circuit is implemented to keep the input common-mode voltage close to the analog ground and to minimize external interference. The amplifier circuit comprises an input instrumentation amplifier (INA) and a programmable-gain amplifier (PGA). Both are implemented in a fully differential topology. The actual performance of the circuit is analyzed using the corner and Monte Carlo analyses that comprise fifth-hundred samples for the global and local process variations. The proposed circuit achieves a high common-mode rejection ratio (CMRR) of 105.5 dB and a high input impedance of 11 G$\mathrm{\Omega }$ with a chip area of 0.09 mm${}^2$. Full article

The design of the analog baseband circuit is based on 55 nm CMOS technology and is integrated in an IEEE 802.11ax concurrent dual band four antenna transceiver. A low-pass filter (LPF) of the receiver was multiplexed with an LPF-transmitter such that the last three stages of the fifth order LPF-receiver were used by the LPF-transmitter, and the first programmable gain amplifier (PGA) of the receiver was partially multiplexed with the PGA-transmitter such that the PGA-receiver and the PGA-transmitter shared the same operational amplifier and input resistance, thereby reducing the power consumption, noise, linearity, and area of intermediate frequency (IF) of the transmitter designed separately. The typical bandwidth of the IF-receiver is 10/20/40 MHz; that of the IF-transmitter is 12/24/50 MHz. The gain range of the IF-receiver and the IF-transmitter is 0.1–65.5 dB and −10.1 to 3.98 dB, respectively. Under the voltage of 1.5 V, the current of the IF-receiver is 3.86 mA. As for the IF-transmitter, the current is 1.78 mA when supply voltage is 1.5 V. The input referred noise (IRN) of the IF-receiver at 10 MHz bandwidth (BW) and 62 dB gain is 14.52 nV/√ Hz, while the IRN of the IF-transmitter at 10 MHz BW and −6 dB gain is 95.16 nV/√ Hz. The suppression ability of the DC offset cancellation circuit is 35.08/80.9/110.1/113 dB. The area of the analog baseband circuit is 0.17 mm². Full article

This paper presents an analog front-end for fine-dust detection systems with a 77-dB-wide dynamic range and a dual-mode ultra-low noise TIA with 142-dBΩ towards the maximum gain. The required high sensitivity of the analog signal conditioning path dictates having a high sensitivity at the front-end while the Input-Referred Noise (IRN) is kept low. Therefore, a TIA with a high sensitivity to detected current bio-signals is provided by a photodiode module. The analog front end is formed by the TIA, a DC-Offset Cancellation (DCOC) circuit, a Single-to-Differential Amplifier (SDA), and two Programmable Gain Amplifiers (PGAs). Gain adjustment is implemented by a coarse-gain-step using selective loads with four different gain values and fine-gain steps by 42 dB dynamic range during 16 fine steps. The settling time of the TIA is compensated using a capacitive compensation which is applied for the last stage. An off-state circuitry is proposed to avoid any off-current leakage. This TIA is designed in a 0.18 µm standard CMOS technology. Post-layout simulations show a high gain operation with a 67 dB dynamic range, input-referred noise, less than 600 fA/√Hz in low frequencies, and less than 27 fA/√Hz at 20 kHz, a minimum detectable current signal of 4 pA, and a 2.71 mW power consumption. After measuring the full path of the analog signal conditioning path, the experimental results of the fabricated chip show a maximum gain of 142 dB for the TIA. The Single-to-Differential Amplifier delivers a differential waveform with a unity gain. The PGA1 and PGA2 show a maximum gain of 6.7 dB and 6.3 dB, respectively. The full-path analog front-end shows a wide dynamic range of up to 77 dB in the measurement results. Full article

Recently, piezoresistive-type (PRT) pressure sensors have been gaining attention in variety of applications due to their simplicity, low cost, miniature size and ruggedness. The electrical behavior of a pressure sensor is highly dependent on the temperature gradient which seriously degrades its reliability and reduces measurement accuracy. In this paper, polynomial-based adaptive digital temperature compensation is presented for automotive piezoresistive pressure sensor applications. The non-linear temperature dependency of a pressure sensor is accurately compensated for by incorporating opposite characteristics of the pressure sensor as a function of temperature. The compensation polynomial is fully implemented in a digital system and a scaling technique is introduced to enhance its accuracy. The resource sharing technique is adopted for minimizing controller area and power consumption. The negative temperature coefficient (NTC) instead of proportional to absolute temperature (PTAT) or complementary to absolute temperature (CTAT) is used as the temperature-sensing element since it offers the best temperature characteristics for grade 0 ambient temperature operating range according to the automotive electronics council (AEC) test qualification ACE-Q100. The shared structure approach uses an existing analog signal conditioning path, composed of a programmable gain amplifier (PGA) and an analog-to-digital converter (ADC). For improving the accuracy over wide range of temperature, a high-resolution sigma-delta ADC is integrated. The measured temperature compensation accuracy is within ±0.068% with full scale when temperature varies from −40 °C to 150 °C according to ACE-Q100. It takes 37 µs to compute the temperature compensation with a clock frequency of 10 MHz. The proposed technique is integrated in an automotive pressure sensor signal conditioning chip using a 180 nm complementary metal–oxide–semiconductor (CMOS) process. Full article

This paper presents a low-noise reconfigurable sensor readout circuit with a multimodal sensing chain for voltage/current/resistive/capacitive microsensors such that it can interface with a voltage, current, resistive, or capacitive microsensor, and can be reconfigured for a specific sensor application. The multimodal sensor readout circuit consists of a reconfigurable amplifier, programmable gain amplifier (PGA), low-pass filter (LPF), and analog-to-digital converter (ADC). A chopper stabilization technique was implemented in a multi-path operational amplifier to mitigate 1/f noise and offsets. The 1/f noise and offsets were up-converted by a chopper circuit and caused an output ripple. An AC-coupled ripple rejection loop (RRL) was implemented to reduce the output ripple caused by the chopper. When the amplifier was operated in the discrete-time mode, for example, the capacitive-sensing mode, a correlated double sampling (CDS) scheme reduced the low-frequency noise. The readout circuit was designed to use the 0.18-µm complementary metal-oxide-semiconductor (CMOS) process with an active area of 9.61 mm². The total power consumption was 2.552 mW with a 1.8-V supply voltage. The measured input referred noise in the voltage-sensing mode was 5.25 µV_rms from 1 Hz to 200 Hz. Full article

CMOS analog baseband circuits including a low-pass filter (LPF) and a programmable gain amplifier (PGA) are designed and implemented for the fifth-generation (5G) mobile communication. The super source follower topology is adopted to achieve a wideband LPF with good linearity, while the constant current density gain control technique is used to implement gain cells of the PGA. The circuits are integrated as an analog baseband for a 5G transmitter (TX) and fabricated using TSMC 90-nm CMOS technology. The analog baseband exhibits the bandwidth from 1.03 to 1.05 GHz when the voltage gain is varied from −18.9 dB to 3.8 dB in 1-dB steps. The gain step errors are within −0.7 dB to +0.9 dB. In the highest gain mode, the analog baseband achieves the IP_1dB of −10 dBv and the IIP3 of −0.2 dBv. Over the band of interest, the NF of the analog baseband is 24.4–40.0 dB. Full article

This study proposes a front-end readout circuit as an encoder chip for magneto-resistance (MR) linear scales. A typical MR sensor consists of two major parts: one is its base structure, also called the magnetic scale, which is embedded with multiple grid MR electrodes, while another is an “MR reader” stage with magnets inside and moving on the rails of the base. As the stage is in motion, the magnetic interaction between the moving stage and the base causes the variation of the magneto-resistances of the grid electrodes. In this study, a front-end readout IC chip is successfully designed and realized to acquire temporally-varying resistances in electrical signals as the stage is in motions. The acquired signals are in fact sinusoids and co-sinusoids, which are further deciphered by the front-end readout circuit via newly-designed programmable gain amplifiers (PGAs) and analog-to-digital converters (ADCs). The PGA is particularly designed to amplify the signals up to full dynamic ranges and up to 1 MHz. A 12-bit successive approximation register (SAR) ADC for analog-to-digital conversion is designed with linearity performance of ±1 in the least significant bit (LSB) over the input range of 0.5–2.5 V from peak to peak. The chip was fabricated by the Taiwan Semiconductor Manufacturing Company (TSMC) 0.35-micron complementary metal oxide semiconductor (CMOS) technology for verification with a chip size of 6.61 mm², while the power consumption is 56 mW from a 5-V power supply. The measured integral non-linearity (INL) is −0.79–0.95 LSB while the differential non-linearity (DNL) is −0.68–0.72 LSB. The effective number of bits (ENOB) of the designed ADC is validated as 10.86 for converting the input analog signal to digital counterparts. Experimental validation was conducted. A digital decoder is orchestrated to decipher the harmonic outputs from the ADC via interpolation to the position of the moving stage. It was found that the displacement measurement error is within ±15 µm for a measuring range of 10 mm. Full article

DC-offset and DC-suppression are key parameters in bioelectric amplifiers. However, specific DC analyses are not often explained. Several factors influence the DC-budget: the programmable gain, the programmable cut-off frequencies for high pass filtering and, the low cut-off values and the capacitor blocking issues involved. A new intermediate stage is proposed to address the DC problem entirely. Two implementations were tested. The stage is composed of a programmable gain amplifier (PGA) with DC-rejection and low output offset. Cut-off frequencies are selectable and values from 0.016 to 31.83 Hz were tested, and the capacitor deblocking is embedded in the design. Hence, this PGA delivers most of the required gain with constant low output offset, notwithstanding the gain or cut-off frequency selected. Full article