Search Results (23)

Trajectory prediction is a critical component of autonomous driving systems, enabling vehicles to anticipate future motion behaviors and perform safe decision-making in dynamic traffic environments. While recent trajectory forecasting methods achieve state-of-the-art prediction accuracy, many operate as black-box systems and are evaluated primarily on high-end computing platforms, limiting their interpretability and practical deployment feasibility in resource-constrained autonomous driving systems. To address these limitations, this work proposes an interpretable and edge-deployable spatio-temporal trajectory prediction framework for autonomous driving. The proposed architecture integrates a Temporal Convolutional Network with Multi-Head Self-Attention (TCN–MHSA) in ActorNet for selective temporal modeling, a Lane Graph Attention Network (LaneGAT) for structured spatial reasoning, and a multi-stage FusionNet for actor–lane interaction. To improve model interpretability, a comprehensive Explainable AI (XAI) evaluation framework is introduced, including temporal sensitivity analysis, interaction-aware perturbation studies, spatial influence analysis, and gradient-based feature attribution methods. These analyses provide insights into how the model captures temporal motion dependencies, neighboring vehicle interactions, and environmental context during trajectory prediction. To improve the robustness of the interpretability analysis, temporal sensitivity was additionally evaluated over 100 validation scenes, demonstrating that recent observations consistently exert the greatest influence on trajectory prediction, while neighboring interaction effects gradually diminish with increasing spatial separation. Furthermore, practical real-world deployment feasibility is investigated on the NVIDIA Jetson Xavier NX platform using edge-aware optimization strategies, including mixed-precision inference and graph-complexity reduction techniques for efficient resource-constrained inference, achieving 125.74 ms latency at 12.86 W. Additional edge deployment comparisons with HiVT and SIMPL approaches under identical hardware conditions demonstrate that the proposed framework provides a more favorable balance between computational efficiency and embedded deployment performance. Experimental evaluation on the Argoverse 1 dataset demonstrates a minimum Average Displacement Error (minADE) of 0.90 m, a minimum Final Displacement Error (minFDE) of 1.50 m, a Miss Rate (MR) of 0.19, and DAC = 0.95, while establishing an accuracy–deployability operating point under embedded hardware constraints with low power consumption and practical inference throughput. Full article

Laser frequency stabilization underpins precision metrology, optical atomic clocks, quantum optics, and laser spectroscopy. In recent years, field-programmable gate arrays (FPGAs) have become attractive for this task because signal generation, phase-sensitive detection, digital filtering, feedback control, lock monitoring, and automatic re-locking can be integrated on compact and reconfigurable platforms. This review examines recent progress in FPGA-based laser frequency stabilization from four linked perspectives: stabilization principles, digital implementation, system architecture, and intelligent control. We first summarize representative error-signal generation methods, including Pound–Drever–Hall locking, saturation absorption spectroscopy, frequency modulation spectroscopy, and modulation transfer spectroscopy. We then discuss the FPGA functions that determine practical performance, such as data acquisition, direct digital synthesis, digital demodulation, proportional-integral-derivative (PID)/infinite impulse response (IIR) filtering, latency management, and lock-state monitoring. Mixed-signal, all-digital, distributed, and machine-learning-assisted systems are compared to show how bandwidth, latency, stability, integration, cost, and automation are balanced in different designs. This review closes by identifying remaining challenges in analog-to-digital converter/digital-to-analog converter (ADC/DAC) resolution, converter noise, loop latency, actuator bandwidth, long-term robustness, and algorithm portability, and by outlining future directions toward low-latency, software-defined, and intelligent stabilization platforms. Full article

To address the issues of high customization, long development cycles, and excessive power/volume in radio frequency (RF) transceiver modules for Synthetic Aperture Radar (SAR) and radar systems, this paper presents an ultra-compact universal RF transceiver module design based on a full application-specific integrated circuit (ASIC) architecture. Centered on a wideband RF System-on-chip (SoC) and a reconfigurable digital SoC, the module integrates the complete RF transceiver chain—including filtering, amplification, mixing, Analog-to-Digital/Digital-to-Analog Converter (ADC/DAC) conversion, digital preprocessing, and high-speed data transmission. Test results demonstrate that the 8-channel module achieves a 53.1% area reduction and 55.1% lower power consumption (only 40.9 W) compared with conventional architectures, while all key RF specifications meet system requirements. The proposed solution improves upon existing limitations in high integration, low power, and generality, offering a low-cost, rapid-development technical route for transceiver modules in radar and communication applications. Full article

Beyond code generation, large language models (LLMs) are increasingly explored in software architectural tasks. However, it remains unclear to what extent LLMs can apply explicitly requested architectural patterns when provided with user-defined requirements. In this paper, we empirically evaluate the ability of multiple LLMs to generate specific architectural styles under controlled conditions. Models are prompted with specific requirements expressed in different ways and are instructed to generate architectures in four typical styles using the same single prompt and execution strategy. The authors assess the generated architectures with respect to specific evaluation criteria. The results show that, while LLMs can correctly apply simpler architectural patterns, performance decreases as architectural complexity and problem size increase. Model size and requirement representation appear to influence pattern adherence, whereas retrieval-augmented generation (RAG) produces mixed effects. The findings contribute empirical evidence regarding prompting strategies, requirement representations, RAG configurations, and diagram-as-code (DaC) representations for LLM-generated software architectures. The study also introduces a reusable experimental workflow intended to support future benchmarking and comparative evaluation in software architecture generation tasks. Full article

Rootstock strongly influences citrus tree performance, but information remains limited for some regionally important cultivars. ‘IAPAR 73’, an early-season sweet orange commonly grown in Paraná, Brazil, has not been previously evaluated for rootstock responses. This study assessed the long-term effects of nine rootstocks, including ‘Rangpur’ lime, ‘Swingle’ citrumelo, ‘Volkamer’ lemon, ‘Caipira DAC’ and ‘Trifoliate’ oranges, ‘Cleopatra’ and ‘Sunki’ mandarins, ‘Carrizo’ and ‘Fepagro C-13’ citranges, on vegetative growth, yield, production stability, and fruit quality under Brazilian subtropical conditions. Tree growth was monitored annually for 10 years (2003–2013) and analyzed at establishment (5 years) and full production (10 years) phases of the orchard. Yield and fruit quality were evaluated across multiple harvests, and total soluble solids (TSS) stability was quantified using the coefficient of variation. Rootstock effects were analyzed using linear mixed-effects models in a randomized complete block design, considering rootstock and year as fixed effects and blocks as random effects. Rootstock significantly influenced all evaluated traits. ‘Carrizo’, ‘Cleopatra’, ‘Sunki’, and ‘Caipira DAC’ induced vigorous canopy growth and higher cumulative yields to the scion, while ‘Volkamer’ showed high yield efficiency and production stability. ‘Swingle’ and ‘Trifoliate’ enhanced TSS, TSS/TA ratios, and juice quality stability but induced lower vigor and yield, similar to ‘Rangpur’. This study provides the first evidence-based guidance for ‘IAPAR 73’ production, demonstrating that rootstock diversification can maximize productivity, stability, and sustainability in citrus orchards. Full article

Recycling spent CO₂ absorbents generated from direct air capture (DAC) processes is important for improving the sustainability of carbon capture technologies. This study investigates the feasibility of using a spent alkaline CO₂ absorbent as a partial replacement of mixing water in cementitious materials and evaluates its effects on microstructure, strength, and durability. Mortar and concrete mixtures were prepared with replacement ratios of 0–40%. Microstructural and phase evolution were analyzed using scanning electron microscopy, X-ray diffraction, and thermogravimetric analysis, while mechanical performance was assessed through compressive and flexural strength tests. Durability was evaluated by freezing–thawing resistance, chemical resistance in acidic environments, and accelerated carbonation tests. The results show that low replacement ratios (10–20%) improve early-age strength due to CaCO₃-induced micro-filling and nucleation effects, while maintaining comparable long-term strength to the reference mixture. In contrast, higher replacement ratios (≥30%) cause excessive carbonation, C–S–H decalcification, increased micro-porosity, and strength reduction. Overall, spent CO₂ absorbents can be effectively recycled in cementitious materials within a 10–20% replacement range. Full article

We present a mixed-signal front-end ASIC designed for compact Silicon Photomultiplier (SiPM) sensor interfaces, implemented in the AMS 0.35 µm CMOS technology. The chip integrates two independent analog channels, each composed of five custom second-generation current conveyors (CCII⁺), a fast zero-crossing discriminator, and a peak-and-hold stage based on a tailored operational amplifier. The CCII⁺ and discriminator blocks were designed in-house, based on literature designs and adapted to the technology to ensure low input impedance and fast current-mode signal propagation. This architecture enables precise detection of small signals with reduced pile-up, important for time-resolved photon detection. Bias and threshold control are provided by programmable current mirrors and SPI-configurable DACs, including a 10-bit current-mode DAC based on a current-splitting structure with approximately 200 nA resolution. A custom SiPM behavioral model was developed in the Cadence environment to support design and simulation, reproducing realistic pulse shapes and recovery dynamics for timing applications. Circuit-level simulations confirm correct analog functionality and stable operation across the intended dynamic range, with a per-channel consumption of about 5.9 mA at 3.3 V (19.5 mW), reflecting a tradeoff between speed and robustness. The system is compatible with external timing architectures, while internal CCII⁺ stages ensure low-impedance current reception, fast discrimination, and accurate current-to-voltage conversion for peak detection. Full article

This paper presents a novel methodology for the design and calibration of ultra-compact digital-to-analog converters (DACs), integrating architectural redundancy and a digital calibration algorithm. The proposed calibration approach generates pre-distortion codes that correct both positive and negative nonlinearity errors, even in designs with severe mismatch or relaxed layout constraints. This enables the use of aggressively scaled devices while maintaining high linearity and spectral fidelity. The algorithm is architecture-agnostic and compatible with resistor-string, current-steering, and hybrid DAC structures. It operates with minimal memory, low latency, and supports both foreground and background calibration modes. The method is validated through simulation and silicon measurement of three 14-bit DAC architectures fabricated in TSMC 180 nm CMOS. Post-calibration results demonstrate linearity within ±0.5–1.2 LSB, ENOB up to 13.8 bits, and significant improvements in SNR, SFDR, and THD. The compact layouts—occupying as little as 0.0169 mm²—highlight the scalability of the proposed method for applications such as analog AI accelerators and high-density mixed-signal SoCs. Full article

This work presents the design and simulation of a time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC) implemented in GlobalFoundries’ 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS process. Motivated by the increasing demand for high-speed electrical links in data center and AI/ML applications, the proposed ADC architecture targets medium-resolution, high-throughput conversion with optimized power and area efficiency. The design leverages asynchronous SAR operation, bootstrapped sampling switches, and a hybrid binary/non-binary capacitive digital-to-analog converter (DAC) to achieve robust performance across process, voltage, and temperature (PVT) variations. System-level modeling using channel operating margin (COM) methodology guided the specification of key circuit blocks, enabling efficient trade-offs between resolution, speed, and power. Post-layout simulations demonstrated effective number of bits (ENOB) performance consistent with system requirements, while Monte Carlo analysis confirmed the statistical yield. The converter achieved competitive figures of merit compared to state-of-the-art designs, as benchmarked against the Murmann ADC survey. This work highlights critical design considerations for scalable mixed-signal architectures in advanced CMOS nodes and lays the foundation for future integration in high-speed SerDes systems. Full article

Background: The fabrication of orthodontic aligners directly via three-dimensional (3D) printing presents potential to increase the efficiency of aligner production relative to traditional workflows; however, several aspects of the 3D printing process might affect the dimensional fidelity of the fabricated appliances. The aim of this study is to measure the forces expressed by a 3D printed aligner made with TC-85 DAC resin (Grapy Inc., Seoul, Republic of Korea) when an expansion movement of the entire upper dental arch is programmed, comparing the measured forces with those obtained by a common thermoformed aligner (Smart Track^®, Align Technology, Santa Clara, CA, USA). Materials and methods: A patient in transitional mixed dentition was selected, with the presence of all the first molars and permanent upper and lower incisors, and the canines and premolars have not started the exchange. From this patient, a virtual set up of the upper arch has been planned with an expansion of 0.2 mm and 0.4 mm per side; 3 mm horizontal rectangular attachments were added to the set up on the vestibular surface of the permanent molars, deciduous premolars, and deciduous canines. On this set up, 10 Smart Track aligners and 10 3D printed aligners with TC-85 DAC resin were produced. The fabricated aligners were mounted on the machinery used for the test (ElectroForce^® Test Bench; TA Instruments, New Castle, DE, USA) by means of specific supports that simulate the upper arch of the patient (divided into two sides: right and left). To simulate the intraoral environment, the measurements were carried out in a thermostatic bath at a temperature of 37 °C. Results: The key results of this paper showed differences between Smart Track^® and TC-85 DAC. In particular, the expanding force exerted by the 0.2 mm per side expanded Smart Track^® aligners was on average +0.2162 N with a D.S. of ±0.0051 N during the 8 h; meanwhile, the force exerted by the 0.2 mm per side expanded TC-85 DAC 3D printed aligners was on average −0.0034 N with a D.S. of ±0.0036 N during the 8 h. The force exerted by the 0.4 mm per side expanded Smart Track^® aligners was on average +0.7159 N with a D.S. of ±0.0543 N during the 8 h; meanwhile, the force exerted by the 0.4 mm per side expanded TC-85 DAC 3D printed aligners was on average +0.0141 N with a D.S. of ±0.004 N during the 8 h. Conclusions: Smart Track^® aligners express a quantitatively measurable force in Newtons during the programmed movements to obtain a posterior expansion of the dental arches; on the contrary, aligners made with TC-85 DAC resin, in light of the results obtained from this study, express forces close to 0 during the realization of the movements programmed to obtain a posterior expansion of the dental arches. Full article

The mitigation of climate change impacts from the automotive sector is important for sustainable development, and for that purpose, synthetic liquid fuel vehicles (SLF-Vs) are being considered as a potential clean option alongside electric vehicles (EVs). However, the energy-intensive production of synthetic liquid fuels (SLFs) requires a thorough life-cycle analysis, as CO₂ emissions vary significantly depending on the power sources and feedstock production technologies. This study evaluates the life-cycle CO₂ emissions of SLF-Vs in Japan through long-term multiple scenarios up to 2050 and compares them with those of gasoline vehicles (GVs), hybrid electric vehicles (HEVs), and battery electric vehicles (BEVs). The results reveal that, in 2020, SLF-Vs’ life-cycle CO₂ emissions were more than 2.9 times higher than those of GVs. By 2050, SLF-Vs’ emissions could only decrease to BEV-like levels if Japan achieves significant decarbonization of its power grid. Even if hydrogen is produced via water electrolysis in Australia, where renewable energy is abundant, and then imported, emissions remain high if Japan’s power grid remains insufficiently decarbonized. This highlights the critical importance of expanding domestic decarbonized power sources, particularly renewable energy, to reduce the life-cycle CO₂ emissions of SLF-Vs in Japan. Full article

Leading-edge analog/mixed-signal LSI designs are still hand-crafted using graphic editors. These graphic editors do not include functionality for parameterized topologies in variable designs. Instead of graphic editors, we have developed the SWA (SoftWare Analog) language, which can describe and display placements and routing for analog/mixed-signal LSI layouts with less or similar labor time. By using SWA, we have developed an R-DAC (resistive digital–analog converter) layout with a parameterized topology and various parameters, such as ~1 Gsps, 4~12-bit (upper segment type + lower R-2R type) R-DAC, and 1~3.3 V logic with 1~3.3 V_pp analog output. Full article

Background and Objectives: The Esophageal Adenocarcinoma Study Group Europe (EACSGE) recently proposed a granular histologic classification of esophageal–esophago-gastric junctional adenocarcinomas (EA-EGJAs) based on the study of naïve surgically resected specimens that, when combined with the pTNM stage, is an efficient indicator of prognosis, molecular events, and response to treatment. In this study, we compared histologic classes of endoscopic biopsies taken before surgical resection with those of the surgical specimen, to evaluate the potential of the EACSGE classification at the initial diagnostic workup. Methods: A total of 106 EA-EGJA cases with available endoscopic biopsies and matched surgical resection specimens were retrieved from five Italian institutions. Histologic classification was performed on all specimens to identify well-differentiated glandular adenocarcinoma (WD-GAC), poorly differentiated glandular adenocarcinoma (PD-GAC), mucinous muconodular carcinoma (MMC), infiltrative mucinous carcinoma (IMC), diffuse desmoplastic carcinoma, diffuse anaplastic carcinoma (DAC), and mixed subtypes. Related risk subgroups (low-risk versus high-risk) were also assessed. The correlations of histologic classes and risk subgroups between diagnostic biopsies and surgical resection specimens were explored with Spearman’s correlation test. Sensitivity, specificity, accuracy, positive predictive value, negative predictive value, true positives, true negatives, false positives, and false negatives were also calculated. Results: A strong positive correlation between biopsies and surgical specimens occurred for both histologic classes (coefficient: 0.75, p < 0.001) and risk subgroups (coefficient: 0.65, p < 0.001). The highest sensitivities and specificities were observed for MMC, IMC, and DAC (100% and 99% for all), followed by WD-GAC (sensitivity 91%, specificity 79%) and PD-GAC (sensitivity 722%, specificity 86%). The low-risk and high-risk groups presented a sensitivity and specificity of 89% and 76% (low-risk) and 76% and 89% (high-risk). Conclusions: The EACSGE histologic classification of EA-EGJAs and associated prognostic subgroups can be reliably assessed on pre-operative diagnostic biopsies. Further studies on larger and more representative cohorts of EA-EGJAs will allow us to validate our findings and confirm if the EA-EGJA biopsy histomorphology and clinical TNM staging will be as efficient as the surgical specimen histomorphology and pTNM in predicting patient prognoses and tailoring personalized therapeutic approaches. Full article

We have developed SWA: SoftWare for Analog design automation. Its commands can describe analog and mixed-signal (AMS) layouts and schematics to replace the graphic editor with a program reflecting the knowledge of design experts. Also, it is able to utilize variables to parameterize schematics and layouts to fulfill design needs. We programmed a 10b 1 GS/s DAC using SWA with 8.3 K lines of code, which is about 1/10 compared with conventional programs. The programmed DAC is configurable with multiple voltages and multiple resolutions from 4 to 12 bits. The DAC schematic and layout generation with DRC and LVS SWA API can be finished in about 1 min. Full article

Successive approximation register (SAR) analog-to-digital converters (ADC) have the advantages of a simple structure, low power consumption and a small area compared with other types of ADCs, and thus, high-performance SAR ADCs have always been a hot research topic in the industry. In this paper, a 12-bit SAR ADC design with calibration using a hybrid RC digital-to-analog converter(RC DAC) structure is proposed to improve the conversion accuracy of the ADC and reduce the circuit area at the same time. The analog supply voltage and reference voltage of the ADC are 3.3 V, and the digital supply voltage is 1.2 V. The ADC adopts a mixed digital–analog design scheme, in which the internal comparator, latch, DAC capacitor array, etc., are analog parts, and the rest of the SAR algorithms and calibration algorithms are all implemented in digital Verilog code, with a conversion accuracy of 0.8 mV and a calibration accuracy of 0.5 LSB. The ADC can be selectively calibrated, and the simulation shows that the accuracy of the calibrated ADC can be guaranteed to be within 2 LSB under a 14 MHz digital clock with a sampling rate of 1 MHz. After simulation at a sampling rate of 1 MHz and an input frequency of 244 Hz sine wave, the effective bit count of the ADC is 9.54 bits and the SFDR is 63.71 dB. The circuit consumes 1.78 mW with a 3.3 V supply voltage. The overall layout core area is 411 $\mathsf{\mu }$m × 517 $\mathsf{\mu }$m. Full article