Search Results (5)

With the evolution of synchrotron light sources to fourth generation (diffraction-limited storage rings), the brilliance is increased by several orders of magnitude compared to third generation facilities. For example, the Swiss Light Source (SLS) has been upgraded to SLS 2.0, promising a horizontal emittance reduced by a factor of 40, and a brilliance up to two orders of magnitude (three at higher energies). A key challenge arising from the increased flux is the heightened accumulated dose in silicon sensors, which leads to a significant increase in radiation damage. This translates into an increase of both noise and dark current, as well as a reduction in the dynamic range for long exposure times, thus affecting the performance of the detector, in particular, for charge-integrating detectors. We have designed sensors with a 4 × 4 mm² pixel array featuring 16 design variations of 25 µm pitch pixels with different implant and metal sizes and tested them bump-bonded to MÖNCH 0.3, a charge integrating hybrid pixel detector readout ASIC. Following a first assessment of the functionality and performance of the different pixel designs, the assembly has been irradiated with X-rays. The variation in the tested parameters was characterized at different accumulated doses up to 100 kGy at the sensor entrance window side. The annealing dynamics at room temperature have also been measured. The results show that the default pixel design is currently not optimal and can benefit from layout changes (reduction in the inter-pixel gap area with full metal coverage of the implant). Further studies on the metal coverage over large implants could be conducted. The layout changes are, however, not sufficient for future full-sized sensors, requiring improved radiation hardness and long-term stability, and additional strategies such as focusing on detector cooling and changes in sensor technologies would be required. Full article

This paper presents ultra high-density spin-orbit torque magnetic random-access memory (SOT-MRAM) for last-level data cache application. Although SOT-MRAM has many appealing attributes of low write energy, nonvolatility, and high reliability, it poses challenges to ultra-high-density memory implementation. Due to using two access transistors per cell, the vertical dimension of SOT-MRAM is >40% longer than that of the spin-transfer torque magnetic random-access memory (STT-MRAM), a single transistor-based design. Moreover, the horizontal dimension cannot be reduced below two metal pitches due to the two vertical metal stacks per cell. This paper proposes an ultra-high-density SOT-MRAM design by reducing the vertical and horizontal dimensions. The proposed SOT-MRAM is designed by a single transistor with a Schottky diode to achieve lesser vertical dimension than the two-transistor-based design of conventional SOT-MRAM. Moreover, the horizontal dimension is also reduced by sharing a vertical metal between two consecutive bit-cells in the same row. The comparison of the proposed designs with the conventional SOT-MRAM reveals a 63% area reduction. Compared with STT-MRAM, the proposed high-density memory design achieves 48% higher integration density, 68% lower write power, 29% lower read power, and 1.9× higher read-disturb margin. Full article

Visible light positioning (VLP) using complementary metal–oxide–semiconductor (CMOS) image sensors is a cost-effective solution to the increasing demand for an indoor positioning system. However, in most of the existing VLP systems with an image sensor, researchers assume that the receiving image sensor is positioned parallel to the indoor floor without any tilting and, thus, have only focused on the high-precision positioning algorithm and ignored the proper light-emitting diode (LED)-ID recognition. To address these limitations, we present, herein, a smartphone CMOS image sensor and visible light-based indoor localization system for a receiver device in a tilted position, and we have applied a machine learning approach for optimized LED-ID detection. For detection of the LED-ID, we generated different features for different LED-IDs and utilize a machine learning method to identify each ID as opposed to using the conventional coding and decoding method. An image processing method was used for the image features extraction and selection. We utilized the rolling shutter mechanism of the smartphone CMOS image sensor in our indoor positioning system. Additionally, to improve the LED-ID detection and positioning accuracy with the tilting of the receiver, we utilized the embedded fusion sensors of the smartphone (e.g., accelerometer, gyroscope, and magnetometer, which can be used to extract the yaw, pitch, and roll angles). The experimental results for the proposed positioning system show that it can provide 2.49, 4.63, 8.46, and 12.20 cm accuracy with angles of 0, 5, 10, and 15°, respectively, within a 2 m × 2 m × 2 m positioning area. Full article

The demand for a high-resolution metal-oxide-semiconductor (CMOS) image sensor has increased in recent years, and pixel size has shrunk below 1.0 μm to allow accumulation of numerous pixels in a limited area. However, shrinking the pixel size lowers the sensitivity and increases crosstalk because the aspect ratio is worsened by maintaining the height of the pixel. This work introduces a high-sensitivity pixel with a quad-WRGB (White, Red, Green, Blue) color filter array (CFA), spatial deep-trench isolation (S-DTI), and a spatial tungsten grid (S-WG). The optical performance of the suggested pixel was analyzed by performing 3D optical simulations at 1.0, 0.9, and 0.8 μm pixel pitches as small-sized pixels. The quad-WRGB CFA is compared with the quad-Bayer CFA, and the S-DTI and S-WG are compared with the conventional DTI and WG. We confirmed an improvement in the sensitivity of the suggested pixel using the quad-WRGB CFA with S-DTI and S-WG to a maximum of 58.2%, 67.0%, and 66.3% for 1.0, 0.9, and 0.8 μm pixels, respectively. Full article

This paper presents a high full well capacity (FWC) CMOS image sensor (CIS) for space applications. The proposed pixel design effectively increases the FWC without inducing overflow of photo-generated charge in a limited pixel area. An MOS capacitor is integrated in a pixel and accumulated charges in a photodiode are transferred to the in-pixel capacitor multiple times depending on the maximum incident light intensity. In addition, the modulation transfer function (MTF) and radiation damage effect on the pixel, which are especially important for space applications, are studied and analyzed through fabrication of the CIS. The CIS was fabricated using a 0.11 μm 1-poly 4-metal CIS process to demonstrate the proposed techniques and pixel design. A measured FWC of 103,448 electrons and MTF improvement of 300% are achieved with 6.5 μm pixel pitch. Full article