Search Results (771)

The conventional von Neumann architecture, constrained by the memory and power walls arising from the separation of storage and computation, faces significant limitations in computational efficiency and energy consumption. To address these challenges, this paper proposes a computing-in-memory (CiM) architecture based on a hybrid 2T-2C/4T-2C ferroelectric random-access memory (FRAM) array. The proposed architecture performs majority-based bitwise computation by simultaneously activating multiple word lines, enabling AND and OR operations in conventional 2T-2C FRAM cells. Selectively embedded 4T-2C FRAM cells further provide in-array inversion, extending the supported functions to NOT and functionally complete Boolean logic. The architecture also supports full-adder operations and stores input operands, intermediate data, and output results within the same FRAM subarray, thereby reducing data movement. Moreover, the architecture provides ADC-free bitwise computing with binary inputs and outputs, reducing peripheral-circuit overhead and power consumption. The internal computation, nevertheless, relies on analog charge sharing and differential sense-amplifier resolution. HSPICE simulations indicate PVT-evaluated sensing stability and computational efficiency under the evaluated conditions. The bit-line voltage difference reaches 337 mV under triple-row activation and 214 mV under quintuple-row activation, with the former being 5.2 times that of the reported DRAM implementation used for comparison. At 3.3 V, process–voltage–temperature (PVT) simulations show that the maximum deviation of ΔV from its mean value remains below 4.62% across the evaluated process corners and temperatures from −40 °C to 125 °C. Simulations of the 8 × 8 FRAM CiM compute-array circuit model yield an energy consumption of 1.94–3.46 pJ/bit and a calculation latency of 0.599–1.167 ns for the supported bitwise operations, corresponding to a 4.86×–5.90× reduction in energy consumption compared with the reported DDR3-based design. The architecture also supports parallel processing and mitigates data loss associated with destructive FRAM readout through an in-array replication mechanism. Finally, an 8 × 8 hybrid FRAM CiM prototype was fabricated in a 180 nm CMOS process as a physical implementation of the proposed hybrid architecture, and its basic array functionality was verified. Full article

Engineering schematics, such as electrical, mechanical, piping and instrumentation diagrams, record how industrial plants are built and operated, but most of them survive only as images or scanned sheets that software cannot read. Digitizing them by hand is slow and error-prone: an expert must find and classify hundreds of symbols, read dense technical text, and work out which label belongs to which component. Progress with learning-based methods has been held back on two fronts at once. There are almost no annotations that connect a text label to its symbol, and the drawings themselves are usually confidential, so even unlabeled sheets rarely reach the public domain. We address this with a system that turns a drawing into a structured, queryable graph: it detects and classifies the graphical components with an object detector, recovers the technical text, and then resolves which label belongs to which component. Our contributions are threefold: (i) the first at-scale dataset of manually annotated text-to-symbol links for industrial schematics; (ii) a complete, deployable digitization system combining tiled detection with sliced inference, off-the-shelf OCR, and a text-to-symbol association stage; and (iii) a rigorous, leakage-free benchmark of association methods. Under an observable-only candidate protocol, we find that on logic circuits association is dominated by geometry: a simple pairwise model reaches about 99% top-1 and a graph neural network matches but does not exceed it, whereas the denser P&IDs still benefit from a geometric rule-based chain. Detection reaches an mAP@50 of 0.995 on logic circuits and about 0.91 across the 107-class P&ID taxonomy. The system produces a partial semantic graph; connecting lines and flow direction are not extracted. Full article

The synthesis of efficient reversible logic circuits is critical for fault-tolerant quantum computing (FTQC). The primary motivation of this work is to overcome the inherent disadvantages of existing synthesis techniques: approximate heuristic methods often miss optimal solutions, while pure exact computational methods suffer from combinatorial explosion on deep circuits. While the strict NCT library (NOT, CNOT, Toffoli) is often preferred due to the high cost of distilling non-Clifford states required for arbitrary gates, standard physical implementations frequently utilize the broader NCV library (NOT, CNOT, V, V-dagger), requiring the decomposition of Toffoli gates into five elementary operations. To bridge this gap, this paper presents a unified, highly scalable methodology for the optimal design of reversible circuits across both libraries. First, a Mixed-Integer Non-Linear Programming (MINLP) formulation, linearized for the high-performance IBM ILOG CPLEX solver, is introduced to automate the exact generation of globally optimal strict NCT topologies. Second, a systematic four-phase optimization framework is proposed to reduce NCV costs. By replacing Toffoli gates with specific NCV decompositions, permuting control lines to match subsequent linear gates, and applying exact local searches via an extended MINLP solver on bounded sliding windows, significant gate cancellations are achieved. Applying this methodology to prominent primitives (MIG, SAYEM, URG, TSG, and MKG), we match global NCT optimality constraints and achieve highly optimized NCV Quantum Costs of 7, 14, and 12 for the MIG, TSG, and MKG gates, respectively, establishing best-known upper bounds that significantly outperform heuristic literature benchmarks. Full article

The rapid growth of cloud and distributed computing systems has increased the complexity of real-time request distribution under dynamic and multi-factor conditions. In such environments, load-balancing decisions must simultaneously consider uncertain and interdependent parameters, including server load, response time, and resource capacity. Fuzzy logic is an effective tool for modeling such uncertainty; however, the expansion of linguistic variables often leads to a rule-explosion problem, which increases computational complexity and reduces the real-time applicability of fuzzy load-balancing systems. This study proposes an explainable multi-objective quantum-inspired fuzzy optimization approach for scalable load balancing in complex computing environments. The proposed model integrates fuzzy inference with a Grover-inspired classical search strategy to optimize the selection of fuzzy rule subsets. The Grover-inspired component is implemented as a classical simulation rather than a gate-based quantum circuit. A multi-objective evaluation function is formulated to jointly assess rule accuracy, coverage, interpretability, and compactness. This formulation enables the model to reduce redundant fuzzy rules while preserving decision transparency and maintaining reliable load distribution performance. The proposed approach is evaluated in a simulated cloud computing environment with heterogeneous servers and dynamic request arrival patterns. Comparative experiments are conducted against classical load-balancing strategies, conventional fuzzy load balancing, and evolutionary fuzzy optimization methods, including GA-FLB and PSO-FLB. The experimental results show that the proposed model reduces the size of the fuzzy rule base while maintaining competitive response time, load distribution quality, SLA compliance, and decision interpretability. These findings indicate that the integration of Grover-inspired classical search mechanisms with fuzzy reasoning provides a promising direction for developing scalable, compact, and explainable load-balancing models for next-generation intelligent computing systems. Full article

Data movement has become a dominant bottleneck in modern artificial intelligence hardware, making in-memory computing a critical direction for energy-efficient and memory-centric architectures. Ferroelectric hafnium oxide provides a distinctive materials platform for this transition because field-driven polarization switching, non-volatility, CMOS compatibility, and nanoscale thickness scalability can be combined within a process-relevant oxide system. This review establishes a device-to-system perspective on HfO₂-based and Hf_0.5Zr_0.5O₂-based ferroelectric memories for in-memory computing. Instead of treating ferroelectric materials, memory devices, circuit primitives, and computing architectures as separate research topics, we examine how their mutual constraints define the achievable efficiency, precision, reliability, and scalability of hafnia-based computing systems. The discussion connects polarization engineering and defect control with charge-domain computation, threshold-state logic, associative search, analog weight representation, neuromorphic plasticity, and sensor-side processing. Particular emphasis is placed on the translation of ferroelectric functionality from individual devices to arrays, macros, and system-level accelerators. We identify variability, fatigue, charge trapping, multilevel-state uncertainty, peripheral overhead, and benchmarking inconsistency as the central barriers that prevent device-level advantages from directly becoming system-level gains. Finally, we outline a cross-layer roadmap in which ferroelectric stack engineering, variability-tolerant arrays, precision-scalable architectures, and SoC-level integration are co-optimized to enable reliable HZO-based memory-centric computing. Full article

In all-Josephson-junction (all-JJ) logic, cell area is determined by the size of Josephson junctions, enabling intrinsically compact layouts. Tunable kinetic inductance offers a route to add circuit reconfigurability, pushing further scaling within the same all-JJ framework. In this work we present a set of basic cells for reconfigurable superconducting “kinemonics” that exploit tunable kinetic inductances of a multilayer nanostructure to realise multiple logic functions within a single compact circuit. We then combine these gates into a universal programmable logic cell consisting of only four reconfigurable gates supplemented by a single tunable kinetic-inductance key and demonstrate that it can realise all sixteen two-input Boolean functions, making it an analogue of a look-up table with in-hardware reconfigurability. We also discuss how the same principle can be used in superconducting neuromorphic circuits, where tunable kinetic inductance controls routing, coincidence detection, inhibition, and delay for soliton-like spikes in neuron-like elements. Full article

The cost and output voltage quality of multilevel inverters are among the most critical design considerations. Consequently, reducing the number of power switches and DC sources while improving output voltage quality plays a crucial role in achieving cost-effective designs. This paper proposes a new multilevel inverter topology capable of generating 17 voltage levels using a single DC source and only 12 power switches. A comprehensive comparison demonstrates the superior cost effectiveness of the proposed topology compared to existing counterparts. Moreover, modulation of reduced-switch multilevel inverters remains a challenge when conventional PWM techniques are employed, as they typically require complex logic circuits to generate appropriate switching patterns. To address this issue, this paper investigates the application of one-dimensional space vector modulation (OD-SVM) to control the proposed multilevel inverter without the need for any additional logic circuits. Simulation and experimental results validate the effectiveness of the proposed inverter topology and the OD-SVM control strategy. Full article

Earth’s rotation produces day and night cycles that are a primary selective pressure driving the evolution of endogenous circadian clocks. Cyanobacteria are the most studied prokaryotic model, and their timekeeping core is a protein oscillator composed of KaiA, KaiB, and KaiC. This oscillator sustains a near-24 h rhythm independently of transcription–translation feedback, challenging the long-standing assumption that prokaryotes merely respond passively to environmental cues. Moreover, it offers unique insights into the evolution and operational logic of circadian clocks. This review summarizes advances in cyanobacterial circadian research. We first analyze the KaiABC oscillator’s molecular basis, including synergistic conformational changes, phosphorylation and dephosphorylation cascades, and temperature compensation, which confer robustness and tunability. We compare oscillator compositions across cyanobacterial lineages, showing evolutionary plasticity. We then outline input and output networks, clarifying how environmental signals reset the oscillator phase and how temporal information is relayed to downstream processes. We further explain how the clock coordinates photosynthesis, nitrogen fixation, respiration, and cell division through predictive regulation, temporal decoupling, and resource prioritization, thereby resolving metabolic conflicts and enhancing fitness under light and dark cycles. This framework provides a theoretical basis for microbial survival strategies in fluctuating environments and offers insights for synthetic biology circuit design. Finally, we discuss open questions, including coupling between the oscillator and the cell cycle, functional divergence among ecotypes, and roles at the community level. Further research on the cyanobacterial clock will help clarify general principles of biological timing and its evolutionary origins. Full article

The transition to a globalized, fabless semiconductor manufacturing model has integrated third-party foundries and external intellectual property (IP) vendors into the integrated circuit (IC) design cycle. While this collaborative system promotes innovation, it also exposes layouts to security threats. Protecting these designs is paramount; however, applying traditional encryption methodologies fundamentally alters the syntactic hierarchy of the industry-standard GDSII stream format, causing electronic design automation (EDA) tools to crash. Furthermore, a full encryption hinders modern system-on-chip (SoC) development, where different teams require access to specific modules of the design, without exposing the entire IP. To resolve this issue between collaborative layout sharing and zero-trust security, this paper presents a software implementing an encryption engine. By applying the NIST-standardized FF1 Format-Preserving Encryption (FPE) algorithm directly to the geometric data, the proposed software obfuscates sensitive spatial coordinates and structural nomenclature while maintaining the native GDSII format. The engine embeds multi-tiered cryptographic access control directly into the layout, utilizing native metadata properties. This framework allows proprietary logic to be securely compartmentalized, ensuring that interacting parties only view the specific structures they possess the clearance to decrypt. Full article

Two-dimensional transition metal dichalcogenides are being studied as channel materials for beyond-silicon electronics because their atomic-scale thickness enables strong electrostatic control. Among these materials, tungsten diselenide (WSe₂) is particularly attractive because it exhibits ambipolar transport. Despite this advantage, practical WSe₂ transistors remain constrained by Fermi-level pinning at metal contacts, contact-dominated carrier injection, and defect-induced variability, making controlled doping a central issue. This review examines doping strategies developed for WSe₂, focusing on methods compatible with atomically thin van der Waals semiconductors. The discussion covers surface charge-transfer doping by molecular adsorbates, Lewis acids, and alkali metals, as well as defect-mediated chemisorption, self-limiting oxide interfacial layers, and in situ vacancy engineering during growth. Particular attention is given to the thermodynamic mechanisms of charge transfer, the distinction between contact-selective and channel-selective doping, and the trade-offs between degenerate and non-degenerate doping. The effects of doping are also discussed, including contact-resistance reduction through Schottky-barrier narrowing, threshold-voltage control, apparent mobility enhancement through impurity screening and defect passivation, and thermal and temporal stability. The review further summarizes how controlled doping has enabled complementary metal-oxide-semiconductor logic circuits and identifies the remaining challenges in air stability, selective-area patterning, scalable synthesis, and low-temperature integration for monolithic three-dimensional electronic devices. Full article

In low-voltage distribution networks, load switching, induction motor start-up, photovoltaic output variations, and short-circuit faults may produce highly overlapping electrical characteristics, which can lead to maloperation or failure to operate in conventional protection. To address this problem, this paper proposes an adaptive protection method integrating physically guided and cost-sensitive learning. First, an incremental topology-constraint deviation and a voltage-current trajectory curvature are constructed based on the fault-superimposed network constraint and the variation characteristics of system equivalent impedance, enabling the discrimination of short-circuit faults from non-fault transient disturbances. Then, a cost-sensitive physically guided extreme gradient boosting (XGBoost) model is developed, in which a fault-current-increment-based weight is introduced into the objective function to enhance the learning capability for weak-fault samples. Furthermore, a temporal-consistency-based protection operation logic is designed using sliding-window confirmation and majority voting to suppress isolated abnormal predictions. Simulation and RTDS-based real-time validation results on a 0.4-kV low-voltage distribution network with distributed photovoltaic generation show that the proposed method improves weak-fault detection sensitivity and reduces maloperation under complex source–load disturbances. The method relies only on local measurements and has potential for deployment in low-voltage intelligent protection terminals. Full article

Soft iontronic devices, which utilize ions as charge carriers and integrate flexibility and stretchability, exhibit diverse carrier species, high biocompatibility, multimodal stimulus responsiveness, and strong resistance to electromagnetic interference. These features make them highly promising for applications in ionic circuits, flexible sensing, implantable systems, and neuromorphic information processing. Among them, soft iontronic diodes have attracted sustained attention over the past two decades as fundamental building blocks of functional circuits. This review systematically summarizes the material types of soft iontronic diodes and their influence on key device performance. It further elucidates the mechanisms underlying ionic rectification and highlights recent advances in logic gate implementation, energy harvesting, flexible sensing, and neuromorphic computing. Finally, we discuss key challenges and future opportunities in this field, aiming to provide design principles and mechanistic insights for the development and application of soft iontronic diodes. Full article

Recent language models exhibit significant logical reasoning abilities, yet the mechanisms supporting deductive inference remain poorly understood. This paper studies small transformer-based language models trained from scratch on multi-step deductive tasks, focusing on the distinction between horizontal reasoning, where intermediate steps are generated autoregressively, and vertical reasoning, where inference unfolds implicitly across layers before the first output token is produced. We analyze two synthetic tasks: logical consequence over chains of symbolic implications and root-to-leaf navigation in binary trees. Mechanistic interpretability reveals that Chain-of-Thought supervision enables models to learn rule-based inference rather than statistical shortcuts. In the horizontal setting, a shallow attention-only model develops interpretable circuits for rule completion, rule chaining, and final decision making, largely implemented through induction-head-like mechanisms. We further introduce a truncated pseudoinverse method to decode the information carried by queries, keys, and values. For vertical reasoning, Chain-of-Thought appears to act less as explicit step-by-step guidance and more as a form of curriculum learning, helping the model acquire increasingly complex reasoning patterns. Without Chain-of-Thought, models tend to memorize or exploit dataset biases. These results provide a low-level account of how transformers can implement deductive reasoning and suggest how Chain-of-Thought may serve different functions in horizontal and vertical reasoning. Full article

Hardware Trojans (HTs) threaten integrated-circuit security in a globalized semiconductor supply chain, yet how the choice of hardware description language—manual Verilog versus compiler-optimized agile languages such as Chisel—affects the synthesis quality of a Trojan-bearing design remains unexplored. This work re-implements AES-T100, the Trust-Hub leakage benchmark that exfiltrates an AES-128 key via an LFSR-driven side channel, faithfully in Chisel. It then compares the resulting netlist against a hand-written Verilog baseline under matched FPGA synthesis and examines dual-use implications. AES-T100 was rebuilt in Chisel 3.5.0 (20-bit LFSR PRNG, 1-to-8-bit key-obfuscation unit, $8\times$ flip-flop leakage circuit), compiled through FIRRTL 1.5.0, and synthesized on a Cyclone IV E FPGA via Quartus Prime 21.1. The FIRRTL-generated netlist achieved 23.8% higher $f_{\max }$ (387.60 vs. 313.19 MHz) and throughput (4.96 vs. 4.01 Gbps) at identical logic-element count (2096 LEs), with only 1.50% Trojan overhead. The gap localizes to the host AES cipher, consistent with FIRRTL optimization passes. A five-seed replication confirms statistical robustness ($t\left(8\right)=11.7$, $p<0.001$, 95% CI: 18.6–27.7%). Causal attribution—compilation flow versus single-author Verilog coding—remains open, requiring pass-ablation experiments. The parametric template supports HT benchmark generation. FIRRTL-level static analysis is proposed as a defensive direction. Full article

This paper presents a novel hybrid protection scheme based on Maximal Overlapped Discrete Wavelet Transform (MODWT) energy and a specialized difference function (DF) to accurately detect low-level inter-turn short-circuit faults in power transformers while maintaining high-selectivity features against transient conditions. Low-level inter-turn short-circuit faults (LIFs) in power transformers start at a low level and gradually spread to other windings. It is crucial to detect the fault in early stages and prevent further damage by disconnecting the faulty transformer immediately. A wavelet transform and difference function-based Transformer Differential Protection (TDP) algorithm is proposed in this paper. A differential protection scheme consists of two stages: feature extraction and fault detection. Maximum Overlapped Discrete Wavelet Transform (MODWT) energy and a difference function are used for feature extraction and an analytical logic is used for fault detection. It is also shown that this combination provides more reliable differential protection scheme than TDP with the wavelet transform only or TDP with a difference function (DF) alone. The method is assessed with experimental datasets collected from a laboratory-based, custom-built transformer which is specifically designed for validating the methods to detect LIFs. The method is evaluated according to a confusion matrix method with accuracy, dependability and sensitivity indices. The proposed TDP method detected all LIF cases, representing less than 2% of total windings. Therefore, the proposed hybrid algorithm represents an innovative step in applied system monitoring by providing a high-precision, software-based solution that enhances the operational reliability and resilience of existing TDP systems without requiring additional hardware. Full article