Search Results (31)

Background: Peripancreatic collections (PPCs) are a frequent and severe complication of acute and chronic pancreatitis, as well as pancreatic surgery, often requiring interventions to treat and prevent infection, gastric obstruction, and other complications. Endoscopic ultrasound (EUS)-guided drainage has emerged as a minimally invasive alternative to surgical and percutaneous approaches, offering reduced morbidity and shorter recovery times. However, the effectiveness of EUS-guided drainage in post-surgical PPCs remains underexplored. Methods: This retrospective, single-center study evaluated the technical and clinical outcomes of EUS-guided drainage in patients with PPCs between October 2021 and December 2024. Patients were categorized as having post-pancreatitis or post-surgical PPCs. Technical success, clinical success, complications, recurrence rates, and the need for reintervention were assessed. Results: A total of 50 patients underwent EUS-guided drainage, including 42 (84%) with post-pancreatitis PPCs and 8 (16%) with post-surgical PPCs. The overall technical success rate was 100%, with clinical success achieved in 96% of cases. Lumen-apposing metal stents (LAMSs) were used in 84% of patients, including 7.1% as a dual-gate salvage strategy after the failure of double-pigtail drainage. The complication rate was 24%, with infection being the most common (16%). The recurrence rate was 25%, with no significant difference between post-pancreatitis and post-surgical cases. Patients with walled-off necrosis had a significantly higher reintervention rate (35%) than those with pseudocysts (18%; p = 0.042). Conclusions: EUS-guided drainage is a highly effective and safe intervention for PPCs, including complex post-surgical cases. The 100% technical success rate reinforces its reliability, even in anatomically altered post-surgical collections. While recurrence rates remain a consideration, EUS-guided drainage offers a minimally invasive alternative to surgery, with comparable outcomes in both post-pancreatitis and post-surgical patients. Future multi-center studies should focus on optimizing treatment strategies and reducing recurrence in high-risk populations. Full article

In this article, thermal investigation methods for electrically insulating and thermally conductive substrate materials will be presented. The investigations were performed in their real-world application environment, i.e., in the form of IGBT (insulated gate bipolar transistor) module substrate plates. First, the overall thermal resistance and thermal structure function of the system in a multivariable parameter space were revealed using CFD (computational fluid dynamics) simulations. Afterwards, thermal transient testing was performed on real samples, with the help of which the thermal resistance values of the modules were determined using the thermal dual interface test method. The presented tests are not intended to determine material parameters, but to rank different substrate materials based on their thermal performance. Full article

Dual-gate metal-oxide-semiconductor transistors have attracted considerable interest due to their high threshold voltage control capability, higher drain current, and the ability to alleviate the impact of carrier surface scattering at the channel/dielectric interface. However, their applications in the monolithic integration of scaled devices encounter challenges stemming from the interaction between the pre-treated channel layer and its covering dielectric. Here, we demonstrate the successful realization of a scaled back-end-of-line (BEOL) compatible dual-gate indium–gallium–zinc oxide (IGZO) transistor with a channel length (L_ch) scaled down to 150 nm and a channel thickness (T_ch) of 4.2 nm. After precisely adjusting the metal ratio to In_0.24Ga_0.58Zn_0.18O and employing O₃ as an oxygen precursor for the deposition of Al₂O₃ as the top-gate dielectric layer, a high maximum current of 1.384 mA was attained under top-gate control, while a high current of 1.956 mA was achieved under bottom-gate control. Additionally, a high current on/off ratio (I_on/off > 10⁹) was achieved for the dual gate. Careful calculations reveal that the field-effective mobility (μ_eff) reaches 11.68 cm²V⁻¹s⁻¹ under top-gate control and 22.46 cm²V⁻¹s⁻¹ under bottom-gate control. We demonstrate excellent dual-gate low-voltage modulation performance, with a high current switch ratio of 3 × 10⁵ at L_ch = 300 nm and 2 × 10⁴ at L_ch = 150 nm achieved by only 1 V modulation voltage, accompanied by a normalized current variation higher than 10⁶. Overall, our devices show the remarkable electrical performance characteristics, highlighting their potential applications in high-performance electronic circuits. Full article

A 4H-silicon carbide (SiC) trench gate metal–oxide–semiconductor field-effect transistor (MOSFET) with dual integrated Schottky barrier diodes (SBDs) was characterized using numerical simulations. The advantage of three-dimensional stacked integration is that it allows the proposed structure to obtain an electric field of below 0.6 MV/cm in the gate oxide and SBD contacts and achieve ~10% lower forward voltage of SBDs than the planar gate SBD-integrated MOSFET (PSI-MOS) and the trench gate structure with three p-type-protecting layers (TPL-MOS). The dual-SBD-integrated MOSFET (DSI-MOS) also highlights the better influences of the more than 70% reduction in the miller charge, as well as the over 50% reduction in switching loss compared to the others. Furthermore, the short-circuit (SC) robustness of the three devices was identified. The DSI-MOS attains the critical energy and the aluminum melting point in a longer SC time interval than the TPL-MOS. The p-shield layers in the DSI-MOS are demonstrated to yield the huge benefit of improving the reliability of the contacts when SC reliability is considered. Full article

Frequency multipliers are essential components in communication systems, and graphene’s exceptional electrical properties make it highly promising for flexible electronics. This paper addresses the technical challenges of multi-frequency multipliers based on graphene field-effect transistors (GFETs) and introduces a novel fabrication method using graphene as the channel material and metals with different work functions as the top gate. By employing Ti and Pd with distinct work functions, we develop a dual-gate GFET device that exhibits stable M-shaped resistance characteristics on a flexible polyethylene naphthalate (PEN) substrate. We demonstrate frequency doubler, tripler, and quadrupler on the flexible substrate. The results show that the GFET-based frequency multiplier offers advantages such as low operating voltage (<1 V), high voltage conversion efficiency (up to 8.4% for tripler and 6% for quadrupler), and high spectral purity (up to 88% for tripler and 76% for quadrupler). The intrinsic maximum operating frequency of the frequency quadrupler reaches 54 GHz. The use of a monolayer graphene channel, dual-metal gate control enabling an M-shaped transfer curve, and flexible characteristics all contribute to its superior performance compared to conventional devices. Full article

In response to the need for deploying the YOLOv4-Tiny model on resource-constrained Field-Programmable Gate Array (FPGA) platforms for rapid inference, this study proposes a general optimization acceleration strategy and method aimed at achieving fast inference for object detection networks. This approach centers on the synergistic effect of several key strategies: a refined resource management strategy that dynamically adjusts FPGA hardware resource allocation based on the network architecture; a dynamic dual-buffering strategy that maximizes the parallelism of data computation and transmission; an interface access latency pre-configuration strategy that effectively improves data throughput; and quantization operations for dynamic bit width tuning of model parameters and cached variables. Experimental results on the ZYNQ7020 platform demonstrate that this accelerator operates at a frequency of 200 MHz, achieving an average computing performance of 36.97 Giga Operations Per Second (GOPS) with an energy efficiency of 8.82 Giga Operations Per Second per Watt (GOPS/W). Testing with a metal surface defect dataset maintains an accuracy of approximately 90% per image, while reducing the inference delay per frame to 185 ms, representing a 52.2% improvement in inference speed. Compared to other FPGA accelerator designs, the accelerator design strategies and methods proposed in this study showcase significant enhancements in average computing performance, energy efficiency, and inference latency. Full article

Silicon carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) are a future trend in traction inverters in electric vehicles (EVs), and their thermal safety is crucial. Temperature-sensitive electrical parameters’ (TSEPs) indirect detection normally requires additional circuits, which can interfere with the system and increase costs, thereby limiting applications. Therefore, there is still a lack of cost-effective and sensorless thermal monitoring techniques. This paper proposes a high-efficiency datasheet-driven method for sensorless estimation utilizing the third-quadrant characteristics of MOSFETs. Without changing the existing hardware, the closure degree of MOS channels is controlled through a dual-gate bias (DGB) strategy to achieve reverse conduction in different patterns with body diodes. This method introduces a MOSFET operating current that TSEPs are equally sensitive to into the two-argument function, improving the complexity and accuracy. A two-stage current pulse is used to decouple the motor effect in various conduction modes, and the TSEP-combined temperature function is built dynamically by substituting the currents. Then, the junction temperature is estimated by the measured bus voltage and current. Its effectiveness was verified through spice model simulation and a test bench with a three-phase inverter. The average relative estimation error of the proposed method is below $7.2\%$ in centigrade. Full article

As a promising candidate for More Moore technology, InGaAs-based n-channel metal-oxide-semiconductor field-effect transistors (nMOSFETs) have attracted growing research interest, especially with InGaAs-on-insulator (InGaAs-OI) configurations aimed at alleviating the short channel effects. Correspondingly, the fabrication of an ultrathin InGaAs body becomes necessary for the full depletion of the channel, while the deteriorated semiconductor–insulator interface-related scattering could severely limit carrier mobility. This work focuses on the exploration of carrier mobility enhancement strategies for 8 nm body-based InGaAs-OI nMOSFETs. With the introduction of a bottom gate bias on the substrate side, the conduction band structure in the channel was modified, relocating the carrier wave function from the InGaAs/Al₂O₃ interface into the body. Resultantly, the channel mobility with an inversion layer carrier concentration of 1 × 10¹³ cm⁻² was increased by 62%, which benefits InGaAs-OI device application in monolithic 3D integration. The influence of the dual-gate bias from front gate and bottom gate on gate stability was also investigated, where it has been unveiled that the introduction of the positive bottom gate bias is also beneficial for gate stability with an alleviated orthogonal electric field. Full article

Background: The electrodes of implantable cardiac devices (ICDs) may cause significant problems in cardiac computed tomography (CT) because they are a source of artifacts that obscure surrounding structures and possible pathology. There are a few million patients currently with ICDs, and some of these patients will require cardiac imaging due to coronary artery disease or problems with ICDs. Modern CT scanners can reduce some of the metal artifacts because of MAR software, but in some vendors, it does not work with ECG gating. Introduced in 2008, dual-energy CT scanners can generate virtual monoenergetic images (VMIs), which are much less susceptible to metal artifacts than standard CT images. Objective: This study aimed to evaluate if dual-energy CT can reduce metal artifacts caused by ICD leads by using VMIs. The second objective was to determine how the angle between the electrode and the plane of imaging affects the severity of the artifacts in three planes of imaging. Methods: A 3D-printed model was constructed to obtain a 0–90-degree field at 5-degree intervals between the electrode and each of the planes: axial, coronal, and sagittal. This electrode was scanned in dual-energy and single-energy protocols. VMIs with an energy of 40–140 keV with 10 keV intervals were reconstructed. The length of the two most extended artifacts originating from the tip of the electrode and 2 cm above it—at the point where the thick metallic defibrillating portion of the electrode begins—was measured. Results: For the sagittal plane, these observations were similar for both points of the ICDs that were used as the reference location. VMIs with an energy over 80 keV produce images with fewer artifacts than similar images obtained in the single-energy scanning mode. Conclusions: Virtual monoenergetic imaging techniques may reduce streak artifacts arising from ICD electrodes and improve the quality of the image. Increasing the angle of the electrode as well as the imaging plane can reduce artifacts. The angle between the electrode and the beam of X-rays can be increased by tilting the gantry of the scanner or lifting the upper body of the patient. Full article

In this study, we propose doping-less feedback field-effect transistors (DLFBFETs). Our DLFBFETs are 5 nm thick intrinsic semiconductor bodies with dual gates. Usually, DLFBFETs are virtually doped through charge plasma phenomena caused by the source, the drain, and the dual-gate electrodes as well as the gate biases. Our DLFBFETs can be fabricated through a simple process of creating contact between a metal and a silicon body without any doping processes. The voltages applied to both gates determine whether the DLFBFETs operate in diode or feedback field-effect transistor (FBFET) modes. In the FBFET mode, our DLFBFETs show good characteristics such as an on/off current ratio of ~10⁴ and steep switching characteristics (~1 mV/decade of current) that result from positive feedback phenomena without dopants. Full article

In this work, a novel enhancement-mode GaN p-MISFET with a buried back gate (BBG) is proposed to improve the gate-to-channel modulation capability of a high drain current. By using the p-GaN/AlN/AlGaN/AlN double heterostructure, the buried 2DEG channel is tailored and connected to the top metal gate, which acts as a local back gate. Benefiting from the dual-gate structure (i.e., top metal gate and 2DEG BBG), the drain current of the p-MISFET is significantly improved from −2.1 (in the conv. device) to −9.1 mA/mm (in the BBG device). Moreover, the dual-gate design also bodes well for the gate to p-channel control; the subthreshold slope (SS) is substantially reduced from 148 to ~60 mV/dec, and such a low SS can be sustained for more than 3 decades. The back gate effect and the inherent hole compensation mechanism of the dual-gate structure are thoroughly studied by TCAD simulation, revealing their profound impact on enhancing the subthreshold and on-state characteristics in the BBG p-MISFET. Furthermore, the decent device performance of the proposed BBG p-MISFET is projected to the complementary logic inverters by mixed-mode simulation, showcasing excellent voltage transfer characteristics (VTCs) and dynamic switching behavior. The proposed BBG p-MISFET is promising for developing GaN-on-Si monolithically integrated complementary logic and power devices for high efficiency and compact GaN power IC. Full article

In this work, a dual interfacial passivation layer (IPL) consisting of TaON/GeON is implemented in GaAs metal-oxide-semiconductor (MOS) capacitors with ZrTaON as a high-k layer to obtain superior interfacial and electrical properties. As compared to the samples with only GeON IPL or no IPL, the sample with the dual IPL of TaON/GeON exhibits the best performance: low interface-state density (1.31 × 10¹² cm⁻² eV⁻¹), small gate leakage current density (1.62 × 10⁻⁵ A cm⁻² at V_fb + 1 V) and large equivalent dielectric constant (18.0). These exceptional results can be attributed to the effective blocking action of the TaON/GeON dual IPL. It efficiently prevents the out-diffusion of Ga/As atoms and the in-diffusion of oxygen, thereby safeguarding the gate stack against degradation. Additionally, the insertion of the thin TaON layer successfully hinders the interdiffusion of Zr/Ge atoms, thus averting any reaction between Zr and Ge. Consequently, the occurrence of defects in the gate stack and at/near the GaAs surface is significantly reduced. Full article

In this study, a capacitorless one-transistor dynamic random-access memory (1T-DRAM), based on polycrystalline silicon (poly-Si) nanotube structure with a grain boundary (GB), is designed and analyzed using technology computer-aided design (TCAD) simulation. In the proposed 1T-DRAM, the 1T-DRAM cell exhibited a sensing margin of 422 μA/μm and a retention time of 213 ms at T = 358 K with a single GB. To investigate the effect of random GBs, it was assumed that the number of GB is seven, and the memory characteristics depending on the location and number of GBs were analyzed. The memory performance rapidly degraded due to Shockley–Read–Hall recombination depending on the location and number of GBs. In the worst case, when the number of GB is 7, the mean of the sensing margin was 194 µA/µm, and the mean of the retention time was 50.4 ms. Compared to a single GB, the mean of the sensing margin and the retention time decreased by 59.7% and 77.4%, respectively. Full article

This paper examines the performance of a Gate-Engineered Gate-All-Around Charge Plasma Nanowire Field Effect Transistor (GAA-DMG-GS-CP NW-FET) and the implementation of a common source (CS) amplifier circuit. The proposed GAA-DMG-GS-CP NW-FET incorporates dual-material gate (DMG) and gate stack (GS) as gate engineering techniques and its analog/RF performance parameters are compared to those of the Gate-All-Around Single-Material Gate Charge Plasma Nanowire Field Effect Transistor (GAA-SMG-CP NW-FET) device. Both Gate-All-Around (GAA) devices are designed using the Silvaco TCAD tool. GAA structures have demonstrated good gate control because the gate holds the channel, which is an inherent advantage for both devices discussed herein. The charge plasma dopingless technique is used, in which the source and drain regions are formed using metal contacts and necessary work functions rather than doping. This dopingless technique eliminates the need for doping, reducing fluctuations caused by random dopants and lowering the device’s thermal budget. Gate engineering techniques such as DMG and GS significantly improved the current characteristics which played a crucial role in obtaining maximum gain for circuit designs. The lookup table (LUT) approach is used in the implementation of the CS amplifier circuit with the proposed device. The transient response of the circuit is analyzed with both the device structures where the gain achieved for the CS amplifier circuit using the proposed GAA-DMG-GS-CP NW-FET is 15.06 dB. The superior performance showcased by the proposed GAA-DMG-GS-CP NW-FET device with analog, RF and circuit analysis proves its strong candidature for future nanoscale and low-power applications. Full article

Metal injection molding (MIM) is a quick manufacturing method that produces elaborate and complex items accurately and repeatably. The success of MIM is highly impacted by green part characteristics. This work characterized the green part of steel produced using MIM from feedstock with a powder/binder ratio of 93:7. Several parameters were used, such as dual gates position, injection temperature of ~150 °C, and injection pressure of ~180 MPa. Analysis using Moldflow revealed that the aformentioned parameters were expected to produce a green part with decent value of confidence to fill. However, particular regions exhibited high pressure drop and low-quality prediction, which may lead to the formation of defects. Scanning electron microscopy, as well as three-dimensional examination using X-ray computed tomography, revealed that only small amounts of pores were formed, and critical defects such as crack, surface wrinkle, and binder separation were absent. Hardness analysis revealed that the green part exhibited decent homogeneity. Therefore, the observed results could be useful to establish guidelines for MIM of steel in order to obtain a high quality green part. Full article