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Keywords = coplanar gate

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12 pages, 3669 KB  
Article
Development of an Extended-Band mTRL Calibration Kit for On-Wafer Characterization of InP-HEMTs up to 1.1 THz
by Rita Younes, Mahmoud Abou Daher, Mohammed Samnouni, Sylvie Lepilliet, Guillaume Ducournau, Nicolas Wichmann and Sylvain Bollaert
Electronics 2025, 14(17), 3472; https://doi.org/10.3390/electronics14173472 - 29 Aug 2025
Viewed by 384
Abstract
In this work, we present a wideband on-wafer characterization technique for InAlAs/InGaAs/InAs InP-based high-electron mobility transistors (HEMTs) using an optimized multiline Thru-Reflect-Line (mTRL) calibration kit. Our goal is to directly extract transition frequency fT and maximum frequency of oscillation fmax values [...] Read more.
In this work, we present a wideband on-wafer characterization technique for InAlAs/InGaAs/InAs InP-based high-electron mobility transistors (HEMTs) using an optimized multiline Thru-Reflect-Line (mTRL) calibration kit. Our goal is to directly extract transition frequency fT and maximum frequency of oscillation fmax values from S-parameters measurements with frequencies up to 1.1 THz and overcome the limitations of the traditional 20 dB/dec extrapolation method using lower-frequency band measurements. Indeed, as the state-of-the-art transistors now exhibit cutoff frequencies exceeding 1 THz, standard low-frequency extrapolation methods become increasingly inaccurate. Full-wave electromagnetic simulations were used to design low-loss coplanar waveguide (CPW) access structures with stable impedance and minimal parasitic effects. These structures were co-fabricated with HEMTs and calibration standards on the same InP substrate. The 2-finger transistor with a 80 nm gate length exhibits a directly measured fT = 320 GHz and fmax = 800 GHz. The technique showed high consistency across six frequency bands and confirms that direct broadband measurement with mTRL improves accuracy. This work highlights the metrological strength of mTRL-based setups for next-generation THz device characterization. Full article
(This article belongs to the Section Electronic Materials, Devices and Applications)
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16 pages, 3251 KB  
Article
Ion Gel-Modulated Low-Temperature Field-Effect Phototransistors with Multispectral Responsivity for Artificial Synapses
by Junjian Zhao, Yufei Zhang, Di Guo and Junyi Zhai
Sensors 2025, 25(9), 2750; https://doi.org/10.3390/s25092750 - 26 Apr 2025
Viewed by 1041
Abstract
We report an ion-gel-gated amorphous indium gallium zinc oxide (a-IGZO) optoelectronic neuromorphic transistors capable of synaptic emulation in both photoelectric dual modes. The ion-gel dielectric in the coplanar-structured transistor, fabricated via ink-jet printing, exhibits excellent double-layer capacitance (>1 μF/cm2) and supports [...] Read more.
We report an ion-gel-gated amorphous indium gallium zinc oxide (a-IGZO) optoelectronic neuromorphic transistors capable of synaptic emulation in both photoelectric dual modes. The ion-gel dielectric in the coplanar-structured transistor, fabricated via ink-jet printing, exhibits excellent double-layer capacitance (>1 μF/cm2) and supports low-voltage operation through lateral gate coupling. The integration of ink-jet printing technology enables scalable and large-area fabrication, highlighting its industrial feasibility. Electrical stimulation-induced artificial synaptic behaviors were successfully demonstrated through ion migration in the gel matrix. Through a simple and controllable oxygen vacancy engineering process involving low-temperature oxygen-free growth and post-annealing process, a sufficient density of stable subgap states was generated in IGZO, extending its responsivity spectrum to the visible-red region and enabling wavelength-discriminative photoresponses to 450/532/638 nm visible light. Notably, the subgap states exhibited unique interaction dynamics with low-energy photons in optically triggered pulse responses. Critical synaptic functionalities—including short-term plasticity (STP), long-term plasticity (LTP), and paired-pulse facilitation (PPF)—were successfully simulated under both optical and electrical stimulations. The device achieves low energy consumption while maintaining compatibility with flexible substrates through low-temperature processing (≤150 °C). This study establishes a scalable platform for multimodal neuromorphic systems utilizing printed iontronic architectures. Full article
(This article belongs to the Section Electronic Sensors)
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13 pages, 2616 KB  
Article
Enhancement of Ion-Sensitive Field-Effect Transistors through Sol-Gel Processed Lead Zirconate Titanate Ferroelectric Film Integration and Coplanar Gate Sensing Paradigm
by Dong-Gyun Mah, Seong-Moo Oh, Jongwan Jung and Won-Ju Cho
Chemosensors 2024, 12(7), 134; https://doi.org/10.3390/chemosensors12070134 - 9 Jul 2024
Cited by 3 | Viewed by 1835
Abstract
To facilitate the utility of field effect transistor (FET)-type sensors, achieving sensitivity enhancement beyond the Nernst limit is crucial. Thus, this study proposed a novel approach for the development of ferroelectric FETs (FeFETs) using lead zirconate titanate (PZT) ferroelectric films integrated with indium–tungsten [...] Read more.
To facilitate the utility of field effect transistor (FET)-type sensors, achieving sensitivity enhancement beyond the Nernst limit is crucial. Thus, this study proposed a novel approach for the development of ferroelectric FETs (FeFETs) using lead zirconate titanate (PZT) ferroelectric films integrated with indium–tungsten oxide (IWO) channels synthesized via a cost-effective sol-gel process. The electrical properties of PZT-IWO FeFET devices were significantly enhanced through the strategic implementation of PZT film treatment by employing intentional annealing procedures. Consequently, key performance metrics, including the transfer curve on/off ratio and subthreshold swings, were improved. Moreover, unprecedented electrical stability was realized by eliminating the hysteresis effect during double sweeps. By leveraging a single-gate configuration as an FeFET transformation element, extended-gate (EG) detection methodologies for pH sensing were explored, thereby introducing a pioneering dimension to sensor architecture. A measurement paradigm inspired by plane gate work was adopted, and the proposed device exhibited significant resistive coupling, consequently surpassing the sensitivity thresholds of conventional ion-sensitive field-effect transistors. This achievement represents a substantial paradigm shift in the landscape of ion-sensing methodologies, surpassing the established Nernst limit (59.14 mV/pH). Furthermore, this study advances FeFET technology and paves the way for the realization of highly sensitive and reliable ion sensing modalities. Full article
(This article belongs to the Collection pH Sensors, Biosensors and Systems)
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10 pages, 859 KB  
Article
Phase-Slip Based SQUID Used as a Photon Switch in Superconducting Quantum Computation Architectures
by Hu Zhao, Xiaoyu Wu, Wenlong Li, Xudong Fang and Tiefu Li
Electronics 2024, 13(12), 2380; https://doi.org/10.3390/electronics13122380 - 18 Jun 2024
Cited by 1 | Viewed by 1565
Abstract
The photon storage time in a superconducting coplanar waveguide (CPW) resonator is contingent on the loaded quality factor, primarily dictated by the input and output capacitance of the resonator. The phase-slip based superconducting quantum interference device (PS-SQUID) comprises two phase-slip (PS) junctions connected [...] Read more.
The photon storage time in a superconducting coplanar waveguide (CPW) resonator is contingent on the loaded quality factor, primarily dictated by the input and output capacitance of the resonator. The phase-slip based superconducting quantum interference device (PS-SQUID) comprises two phase-slip (PS) junctions connected in series with a superconducting island in between. The PS-SQUID can manifest nonlinear capacitance behavior, with the capacitance finetuned by the gate voltage to minimize the impact of magnetic field noise as much as possible. By substituting the coupling capacitance of the CPW resonator with the PS-SQUID, the loaded quality factor of the resonator can be changed by three orders, thus, we get a microwave photon switch in superconducting quantum computation architectures. Furthermore, by regulating the loaded quality factors, the coupling strength between the CPW and superconducting quantum circuits can be controlled, enabling the ability to manipulate stationary qubits and flying qubits. Full article
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14 pages, 3924 KB  
Article
Effects of Annealing Temperature on Bias Temperature Stress Stabilities of Bottom-Gate Coplanar In-Ga-Zn-O Thin-Film Transistors
by Yuyun Chen, Yi Shen, Yuanming Chen, Guodong Xu, Yudong Liu and Rui Huang
Coatings 2024, 14(5), 555; https://doi.org/10.3390/coatings14050555 - 30 Apr 2024
Cited by 2 | Viewed by 1759
Abstract
Defect annihilation of the IGZO/SiO2 layer is of great importance to enhancing the bias stress stabilities of bottom-gate coplanar thin-film transistors (TFTs). The effects of annealing temperatures (Ta) on the structure of the IGZO/SiO2 layer and the stabilities of [...] Read more.
Defect annihilation of the IGZO/SiO2 layer is of great importance to enhancing the bias stress stabilities of bottom-gate coplanar thin-film transistors (TFTs). The effects of annealing temperatures (Ta) on the structure of the IGZO/SiO2 layer and the stabilities of coplanar IGZO TFTs were investigated in this work. An atomic depth profile showed that the IGZO/SiO2 layer included an IGZO layer, an IGZO/SiO2 interfacial mixing layer, and a SiO2 layer. Higher Ta had only one effect on the IGZO layer and SiO2 layer (i.e., strengthening chemical bonds), while it had complex effects on the interfacial mixing layer—including weakening M-O bonds (M: metallic elements in IGZO), strengthening damaged Si-O bonds, and increasing O-related defects (e.g., H2O). At higher Ta, IGZO TFTs exhibited enhanced positive bias temperature stress (PBTS) stabilities but decreased negative bias temperature stress (NBTS) stabilities. The enhanced PBTS stabilities were correlated with decreased electron traps due to the stronger Si-O bonds near the interfacial layer. The decreased NBTS stabilities were related to increased electron de-trapping from donor-like defects (e.g., weak M-O bonds and H2O) in the interfacial layer. Our results suggest that although higher Ta annihilated the structural damage at the interface from ion bombardment, it introduced undesirable defects. Therefore, to comprehensively improve electrical stabilities, controlling defect generation (e.g., by using a mild sputtering condition of source/drain electrodes and oxides) was more important than enhancing defect annihilation (e.g., through increasing Ta). Full article
(This article belongs to the Special Issue Advanced Metal Oxide Films: Materials and Applications)
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13 pages, 2633 KB  
Article
High-Performance Potassium-Selective Biosensor Platform Based on Resistive Coupling of a-IGZO Coplanar-Gate Thin-Film Transistor
by Tae-Hwan Hyun and Won-Ju Cho
Int. J. Mol. Sci. 2023, 24(7), 6164; https://doi.org/10.3390/ijms24076164 - 24 Mar 2023
Cited by 6 | Viewed by 3026
Abstract
The potassium (K+) ion is an essential mineral for balancing body fluids and electrolytes in biological systems and regulating bodily function. It is associated with various disorders. Given that it exists at a low concentration in the human body and should [...] Read more.
The potassium (K+) ion is an essential mineral for balancing body fluids and electrolytes in biological systems and regulating bodily function. It is associated with various disorders. Given that it exists at a low concentration in the human body and should be maintained at a precisely stable level, the development of highly efficient potassium-selective sensors is attracting considerable interest in the healthcare field. Herein, we developed a high-performance, potassium-selective field-effect transistor-type biosensor platform based on an amorphous indium gallium zinc oxide coplanar-gate thin-film transistor using a resistive coupling effect with an extended gate containing a potassium-selective membrane. The proposed sensor can detect potassium in KCl solutions with a high sensitivity of 51.9 mV/dec while showing a low sensitivity of <6.6 mV/dec for NaCl, CaCl2, and pH buffer solutions, indicating its high selectivity to potassium. Self-amplification through the resistive-coupling effect enabled an even greater potassium sensitivity of 597.1 mV/dec. Additionally, we ensured the stability and reliability of short- and long-term detection through the assessment of non-ideal behaviors, including hysteresis and drift effects. Therefore, the proposed potassium-sensitive biosensor platform is applicable to high-performance detection in a living body, with high sensitivity and selectivity for potassium. Full article
(This article belongs to the Special Issue Feature Papers in 'Physical Chemistry and Chemical Physics' 2023)
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12 pages, 3027 KB  
Article
Fully Transparent and Highly Sensitive pH Sensor Based on an a-IGZO Thin-Film Transistor with Coplanar Dual-Gate on Flexible Polyimide Substrates
by Tae-Hwan Hyun and Won-Ju Cho
Chemosensors 2023, 11(1), 46; https://doi.org/10.3390/chemosensors11010046 - 4 Jan 2023
Cited by 13 | Viewed by 3645
Abstract
In this paper, we propose a fully transparent and flexible high-performance pH sensor based on an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) transducer with a coplanar dual-gate structure on polyimide substrates. The proposed pH sensor system features a transducer unit [...] Read more.
In this paper, we propose a fully transparent and flexible high-performance pH sensor based on an amorphous indium gallium zinc oxide (a-IGZO) thin-film transistor (TFT) transducer with a coplanar dual-gate structure on polyimide substrates. The proposed pH sensor system features a transducer unit consisting of a floating gate (FG), sensing gate (SG), and control gate (CG) on a polyimide (PI), and an extended gate (EG) sensing unit on a separate glass substrate. We designed a capacitive coupling between (SG) and (CG) through the FG of an a-IGZO TFT transducer to contribute to sensitivity amplification. The capacitance ratio (CSG/CCG) increases linearly with the area ratio; therefore, the amplification ratio of the pH sensitivity was easily controlled using the area ratio of SG/CG. The proposed sensor system improved the pH sensitivity by up to 359.28 mV/pH (CSG/CCG = 6.16) at room temperature (300 K), which is significantly larger than the Nernstian limit of 59.14 mV/pH. In addition, the non-ideal behavior, including hysteresis and drift effects, was evaluated to ensure stability and reliability. The amplification of sensitivity based on capacitive coupling was much higher than the increase in the hysteresis voltage and drift rate. Furthermore, we verified the flexibility of the a-IGZO coplanar dual-gate TFT transducer through a bending test, and the electrical properties were maintained without mechanical damage, even after repeated bending. Therefore, the proposed fully transparent and highly sensitive a-IGZO coplanar dual-gate TFT-based pH sensor could be a promising wearable and portable high-performance chemical sensor platform. Full article
(This article belongs to the Collection pH Sensors, Biosensors and Systems)
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11 pages, 2268 KB  
Article
Biocompatible Potato-Starch Electrolyte-Based Coplanar Gate-Type Artificial Synaptic Transistors on Paper Substrates
by Hyun-Sik Choi, Young-Jun Lee, Hamin Park and Won-Ju Cho
Int. J. Mol. Sci. 2022, 23(24), 15901; https://doi.org/10.3390/ijms232415901 - 14 Dec 2022
Cited by 10 | Viewed by 2708
Abstract
In this study, we propose the use of artificial synaptic transistors with coplanar-gate structures fabricated on paper substrates comprising biocompatible and low-cost potato-starch electrolyte and indium–gallium–zinc oxide (IGZO) channels. The electrical double layer (EDL) gating effect of potato-starch electrolytes enabled the emulation of [...] Read more.
In this study, we propose the use of artificial synaptic transistors with coplanar-gate structures fabricated on paper substrates comprising biocompatible and low-cost potato-starch electrolyte and indium–gallium–zinc oxide (IGZO) channels. The electrical double layer (EDL) gating effect of potato-starch electrolytes enabled the emulation of biological synaptic plasticity. Frequency dependence measurements of capacitance using a metal-insulator-metal capacitor configuration showed a 1.27 μF/cm2 at a frequency of 10 Hz. Therefore, strong capacitive coupling was confirmed within the potato-starch electrolyte/IGZO channel interface owing to EDL formation because of internal proton migration. An electrical characteristics evaluation of the potato-starch EDL transistors through transfer and output curve resulted in counterclockwise hysteresis caused by proton migration in the electrolyte; the hysteresis window linearly increased with maximum gate voltage. A synaptic functionality evaluation with single-spike excitatory post-synaptic current (EPSC), paired-pulse facilitation (PPF), and multi-spike EPSC resulted in mimicking short-term synaptic plasticity and signal transmission in the biological neural network. Further, channel conductance modulation by repetitive presynaptic stimuli, comprising potentiation and depression pulses, enabled stable modulation of synaptic weights, thereby validating the long-term plasticity. Finally, recognition simulations on the Modified National Institute of Standards and Technology (MNIST) handwritten digit database yielded a 92% recognition rate, thereby demonstrating the applicability of the proposed synaptic device to the neuromorphic system. Full article
(This article belongs to the Special Issue Biopolymer Composites 2022)
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15 pages, 8689 KB  
Article
Novel Reversible Comparator Design in Quantum Dot-Cellular Automata with Power Dissipation Analysis
by Mohsen Vahabi, Pavel Lyakhov, Ali Newaz Bahar, Akira Otsuki and Khan A. Wahid
Appl. Sci. 2022, 12(15), 7846; https://doi.org/10.3390/app12157846 - 4 Aug 2022
Cited by 9 | Viewed by 2845
Abstract
In very large-scale integration (VLSI) circuits, a partial of energy lost leads to information loss in irreversible computing because, in conventional combinatorial circuits, each bit of information generates heat and power consumption, thus resulting in energy dissipation. When information is lost in conventional [...] Read more.
In very large-scale integration (VLSI) circuits, a partial of energy lost leads to information loss in irreversible computing because, in conventional combinatorial circuits, each bit of information generates heat and power consumption, thus resulting in energy dissipation. When information is lost in conventional circuits, it will not be recoverable, as a result, the circuits are provided based on the reversible logic and according to reversible gates for data retrieval. Since comparators are one of the basic building blocks in digital logic design, in which they compare two numbers, the aim of this research is to design a 1-bit comparator building block based on reversible logic and implement it in the QCA with the minimum cell consumption, less occupied area, and lower latency, as well as to design it in a single layer. The proposed 1-bit reversible comparator is denser, cost-effective, and more efficient in quantum cost, power dissipation, and the main QCA parameters than that of previous works. Full article
(This article belongs to the Section Quantum Science and Technology)
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14 pages, 4336 KB  
Article
Ultra-Low-Cost Design of Ripple Carry Adder to Design Nanoelectronics in QCA Nanotechnology
by Mohsen Vahabi, Ali Newaz Bahar, Akira Otsuki and Khan A. Wahid
Electronics 2022, 11(15), 2320; https://doi.org/10.3390/electronics11152320 - 26 Jul 2022
Cited by 13 | Viewed by 2542
Abstract
Due to the development of integrated circuits and the lack of responsiveness to existing technology, researchers are looking for an alternative technology. Quantum-dot cellular automata (QCA) technology is one of the promising alternatives due to its higher switch speed, lower power dissipation, and [...] Read more.
Due to the development of integrated circuits and the lack of responsiveness to existing technology, researchers are looking for an alternative technology. Quantum-dot cellular automata (QCA) technology is one of the promising alternatives due to its higher switch speed, lower power dissipation, and higher device density. One of the most important and widely used circuits in digital logic calculations is the full adder (FA) circuit, which actually creates the problem of finding its optimal design and increasing performance. In this paper, we designed and implemented two new FA circuits in QCA technology and then implemented ripple carry adder (RCA) circuits. The proposed FAs and RCAs showed excellent performance in terms of QCA evaluation parameters, especially in cost and cost function, compared to the other reported designs. The proposed adders’ approach was 46.43% more efficient than the best-known design, and the reason for this superiority was due to the coplanar form, without crossovers and inverter gates in the designs. Full article
(This article belongs to the Special Issue Resource Sustainability for Energy and Electronics)
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15 pages, 5657 KB  
Article
Design and Implementation of New Coplanar FA Circuits without NOT Gate and Based on Quantum-Dot Cellular Automata Technology
by Mohsen Vahabi, Pavel Lyakhov, Ali Newaz Bahar and Khan A. Wahid
Appl. Sci. 2021, 11(24), 12157; https://doi.org/10.3390/app112412157 - 20 Dec 2021
Cited by 9 | Viewed by 3917
Abstract
The miniaturization of electronic devices and the inefficiency of CMOS technology due to the development of integrated circuits and its lack of responsiveness at the nanoscale have led to the acquisition of nanoscale technologies. Among these technologies, quantum-dot cellular automata (QCA) is considered [...] Read more.
The miniaturization of electronic devices and the inefficiency of CMOS technology due to the development of integrated circuits and its lack of responsiveness at the nanoscale have led to the acquisition of nanoscale technologies. Among these technologies, quantum-dot cellular automata (QCA) is considered one of the possible replacements for CMOS technology because of its extraordinary advantages, such as higher speed, smaller area, and ultra-low power consumption. In arithmetic and comparative circuits, XOR logic is widely used. The construction of arithmetic logic circuits using AND, OR, and NOT logic gates has a higher design complexity. However, XOR gate design has a lower design complexity. Hence, the efficient and optimized XOR logic gate is very important. In this article, we proposed a new XOR gate based on cell-level methodology, with the expected output achieved by the influence of the cells on each other; this design method caused less delay. However, this design was implemented without the use of inverter gates and crossovers, as well as rotating cells. Using the proposed XOR gate, two new full adder (FA) circuits were designed. The simulation results indicate the advantage of the proposed designs compared with previous structures. Full article
(This article belongs to the Special Issue Advanced Compound Semiconductor)
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11 pages, 2332 KB  
Article
Quantitative Analysis of Positive-Bias-Stress-Induced Electron Trapping in the Gate Insulator in the Self-Aligned Top Gate Coplanar Indium–Gallium–Zinc Oxide Thin-Film Transistors
by Dae-Hwan Kim, Hwan-Seok Jeong, Dong-Ho Lee, Kang-Hwan Bae, Sunhee Lee, Myeong-Ho Kim, Jun-Hyung Lim and Hyuck-In Kwon
Coatings 2021, 11(10), 1192; https://doi.org/10.3390/coatings11101192 - 29 Sep 2021
Cited by 12 | Viewed by 5699
Abstract
We experimentally extracted the positive bias temperature stress (PBTS)-induced trapped electron distribution within the gate dielectric in self-aligned top-gate (SA-TG) coplanar indium–gallium–zinc oxide (IGZO) thin-film transistors (TFTs) using the analytical threshold voltage shift model. First, we carefully examined the effects of PBTS on [...] Read more.
We experimentally extracted the positive bias temperature stress (PBTS)-induced trapped electron distribution within the gate dielectric in self-aligned top-gate (SA-TG) coplanar indium–gallium–zinc oxide (IGZO) thin-film transistors (TFTs) using the analytical threshold voltage shift model. First, we carefully examined the effects of PBTS on the subgap density of states in IGZO TFTs to exclude the effects of defect creation on the threshold voltage shift due to PBTS. We assumed that the accumulated electrons were injected into the gate dielectric trap states near the interface through trap-assisted tunneling and were consequently moved to the trap states, which were located further away from the interface, through the Poole–Frenkel effect. Accordingly, we quantitatively analyzed the PBTS-induced electron trapping. The experimental results showed that, in the fabricated IGZO TFTs, the electrons were trapped in the shallow and deep trap states simultaneously owing to PBTS. Electrons trapped in the shallow state were easily detrapped after PBTS termination; however, those trapped in the deep state were not. We successfully extracted the PBTS-induced trapped electron data within the gate dielectric in the fabricated SA-TG coplanar IGZO TFTs by using the proposed method. Full article
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9 pages, 1600 KB  
Article
Comparative Study on the Separate Extraction of Interface and Bulk Trap Densities in Indium Gallium Zinc Oxide Thin-Film Transistors Using Capacitance–Voltage and Current–Voltage Characteristics
by Dong-Ho Lee, Dae-Hwan Kim, Hwan-Seok Jeong, Seong-Hyun Hwang, Sunhee Lee, Myeong-Ho Kim, Jun Hyung Lim and Hyuck-In Kwon
Coatings 2021, 11(9), 1135; https://doi.org/10.3390/coatings11091135 - 18 Sep 2021
Cited by 3 | Viewed by 5832
Abstract
The interface and bulk trap densities were separately extracted from self-aligned top-gate (SA-TG) coplanar indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) using the low-frequency capacitance–voltage (CV) characteristics and space-charge-limited current (SCLC) under the flat-band condition. In the method [...] Read more.
The interface and bulk trap densities were separately extracted from self-aligned top-gate (SA-TG) coplanar indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) using the low-frequency capacitance–voltage (CV) characteristics and space-charge-limited current (SCLC) under the flat-band condition. In the method based on the CV curve, the energy distribution of the interface trap density was extracted using the low-frequency CV characteristics, and that of the bulk trap density was obtained by subtracting the density of interface trap states from the total subgap density of states (DOS) at each energy level. In the SCLC-based method, the energy distribution of the bulk trap density was extracted using the SCLC under the flat-band condition at high drain-to-source voltages, and that of the interface trap density was obtained by subtracting the density of bulk trap components from the total subgap DOS at each energy level. In our experiments, the two characterization techniques provided very similar interface and bulk trap densities and showed that approximately 60% of the subgap states originate from the IGZO/SiO2 interface at the conduction band edge in the fabricated IGZO TFTs, although the two characterization techniques are based on different measurement data. The results of this study confirm the validity of the characterization techniques proposed to separately extract the interface and bulk trap densities in IGZO TFTs. Furthermore, these results show that it is important to reduce the density of interface trap states to improve the electrical performance and stability of fabricated SA-TG coplanar IGZO TFTs. Full article
(This article belongs to the Special Issue New Advances in Thin-Film Transistor)
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11 pages, 1152 KB  
Article
A Study about Schottky Barrier Height and Ideality Factor in Thin Film Transistors with Metal/Zinc Oxide Nanoparticles Structures Aiming Flexible Electronics Application
by Ivan Rodrigo Kaufmann, Onur Zerey, Thorsten Meyers, Julia Reker, Fábio Vidor and Ulrich Hilleringmann
Nanomaterials 2021, 11(5), 1188; https://doi.org/10.3390/nano11051188 - 30 Apr 2021
Cited by 14 | Viewed by 3856
Abstract
Zinc oxide nanoparticles (ZnO NP) used for the channel region in inverted coplanar setup in Thin Film Transistors (TFT) were the focus of this study. The regions between the source electrode and the ZnO NP and the drain electrode were under investigation as [...] Read more.
Zinc oxide nanoparticles (ZnO NP) used for the channel region in inverted coplanar setup in Thin Film Transistors (TFT) were the focus of this study. The regions between the source electrode and the ZnO NP and the drain electrode were under investigation as they produce a Schottky barrier in metal-semiconductor interfaces. A more general Thermionic emission theory must be evaluated: one that considers both metal/semiconductor interfaces (MSM structures). Aluminum, gold, and nickel were used as metallization layers for source and drain electrodes. An organic-inorganic nanocomposite was used as a gate dielectric. The TFTs transfer and output characteristics curves were extracted, and a numerical computational program was used for fitting the data; hence information about Schottky Barrier Height (SBH) and ideality factors for each TFT could be estimated. The nickel metallization appears with the lowest SBH among the metals investigated. For this metal and for higher drain-to-source voltages, the SBH tended to converge to some value around 0.3 eV. The developed fitting method showed good fitting accuracy even when the metallization produced different SBH in each metal-semiconductor interface, as was the case for gold metallization. The Schottky effect is also present and was studied when the drain-to-source voltages and/or the gate voltage were increased. Full article
(This article belongs to the Section Nanoelectronics, Nanosensors and Devices)
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7 pages, 2010 KB  
Communication
High-Sensitivity pH Sensor Based on Coplanar Gate AlGaN/GaN Metal-Oxide-Semiconductor High Electron Mobility Transistor
by Seong-Kun Cho and Won-Ju Cho
Chemosensors 2021, 9(3), 42; https://doi.org/10.3390/chemosensors9030042 - 25 Feb 2021
Cited by 21 | Viewed by 3837
Abstract
The sensitivity of conventional ion-sensitive field-effect transistors is limited to the Nernst limit (59.14 mV/pH). In this study, we developed a pH sensor platform based on a coplanar gate AlGaN/GaN metal-oxide-semiconductor (MOS) high electron mobility transistor (HEMT) using the resistive coupling effect to [...] Read more.
The sensitivity of conventional ion-sensitive field-effect transistors is limited to the Nernst limit (59.14 mV/pH). In this study, we developed a pH sensor platform based on a coplanar gate AlGaN/GaN metal-oxide-semiconductor (MOS) high electron mobility transistor (HEMT) using the resistive coupling effect to overcome the Nernst limit. For resistive coupling, a coplanar gate comprising a control gate (CG) and a sensing gate (SG) was designed. We investigated the amplification of the pH sensitivity with the change in the magnitude of a resistance connected in series to each CG and SG via Silvaco TCAD simulations. In addition, a disposable extended gate was applied as a cost-effective sensor platform that helped prevent damages due to direct exposure of the AlGaN/GaN MOS HEMT to chemical solutions. The pH sensor based on the coplanar gate AlGaN/GaN MOS HEMT exhibited a pH sensitivity considerably higher than the Nernst limit, dependent on the ratio of the series resistance connected to the CG and SG, as well as excellent reliability and stability with non-ideal behavior. The pH sensor developed in this study is expected to be readily integrated with wide transmission bandwidth, high temperature, and high-power electronics as a highly sensitive biosensor platform. Full article
(This article belongs to the Collection pH Sensors, Biosensors and Systems)
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