# Novel Reversible Comparator Design in Quantum Dot-Cellular Automata with Power Dissipation Analysis

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## Abstract

**:**

## 1. Introduction

## 2. Background Materials

#### 2.1. QCA Basic Terminology

#### 2.2. Comparator

## 3. The Proposed Circuits

#### 3.1. Reversible Comparator with QCA

#### 3.2. Design of FG

#### 3.3. Design of TR Gate

#### 3.4. Design of Reversible 1-Bit Comparator Circuit

## 4. Performance Evaluation

#### 4.1. Design Results and Discussions

#### 4.2. Results Circuit Cost and Quantum Cost

#### 4.3. Complexity Estimation for the Proposed Circuits

^{2}consumption area, 0.25 delay clock, and 11 QCA cells, respectively. For the proposed TR gate, it had 0.073 µm

^{2}consumption area, 1.5 delay clock, and 64 QCA cells, respectively. The QCA circuit for the proposed 1-bit reversible comparator also had 0.237 µm

^{2}consumption area, 3.0 delay clock, and 165 QCA cells, respectively.

^{−10}, 27.56 × 10

^{–10}, and 58.32 × 10

^{− 10}(W), respectively. The proposed FG gate, TR gate, and 1-bit comparator showed improvements of 50.62%, 62.69%, and 63.95%, respectively, in comparison to the power parameter compared to the design [2]. Additionally, the PDP parameters for the proposed FG gate, TR gate, and 1-bit comparator circuit were 2.867 × 10

^{−22}, 41.34 × 10

^{−22}, and 174.96 × 10

^{−22}(Ws), respectively. As a result, in terms of the PDP parameter, the proposed FG gate, TR gate, and 1-bit comparator circuit, compared to [2], were superior at about 83.54%, 44.03%, and 63.95%, respectively.

#### 4.4. Energy Dissipation Analysis for the Proposed QCA Layout Circuits

## 5. Conclusions

## Author Contributions

## Funding

## Institutional Review Board Statement

## Informed Consent Statement

## Data Availability Statement

## Conflicts of Interest

## References

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**Figure 1.**Schematics types of QCA cells (

**a**) two structures logical values the QCA 90-degree cells, (

**b**) QCA 90-degree wire, (

**c**) two structures logical values the QCA 45-degree cells, (

**d**) QCA 45-degree wire.

**Figure 3.**QCA crossover, (

**a**) multilayer crossovers, (

**b**) coplanar crossovers by using rotation cells, and (

**c**) coplanar crossover by using standard cells.

**Figure 15.**Quantum cost for the proposed circuits [2].

**Figure 16.**Thermal hotspots of the (

**a**) FG gate, (

**b**) TR gate, and (

**c**) reversible 1-bit comparator at 0.5 Ek.

Input | Output | |||
---|---|---|---|---|

A | B | A > B | A < B | A = B |

0 | 0 | 0 | 0 | 1 |

0 | 1 | 0 | 1 | 0 |

1 | 0 | 1 | 0 | 0 |

1 | 1 | 0 | 0 | 1 |

Input | Output | ||
---|---|---|---|

A | B | P | Q |

0 | 0 | 0 | 0 |

0 | 1 | 0 | 1 |

1 | 0 | 1 | 1 |

1 | 1 | 1 | 0 |

Input | Output | ||||
---|---|---|---|---|---|

A | B | C | P | Q | R |

0 | 0 | 0 | 0 | 0 | 0 |

0 | 0 | 1 | 0 | 0 | 1 |

0 | 1 | 0 | 0 | 1 | 0 |

0 | 1 | 1 | 0 | 1 | 1 |

1 | 0 | 0 | 1 | 1 | 1 |

1 | 0 | 1 | 1 | 1 | 0 |

1 | 1 | 0 | 1 | 0 | 0 |

1 | 1 | 1 | 1 | 0 | 1 |

Parameter | Value |
---|---|

Cell width | 18 nm |

Cell height | 18 nm |

Relative permittivity | 12.9 |

Dot diameter | 5 nm |

Number of samples | 12,800 |

Convergence tolerance | 0.001 |

Clock high | 9.8 × 10^{−22} J |

Clock low | 3.8 × 10^{−23} J |

Clock amplitude factor | 2 |

Radius of effect | 65 nm |

Layer separation | 11.5 nm |

Maximum iteration per sample | 100 |

Proposed Reversible Circuits | Area (µm ^{2}) | Latency (clock) | Cost (Area × Latency ^{2}) |
---|---|---|---|

FG | 0.010 | 0.25 | 0.0006 |

TR gate | 0.073 | 1.50 | 0.164 |

1-bit comparator | 0.237 | 3.0 | 2.133 |

Proposed Reversible Circuits | Circuit Cost | Quantum Cost |
---|---|---|

FG | $1\alpha $ | 1 |

TR gate | $2\alpha +1\beta +1\gamma $ | 4 |

1-bit comparator | $5\alpha +2\beta +3\gamma $ | 9 |

Proposed Reversible Circuits | Area (µm ^{2}) | Cell Count | Delay (Clock) | Cost (Area × Latency^{2}) | Power (W) | PDP (Ws) (Power × Latency) | Crossover Type |
---|---|---|---|---|---|---|---|

FG [2] | 0.023 | 37 | 0.75 | 0.013 | 23.23 × 10^{−10} | 17.42 × 10^{−22} | Multi-Layer |

TR gate [2] | 0.090 | 122 | 1.0 | 0.090 | 73.86 × 10^{−10} | 73.86 × 10^{−22} | Multi-Layer |

1-bit comparator [2] | 0.343 | 319 | 3.0 | 3.087 | 161.8 × 10^{−10} | 485.4 × 10^{−22} | Multi-Layer |

Proposed FG | 0.010 | 11 | 0.25 | 0.0006 | 11.47 × 10^{−10} | 2.867 × 10^{−22} | Coplanar |

Proposed TR gate | 0.073 | 64 | 1.5 | 0.164 | 27.56 × 10^{−10} | 41.34 × 10^{−22} | Coplanar |

Proposed 1-bit comparator | 0.237 | 165 | 3.0 | 2.133 | 58.32 × 10^{−10} | 174.96 × 10^{−22} | Coplanar |

Proposed Reversible Circuits | Avg Leakage Energy (meV) | Avg Switching Energy (meV) | Avg Energy Diss (meV) | ||||||
---|---|---|---|---|---|---|---|---|---|

0.5 E_{K} | 1 E_{K} | 1.5 E_{K} | 0.5 E_{K} | 1 E_{K} | 1.5 E_{K} | 0.5 E_{K} | 1 E_{K} | 1.5 E_{K} | |

FG | 3.78 | 10.42 | 17.82 | 10.54 | 9.22 | 7.98 | 14.32 | 19.64 | 25.80 |

TR gate | 21.42 | 63.10 | 110.65 | 89.03 | 76.12 | 64.38 | 110.45 | 139.22 | 175.03 |

1-bit comparator | 53.82 | 162.65 | 287.96 | 267.05 | 230.20 | 195.15 | 320.87 | 392.85 | 483.11 |

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**MDPI and ACS Style**

Vahabi, M.; Lyakhov, P.; Bahar, A.N.; Otsuki, A.; Wahid, K.A. Novel Reversible Comparator Design in Quantum Dot-Cellular Automata with Power Dissipation Analysis. *Appl. Sci.* **2022**, *12*, 7846.
https://doi.org/10.3390/app12157846

**AMA Style**

Vahabi M, Lyakhov P, Bahar AN, Otsuki A, Wahid KA. Novel Reversible Comparator Design in Quantum Dot-Cellular Automata with Power Dissipation Analysis. *Applied Sciences*. 2022; 12(15):7846.
https://doi.org/10.3390/app12157846

**Chicago/Turabian Style**

Vahabi, Mohsen, Pavel Lyakhov, Ali Newaz Bahar, Akira Otsuki, and Khan A. Wahid. 2022. "Novel Reversible Comparator Design in Quantum Dot-Cellular Automata with Power Dissipation Analysis" *Applied Sciences* 12, no. 15: 7846.
https://doi.org/10.3390/app12157846