Quantitative Analysis of Positive-Bias-Stress-Induced Electron Trapping in the Gate Insulator in the Self-Aligned Top Gate Coplanar Indium – Gallium – Zinc Oxide Thin-Film Transistors

: We experimentally extracted the positive bias temperature stress (PBTS)-induced trapped electron distribution within the gate dielectric in self-aligned top-gate (SA-TG) coplanar indium – gallium – zinc oxide (IGZO) thin-film transistors (TFTs) using the analytical threshold voltage shift model. First, we carefully examined the effects of PBTS on the subgap density of states in IGZO TFTs to exclude the effects of defect creation on the threshold voltage shift due to PBTS. We assumed that the accumulated electrons were injected into the gate dielectric trap states near the interface through trap-assisted tunneling and were consequently moved to the trap states, which were located further away from the interface, through the Poole – Frenkel effect. Accordingly, we quantitatively analyzed the PBTS-induced electron trapping. The experimental results showed that, in the fabricated IGZO TFTs, the electrons were trapped in the shallow and deep trap states simultaneously owing to PBTS. Electrons trapped in the shallow state were easily detrapped after PBTS ter-mination; however, those trapped in the deep state were not. We successfully extracted the PBTS-induced trapped electron data within the gate dielectric in the fabricated SA-TG coplanar IGZO TFTs by using the proposed method. eV for the electrons trapped in shallow traps and n tr = 3.63 × 10 18 cm − 3 , x 0 = 2.3 nm, x 1 = 5.9 nm, and E OT = 1.63 eV for the electrons trapped in deep traps. The results of this study are expected to be helpful in determining the physical origin of the gate dielectric traps, which degrade the PBTS stability in IGZO


Introduction
In the last decade, indium-gallium-zinc oxide (IGZO) thin-film transistors (TFTs) have attracted significant attention because of their excellent electrical properties, low fabrication temperatures, and good large-area uniformities [1][2][3]. Recently, IGZO TFTs have been used for the backplane of active-matrix organic light-emitting diode (AMOLED) displays and for digital X-ray detectors [4][5][6]. However, with an increase in the application area of IGZO TFTs, the requirements for the electrical stability of IGZO TFTs have become more stringent. When used for the backplane of AMOLED displays or digital X-ray detectors, IGZO TFTs are frequently subjected to positive bias temperature stress (PBTS); therefore, it is crucial to understand the PBTS-induced instability mechanism in IGZO TFTs. Under PBTS, numerous electrons accumulate near the gate dielectric, and some electrons move toward the gate dielectric and become trapped in the dielectric trap states [7]. The trapped electrons partially screen the applied electric field from the gate terminal. Therefore, a large gate voltage is required to activate the TFT, thereby shifting the transfer curve in the positive direction [8]. To date, only a few studies have quantitatively analyzed PBTS-induced electron trapping in the gate dielectric in IGZO TFTs. Some previous studies have successfully established analytical models for the extraction of a detailed trapped electron distribution within the gate dielectric after PBTS [9,10]. However, the assumptions made in these studies are somewhat problematic. They assumed that the trapped electrons in the gate dielectric are the primary reason for the transfer curve shift under PBTS and that electrons are trapped in the trap state only at a single energy level. However, studies on IGZO TFTs have reported that the defect state creation within the IGZO channel can also induce the transfer curve shift under PBTS even when there is no change in the subthreshold swing (SS) values [11]. Moreover, it has been reported that carriers can be simultaneously trapped in multiple dielectric trap states with different energy levels under electrical stresses in metal-oxide-semiconductor structure devices [12].
In this study, we experimentally extracted the PBTS-induced trapped electron distribution within the gate dielectric by considering the effects of PBTS on the subgap density of states (DOS) in IGZO TFTs. Furthermore, we assumed that electrons can be simultaneously trapped in multiple dielectric trap states with different energy levels under PBTS in the fabricated IGZO TFTs. In this study, the accumulated electrons were assumed to be injected into the gate dielectric trap states near the interface through trap-assisted tunneling and then moved to the trap states located further away from the interface by the Poole-Frenkel (P-F) effect [13,14]. Using the proposed method, we successfully extracted the PBTS-induced trapped electron distribution within the gate dielectric in self-aligned topgate (SA-TG) coplanar IGZO TFTs, which are now widely used in commercially available AMOLED displays [15][16][17]. The results of this study are expected to contribute to the improvement of PBTS stability in IGZO TFTs.

Experimental Section
SA-TG coplanar IGZO TFTs were fabricated as shown in Figure 1. First, a buffer layer (SiNX/SiO2 = 30/200 nm) was deposited by plasma-enhanced chemical vapor deposition (PECVD) on a glass substrate. A 40-nm-thick IGZO layer (In:Ga:Zn = 1:1:1 at.%) was deposited by RF sputtering on a buffer layer. A 120-nm-thick SiOX layer was deposited by PECVD as a gate insulator, followed by the sequential deposition of a gate metal (Ti/Mo = 30 nm/250 nm.). After the deposition and patterning of the gate electrode and gate insulator, 300-nm-thick SiOX and 200-nm thick SiNX were sequentially deposited as passivation layers by PECVD and patterned to form via holes. A metal layer (Ti/Al/Ti = 30/600/60 nm) was deposited and patterned as the source and drain electrodes. Finally, the devices were thermally annealed at 340 °C to achieve a stable and uniform electrical performance. The channel width (W) and length (L) were 3 and 5 μm, respectively. The electrical parameters of the representative device were as follows: field-effect mobility (μFE) of 8.1 cm 2 /Vs, threshold voltage (VTH) of 0.15 V, and SS of 0.19 V/dec. Here, μFE was determined using the maximum transconductance method, and VTH was defined as the gate-to-source voltage value (VGS) inducing a drain current (ID) of 1 nA at a VDS of 0.1 V. The energy distribution of the subgap DOS was extracted using the monochromatic photonic C-V (MPCV) technique [18]. For MPCV characterization, a light source of 3 mW with a wavelength corresponding to the energy of 2.8 eV was used, and the C-V curves were measured at 100 kHz. The ΔVTH decomposition was performed by the stress time-divided measurement technique [19]. The current-voltage and capacitance-voltage (C-V) characteristics of the TFTs were extracted using an Agilent 4156C semiconductor parameter analyzer (Agilent Technologies, Santa Clara, CA, USA) and a 4284A precision LCR meter(Agilent Technologies, Santa Clara, CA, USA), respectively. All measurements were performed under dark ambient conditions unless stated otherwise.

Results and Discussion
First, we examined the effects of PBTS on the subgap DOS in the fabricated SA-TG coplanar IGZO TFTs. Figure 2 shows the time evolution of the transfer curves for the fabricated SA-TG coplanar IGZO TFTs under a constant VGS and VDS of 40 V and 0 V, respectively, at 80 °C. The transfer curve shifted in the positive direction with an increase in the stress time; the SS value exhibited no significant change. Previous studies on well-passivated IGZO TFTs have reported that the PBTS-induced parallel shift of the transfer curves can primarily be attributed to the creation of acceptor-like states below the Fermi level in the IGZO channel layer or the electron injection from IGZO into the gate dielectric [20,21].   Subsequently, we validated the assumption made in previous reports that electrons are trapped in the dielectric trap states only at a single energy level during PBTS in IGZO TFTs [10]. Figure 4 illustrates the time evolution of the threshold voltage shift (ΔVTH) during the stress (VGS = 40 V, VDS = 0 V, 80 °C, tst = 5000 s) and subsequent recovery (VGS = 0 V, VDS = 0 V, 80 °C, tst = 10,000 s) phases. The results reveal that the ΔVTH value decreased rapidly in the early stage of the recovery phase and was saturated at a certain value, implying that a part of trapped electrons were easily detrapped during this phase, but the remaining electrons were intact.    Figure 5b shows that the time evolution of both ΔVTH for the recoverable and non-recoverable trapped electrons were well-fitted by the stretched-exponential function. Generally, the stretched-exponential time dependence of ΔVTH is observed when electrons are trapped in the trap states at a single energy level [22,23]. The stretched-exponential equation for the ΔVTH(t) is defined as: where ΔVTH,0 is the ΔVTH at infinite time, β is the stretched-exponential exponent, and τ = τ0 × exp(Ea /kT) represents the characteristic trapping time of carriers, and Ea is the average effective energy barrier that electrons in the IGZO TFT channel need to overcome before they can enter the insulator, and τ0 is the thermal prefactor for emission over the barrier. The lines in Figures 6a and 6b show that the recoverable trap component and the nonrecoverable trap component was well fitted with the stretched exponential model functions. As shown in Figure 6c, the temperature dependence of the τ was confirmed, Ea was 0.29 eV for the recoverable trap and 0.78 eV for the non-recoverable trap. Therefore, we can assume that the electrons were simultaneously trapped in the two dielectric trap states with different energy levels under PBTS in the fabricated IGZO TFTs. Hereafter, the gate dielectric trap where the trapped electrons can and cannot be easily detrapped during the recovery phase will be called as "shallow trap" and "deep trap", respectively.
Finally, we extracted the PBTS-induced trapped electron distribution in the shallow and deep SiO2 gate dielectric traps in the fabricated SA-TG coplanar IGZO TFTs. Figure  7a presents the energy band diagram of the IGZO TFT under PBTS, where x represents the direction from the IGZO/SiO2 interface to SiO2. The energy level ET of the electron trap is defined by ΔEOT [eV], which indicates the energy difference between ET and the SiO2 conduction band minimum (EC, oxide). The Fermi energy level (EF) and ET cross at x0, which is extracted using the response time of the traps at the interface; the detailed methodology is provided in [24]. There were three different cases of trapped electrons in gate dielectrics under PBTS in IGZO TFTs. As depicted in Figure 7a, under a small VGS for a short tst, the electrons could not transfer to the position x0 and tunnel back easily to IGZO; as VGS and tst increased, the electrons tunneled deeper into the gate dielectric, and could not tunnel back easily to IGZO until they were trapped in ET below EF [10]. Further, as VGS and tst continued to increase, the trap states located near x0 were filled with electrons and thus could no longer capture them. The trapped electrons located below EF transferred to deeper positions by P-F conduction within the gate dielectric, as shown in Figure 7b   Accordingly, the trapped electron distribution in the gate dielectric under PBTS can be expressed by the following equation [26,27]: where ntr represents the concentration of the filled trap states in SiO2 at time t and position x, Jn is the transport current density in SiO2, G is the generation rate of the trapped electrons, and q represents the electron charge. The generation rate of the trapped electrons, G, is expressed based on the Shockley-Read-Hall recombination equation as follows [24,28]: where σ(x) = σ0 × exp(−ax) represents the location-dependent capture cross-section, σ0 is the capture cross-section at the semiconductor/gate dielectric interface, and a is the decay parameter, which depends on the tunneling effective mass of an electron and barrier height. In addition, vs represents the velocity at which the electrons move to the gate dielectric, and ns and NT are the electron density in the channel layer and trap density in the gate dielectric, respectively. The PBTS-induced transport current density in the gate dielectric is described by the P-F conduction [13,14,26]. where β = (q 3 /(πε0εSiO2)) 1/2 . Δz is the mean distance between two adjacent SiO2 trap states, r is the characteristic P-F attempt frequency of the trapped electrons, T is the temperature, and ζ is the P-F factor. Additionally, k denotes the Boltzmann's constant (8.62 × 10 −5 eV), ε0 denotes the vacuum permittivity (8.854 × 10 −14 F/cm), and εSiO2 denotes the relative permittivity of SiO2 (3.9). Because a significant portion of VGS falls on SiO2, the electric field in SiO2 (E) is expressed as E ≈ VGS/tox, where tox is the thickness of SiO2. By substituting equations (3) and (4) into (2) and solving the differential equation, we obtain: where the parameters ntr, x0, x1, and EOT in Equations (5)-(9) are obtained as a function of the PBTS condition and tst [26]. The results presented in Figures 4-6 show that the electrons were simultaneously trapped in the two dielectric trap states with different energy levels, called shallow and deep traps, under PBTS, in the fabricated IGZO TFTs. Therefore, we independently extracted the parameters ntr, x0, x1, and EOT for the electrons trapped in each gate dielectric trap under a specific PBTS condition. These parameters can be obtained from the separately extracted ΔVTH (t) values at that specific PBTS condition and T and VGS (or E)-dependence of each ΔVTH (t).  Table 1 summarizes the ntr, x0, x1, and EOT values for the electrons in each type of trap. Although further study is necessary, the extracted EOT values for each gate dielectric trap suggest that the shallow and deep traps (Figure 9) possibly originated from the oxygen vacancy defect and E' center defect in SiO2, respectively [29][30][31][32].

Conclusions
In this study, we quantitatively analyzed PBTS-induced electron trapping in the gate dielectric in SA-TG coplanar IGZO TFTs. First, we investigated the effects of PBTS on the subgap DOS in IGZO TFTs. Then, we examined the PBTS-induced ΔVTH values originating from electron trapping in shallow and deep gate dielectric traps. The data on the PBTSinduced trapped electrons in shallow and deep trap states was obtained from the analytical threshold voltage shift model based on trap-assisted tunneling and P-F effects. The extracted model parameters were ntr = 2.49 × 10 18 cm −3 , x0 = 1.2 nm, x1 = 3.3 nm, and EOT = 3.41 eV for the electrons trapped in shallow traps and ntr = 3.63 × 10 18 cm −3 , x0 = 2.3 nm, x1 = 5.9 nm, and EOT = 1.63 eV for the electrons trapped in deep traps. The results of this study are expected to be helpful in determining the physical origin of the gate dielectric traps, which degrade the PBTS stability in IGZO TFTs.