Design and Implementation of New Coplanar FA Circuits without NOT Gate and Based on Quantum-Dot Cellular Automata Technology

Abstract

The miniaturization of electronic devices and the inefficiency of CMOS technology due to the development of integrated circuits and its lack of responsiveness at the nanoscale have led to the acquisition of nanoscale technologies. Among these technologies, quantum-dot cellular automata (QCA) is considered one of the possible replacements for CMOS technology because of its extraordinary advantages, such as higher speed, smaller area, and ultra-low power consumption. In arithmetic and comparative circuits, XOR logic is widely used. The construction of arithmetic logic circuits using AND, OR, and NOT logic gates has a higher design complexity. However, XOR gate design has a lower design complexity. Hence, the efficient and optimized XOR logic gate is very important. In this article, we proposed a new XOR gate based on cell-level methodology, with the expected output achieved by the influence of the cells on each other; this design method caused less delay. However, this design was implemented without the use of inverter gates and crossovers, as well as rotating cells. Using the proposed XOR gate, two new full adder (FA) circuits were designed. The simulation results indicate the advantage of the proposed designs compared with previous structures.

1. Introduction

In today’s world, digital systems, and especially computer systems, play an important role in human life, and they are widely used. As a result, scientists and researchers have focused all of their efforts, both orbital and economic, on the development, improvement, and optimization of these systems. Moreover, the miniaturization of day-to-day electronic devices and components and the lack of responsiveness of common technology (CMOS), due to the appearance of problems at the nanoscale, have led to the acquisition of nanoscale devices. These devices have led to the coming existence of new nanoscale technologies. This field of electronics is called nanoelectronics or nanotechnology.

Among these technologies, quantum-dot cellular automata (QCA) is one of them, which has introduced a new landscape with unique features. QCA technology is considered as a new communication and computing technology due to its unique features, such as small size, high operating speed, and ultra-low power consumption. This technology has drawn the attention of many researchers and scientists. As a result, QCA can be considered as a potential solution to the scale limitations of complementary metal–oxide–semiconductor (CMOS) technology [1].

As previously mentioned, QCA technology is a novel nanoscale computational paradigm that may significantly enhance electronic circuit design technology [2]. It uses nano-level interactions to implement digital logic with low energy consumption and high clocking frequency. The advancements in the fabrication [3,4] and simulation [5,6] of QCA circuits have enabled researchers to design complete computational circuits [7]. Moreover, adders are one of the most basic and main computational circuits of digital logic, and as the most common and most widely used arithmetic digital circuits, they are the subject of many research studies [8].

However, with the appearance of new technologies to operate these technologies, it is necessary to create well-known tools needed for use in more complex applications, which, in the digital field, leads to the design of basic and main logic gates. The optimization of logic gates is very important because the improvement and optimization of these gates, due to their many uses in larger and more complicated circuits of the cause, improve and optimize these circuits. One of the most important and widely used logic gates is the XOR gate. The improvement and optimization of the XOR gate are very important. Adders are constituent and also one of the main and basic blocks of many VLSI systems, such as microprocessors and other various processors. One of the factors leading to optimizing the relevant blocks is the presentation of new designs in proportion to the development of new technologies. Designing a full adder with a simple structure and limited power consumption can play an essential role in simplifying digital circuits.

There are certain factors for a better design of full adder circuits. The most important criterion is the usage in more complex and larger circuits. Other criteria include low power consumption, high speed, and simplex circuits; these criteria themselves can be considered as components of the usage criterion. Among the most important items used are full adders, which are used in more complex and larger computing circuits and communication devices. Given that mass media is portable and fully available today, the main concern is an increase in battery life, which reduces the need for recharging. In other words, the main concern is reducing power consumption. Increasing the performance of the full adder is directly related to improving orbital parameters and improving system performance. Thus, many researchers are looking for ways to reduce power consumption. Adders are widely used in mobile digital devices, and they are the main element in many computing circuits. Nowadays, with the increasing use of electronic devices, the need for the optimal design of adders has become very important. The better the quality and parametric characteristics of the adders, the more direct their effect on the device used, and as a result, the device will be more popular. For this reason, the presentation of new structures for these circuits is of interest to integrated circuit designers. The main goal in designing digital adders is to increase speed and reduce power consumption.

One of the factors indicating the efficiency and good performance of the adder block is its use in larger and more practical circuits. Among the challenges in the design of the composite layout and cells is the challenge of designing the crossovers of wires in the best way to reduce costs [9,10,11]. Nowadays, non-adjacent clock phases are used to design the crossover of passing wires in a single layer [9,12], and the presence of crossover in the design increases the delay.

As a result, we did not use any crossovers in our designs in the present research, which in turn reduced the number of cells, the consumption area, and delay; therefore, the designs are coplanar due to the lack of need for crossovers. Therefore, we designed a new XOR gate, and we designed and implemented two full adder (FA) circuits with this proposed XOR gate, which was designed without an inverter gate (NOT gate); with a reduced number of cells, reduced consumption area, less delay, and reduced cost function; without crossovers and rotated cells (cell-45); and with the coplanar method.

The remainder of this article is organized as follows: an overview of QCA and previous works is given in Section 2. In Section 3, the design of the XOR gate is proposed, and then the architecture of the circuits of the full adder proposed by this research is presented. In Section 4 and Section 5, we compare the proposed designs with previous architectures. In Section 6, we conclude the article.

2. Background

The QCA Basics

The main component of QCA technology is the QCA cell. Each QCA cell contains two electrons, which, based on the coulombic interactions created between the two electrons [9], create two logical values, “0” and “1” [13]. Every QCA cell contains four holes, in which two electrons are trapped inside. By placing two electrons in four holes, due to the coulombic interactions between the electrons, two electrons are always positioned diagonally [14]. As a result, two stable states are created, and the electrons are diagonally placed inside the cavities to keep the maximum distance from each other and to establish the coulombic interaction law. By placing electrons in the diameter, two structures are created, which we attribute to the polar structures +1 and −1 with the logical values “1” and “0”, respectively; the poles 1+ and 1− are the same poles of the square cells shown in Figure 1 [15].

The clocked QCA maintains four clocking phases (switch, hold, release, and relax) to transmit a signal [8], as shown in Figure 2. During the switch phase, the interdot barriers become lower, and the data propagation happens through electron tunneling. The potential barrier is raised gradually, and the cell becomes polarized according to the modes of the input drives. At the end of this phase, the barriers are high enough to prevent electronic tunneling. During the hold phase, the barriers remain high, and the cell retains the polarization state. In this state, the cell maintains a steady state and transmits data to the neighboring cells. Indeed, the outputs can be used as inputs to the next stage. During the release phase, the barriers gradually decrease, and the QCA cells start to lose their polarization by lowering the barriers. During the relaxation state, cell barriers stay on the lowest level and in an unpolarized state [9,10].

The most simple gate in a logic circuit is the inverter gate (NOT gate). Figure 3 shows these gates [16]. In QCA logic circuit design, the majority gate (MV) is the most commonly used logic gate. This gate has three inputs and one output cell. The majority vote of the inputs determines the output. As a result, the majority of the logical values of the inputs specify the polarization and the value of the output cell [14,16]. Figure 4 shows different samples of this gate.

By stabilizing one of the inputs of the majority gate and valuing the logical “0” (polarization −1), the AND gate is constructed [16,17]. Figure 5 shows the AND gate of two inputs. The OR gate is also created by fixing one of the inputs of the majority gate and value logical “1” (polarization +1) [16,17]. Figure 6 also shows the OR gate of two inputs.

3. The Proposed Circuits

Adders are one of the main and most basic computational circuits in digital logic, which is the most common and most widely used digital arithmetic circuit.

Among the adder circuits, the full adder circuit is one of the most important and main computational circuits because this circuit is used in all arithmetic and computational circuits. In the present article, we first design and implement a new XOR gate. Then, by inverting the fixed cells of this proposed XOR gate, we implement the XNOR gate. Finally, using the same proposed XOR gate, we implement two new full adder (FA) circuits. These are designed to have a reduced cost function, and the implementations are performed without the use of rotational cells, without the use of crossovers and NOT gates, and in a coplanar manner (single layer) compared to the best previous models.

3.1. The XOR Gate Design

The XOR gate is one of the most momentous and main logic gates. Moreover, the XOR gate is the fundamental logic gate, plays an important role in digital circuit design, and is the core of several reversible gates. The proposed XOR gate in this research has the following advantages over the previous best design:

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Reduced number of cells consumed;

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Reduced consumption area;

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Reduced cost function;

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Less delay;

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No use of NOT gates;

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No use of crossovers;

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No use of rotary cells (45-degree cells).

Figure 7 shows the implementation of the proposed XOR gate design, and Figure 8 shows the simulator output of this gate. Equation (1) shows the logical relationship of this gate:

A⊕B = A.B’ + A’.B

(1)

To design a large circuit using smaller units, the area and delay of the small units are crucial because these smaller units are used multiple times. Hence, our main goal is to design an efficient XOR block. The proposed structure for a two-input XOR gate (with a 0.25 clock cycle delay) can be effectively utilized as a building block in designing multi-input XOR gates. Similarly, a three-input XOR gate can be designed using only two two-input XOR gates with a 0.5 clock cycle delay. A four-input XOR gate can be designed using only three cascaded two-input XOR gates with a 0.75 clock cycle. In the same way, an ultra-high-speed five-input XOR can be effectively designed using four cascaded gates working in one clock cycle as shown in Figure 9 and Figure 10, which show, respectively, a block diagram and implementation. Following the proposed five-input XOR gate, we also provided cost function, complexity and delay diagrams in Section 4 to illustrate the application of the cost function for L, K, P = 2. Equation (2) below describes this important criterion. As can be seen in cost function diagram in Section 4, in evaluating the comparison of the cost function parameter [18] for QCA XOR, the highest value is related to the designs [19,20], and the lowest value is related to our proposed design.

Cost Function = (M^K + I + C^L) × T^P

(2)

3.2. The XNOR Gate Design

The XNOR gate is achieved by inverting (NOT) the proposed XOR gate fixed cells. Figure 11 shows the implementation of the XNOR gate, and Figure 12 shows the simulator output of this gate. Equation (3) shows the logical relationship of this gate:

(A⊕B)’ = A’.B’ + A.B

(3)

3.3. The Full Adder (FA) Circuits’ Design

In this section, we designed and implemented two full adder (FA) circuits using the proposed XOR gate. The design was carried out with a delay of only three clock phases (0.75 clocks). The FA circuits proposed in this research are among the best samples ever designed. This is because they are designed without the use of a NOT gate, rotational cells, and crossovers, and they are designed to be coplanar. Equations (4) and (5) below are relationships related to the full adder circuits;

Table 1. Truth table of the full adder/subtractor.

A	B	Cin	S	Cout
0	0	0	0	0
0	0	1	1	0
0	1	0	1	0
0	1	1	0	1
1	0	0	1	0
1	0	1	0	1
1	1	0	0	1
1	1	1	1	1

is its truth table; Figure 13 and Figure 14 present, respectively, a block diagram and implementation of the a and b proposed FA circuits with QCA technology; and Figure 15 shows the simulator output of these FA circuits.

S = A⊕B⊕Cin = ABCin + A’B’Cin + AB’Cin’ + A’BCin’

(4)

Cout = M (A, B, Cin) = A.B + A.Cin + B.Cin

(5)

4. Performance Evaluation

This section evaluates the proposed circuits for the QCA implementation of the XOR gate and the FA circuits and compares them to those of previous works. For this evaluation, the number of cells, the area, and the delay obtained with the QCA Designer tool are considered. In

Table 2. Simulation parameters for the QCA Designer.

Parameter	Value
Cell width	18 nm
Cell height	18 nm
Dot diameter	5 nm
Number of samples	12,800
Convergence tolerance	0.001
Radius of effect	65 nm
Relative permittivity	12.9
Clock high	9.8 × 10−22 J
Clock low	3.8 × 10−23 J
Clock amplitude factor	2
Layer separation	11.5 nm
Maximum iteration per sample	100

, the simulation parameters used by the QCA Designer tool are listed. The simulation results of the proposed full adder (FA) circuits are shown in

Table 3. Relative evaluation of the proposed full adder (FA) circuits in comparison with the state of the art.

Design	Area (µm2)	Cell Count	Latency (Clock)	Crossover Type	45° Cells Count	NOT Gate Count
FA [21]	0.043	59	1	Coplanar (clocking based)	0	2
FA [22]	0.047	58	1	Coplanar (clocking based)	0	4
FA [23]	0.038	52	0.75	Not required	1	6
FA [24]	0.057	60	1	Not required	0	1
FA [25]	0.047	56	1	Coplanar (clocking based)	0	2
FA [26]	0.076	61	0.5	Coplanar (rotated cells)	8	4
FA [27]	0.043	44	1.5	Not required	0	6
Proposed FA design-1	0.043	45	0.75	Not required	0	0
Proposed FA design-2	0.037	43	0.75	Not required	0	0 (or 4 NOT gate and 4 majority gate)

. As can be seen, the proposed full adder (FA) circuits in this research were compared with the best previous examples. As can be seen, the proposed collectors of this research have a better advantage than the previous designs due to the lack of any crossovers and inverter gate (NOT gate), as well as the reduced use of the majority gate number.

As can be seen in Table 3, the consumption area of the proposed FA design-2 circuit is less than that of all the compared works. Regarding the consumption area of the proposed FA design-1 circuit, as shown in the table, the consumption area of this proposed design is equal to that of the design in [27]; however, the delay of our proposed design is better. Moreover, compared to the design in [23], the consumption area of our proposed design is higher, but in the design in [23], a 45-degree cell was used to implement the FA circuit.

Comparing the parameter of the number of cells used, as can be seen, the number of cells in the proposed circuit design of FA design-2 is less than that of all previous works, and in the case of the number of cells in the circuit of FA design-1, it can be said that compared to the design in [27], one more cell is used for implementation; however, our proposed FA design-1 circuit is designed using three clock phase (0.75 clock cycle).

Regarding the comparison of the proposed designs’ delay compared to the previous works, as can be seen, the delay of both of our proposed circuits is the same, and the delay of these two designs is less (superior) than that of all previous designs, except those in [23,26]. The delay of our proposed circuit designs is equal to that of the design in [22], but, instead, the number of its cells is more than that of our proposed designs, and also, in this design [23], 45-degree cells have been used to implement the circuit. Moreover, the delay of the proposed circuits compared to that of the design in [26] is more than one clock phase (0.25); however, the consumption area and the number of cells in this design are much higher than those of our proposed designs, and most importantly, in this design, not only is the crossover used, but also 45-degree cells are used to implement it, and this reduces the delay of this design, which instead has less cost function and strength and stability.

Regarding the parameters of the number of crossing intersections, the number of inverter gates, and the number of 45-degree cells, it can be said that none of these circuit parameters were used in the proposed design, which made the cost function of the proposed designs superior to that of previous works. It should be noted that the three-input majority gate used in the proposed FA design-2 is realized by four inverter gates; however, this majority gate is considered as one gate.

In this paper, the coefficients of L, K, and P are considered equal to one (L, K, P = 2); to evaluate the performance of the proposed XOR gate and compare the performance of the previous work, an evaluation was carried out. The diagram in Figure 16 shows the evaluation and comparison of the cost function criterion for L, K, P = 2. As can be seen in this diagram, the evaluation criterion of cost function for our proposed XOR gate design and that of the design in [24] is significantly superior to that of all previous designs. The reasons for this superiority are the lack of use of NOT gates and crossovers and the reduced number of majority gates used in the implementation of the proposed designs. These results and this comparison were carried out in the size range of 1≤ n ≤ 128. Figure 17 also shows a comparison diagram of the complexity parameter. In this evaluation, the number of majority gates, the number of inverter gates, and the number of crossovers were compared. To measure the complexity of the proposed XOR gate (nbit-input) with previous designs, this evaluation was performed in the range of 1≤ n ≤ 128. As can be seen in the review of this evaluation criterion, our proposed XOR gate design and the design in [24] are significantly superior to all previous designs. The diagram in Figure 18 also shows the delay parameter. This parameter is also used to measure the speed of the XOR gate. This comparison is also carried out in the range of 1≤ n ≤ 128, and as can be seen, the fastest XOR gate is related to our proposed design, [19,20,24,28,29,30,31,32,33,34,35]; our proposed design is coplanar, and crossovers are not used in any of the designs.

5. Power Delay Product (PDP) Analysis

The QCADesignerE was used to estimate the energy dissipation of the proposed FA, as well as the previous FA [21,22,23,24,25,26,27]. Here, we considered the default parameters of QCADesignerE, and this simulation tool provides energy dissipation data as shown in

Table 4. Energy and power dissipation analysis of the proposed full adder (FA) circuits in comparison with the state of the art.

Design	Energy (meV)	Power (W)	PDP (Ws)
FA [21]	22.0	35.248 × 10−10	35.248 × 10−22
FA [22]	27.20	43.579 × 10−10	43.579 × 10−22
FA [23]	24.20	38.772 × 10−10	29.079 × 10−22
FA [24]	26.0	41.657 × 10−10	41.657 × 10−22
FA [25]	28.60	45.822 × 10−10	45.822 × 10−22
FA [26]	31.50	50.469 × 10−10	25.234 × 10−22
FA [27]	20.50	32.845 × 10−10	49.267 × 10−22
Proposed FA design-1	28.20	45.181 × 10−10	33.886 × 10−22
Proposed FA design-2	23.70	37.972 × 10−10	28.479 × 10−22

. For power delay product (PDP) calculation, the standard theoretical clock frequency of 1 THz was considered.

Power Delay Product (PDP) = Power × Delay

(6)

6. Conclusions

The many FA designs in QCA technology use at least three layers for the crossovers; there are also a number of designs that use rotation cells or the design of the coplanar crossover with the utilization of non-adjacent clock phases. That is why we did not use any crossovers in our designs. As a result, they were designed not only to be coplanar but also to be designs without the use of any NOT gates, crossovers, and rotation cells, which creates a more stable and robust circuit. Our proposed designs are superior to the previous designs; the number of cells in design-2 is superior to that in all compared designs, with 29.51% and 2.27% reductions when compared to the smallest and largest previous examples, respectively, [26,27]. Moreover, the area consumption of design-2 is superior to that of all the compared designs, with reductions of 10.53% and 51.32% when compared to the most compact previous sample [23] and the largest previous sample [26], respectively. In the case of the delay parameter, the delay in our proposed design-1 and design-2 is shorter than that of any of the previous designs, except for the design in [26]. This design uses rotation cells, and both the number of cells and the area of consumption are higher than those of design-1 and design-2. The proposed XOR circuit can be implemented in QCA technology, which employs reversible logic for its implementation, including Feynman gate, Toffoli gate, Peres gate, and other reversible circuits where the XOR gate is the most important element for the design of these circuits.