Search Results (32)

In this paper, an experimental and theoretical study was undertaken to assess the impact of rare-earth co-doping of silica glasses on the light emission under X-rays. To this aim, radioluminescence (RL), phosphorescence (PP), and thermoluminescence (TL) signals of Ce³⁺/Gd³⁺ co-doped silica glasses have been successively measured and combined at different dose rates and irradiation temperatures. The RL response of the weakly co-doped sample was found to be temperature-independent between 273 K and 353 K. This result suggests that, based on this RL response, it is possible to design ionizing radiation sensors independent of the irradiation temperature in the corresponding range. Moreover, a model that considers the electron–hole pair generation, the charge carrier trapping–detrapping, and the electron–hole recombination in the localized and delocalized bands has been developed to reproduce these optical signals. The theoretical model also explains the temperature independence of the RL response between 273 K and 353 K for the weakly co-doped sample and, therefore, the operating principle of an X-ray sensor independent of the irradiation temperature. Full article

GaN HEMT devices are sensitive to the single event effect (SEE) caused by heavy ions, and their reliability affects the safe use of space equipment. In this work, a Ge ion (LET = 37 MeV·cm²/mg) and Bi ion (LET = 98 MeV·cm²/mg) were used to irradiate Cascode GaN power devices by heavy ion accelerator experimental device. The differences of SEE under three conditions: pre-applied electrical stress, different LET values, and gate voltages are studied, and the related damage mechanism is discussed. The experimental results show that the pre-application of electrical stress before radiation leads to an electron de-trapping effect, generating defects within the GaN device. These defects will assist in charge collection so that the drain leakage current of the device will be enhanced. The higher the LET value, the more electron–hole pairs are ionized. Therefore, the charge collected by the drain increases, and the burn-out voltage advances. In the off state, the more negative the gate voltage, the higher the drain voltage of the GaN HEMT device, and the more serious the back-channel effect. This study provides an important theoretical basis for the reliability of GaN power devices in radiation environments. Full article

Based on S-parameter measurements, the effect of dynamic trapping and de-trapping of charge in the gate oxide, the increase of dielectric loss due to polarization, and the impact of leakage current on the small-signal input impedance at RF is analyzed and represented. This is achieved by systematically extracting the corresponding model parameters from single device measurements at different frequency ranges, and then the methodology is applied to analyze the evolution of these parameters when the device is submitted to non-conducting electrical stress. This approach not only allows to inspect the impact of effects not occurring under DC conditions, such as the current due to the time varying dielectric polarization, but also to clearly distinguish effects in accordance with the functional form of their contribution to the device’s impedance. In fact, it is shown that minor changes in the model of the gate capacitance by including additional resistive and capacitive components allows for an excellent model-experiment correlation up to 30 GHz. Moreover, the accuracy of the correlation is shown to be maintained when applying the proposal to the device under different gate-to-source bias conditions and at several stages during off-state degradation. Full article

Room-temperature semiconductor radiation detectors (RTSD) such as CdZnTe are popular in Computed Tomography (CT) imaging and other applications. Transport properties and material defects with respect to electron and hole transport often need to be characterized, which is a labor intensive process. However, these defects often vary from one RTSD to another and are not known a priori during characterization of the material. In recent years, physics-inspired machine learning (PI-ML) models have been developed for the RTSDs which have the ability to characterize the defects in a RTSD by discretizing it volumetrically. These learning models capture the heterogeneity of the defects in the RTSD—which arises due to the fabrication process and the energy bands of elements in the RTSD. In those models, the different defects of RTSD—trapping, detrapping and recombination for electrons and holes—are present. However, these defects are often unknown. In this work, we show the capabilities of a PI-ML model which has been developed considering all the material defects to identify certain defects which are present (or absent). Additionally, these models can identify the defects over the volume of the RTSD in a discretized manner. Full article

This study aimed to propose a silicon-on-insulator (SOI)-based charge-trapping synaptic transistor with engineered tunnel barriers using high-k dielectrics for artificial synapse electronics capable of operating at high temperatures. The transistor employed sequential electron trapping and de-trapping in the charge storage medium, facilitating gradual modulation of the silicon channel conductance. The engineered tunnel barrier structure (SiO₂/Si₃N₄/SiO₂), coupled with the high-k charge-trapping layer of HfO₂ and high-k blocking layer of Al₂O₃, enabled reliable long-term potentiation/depression behaviors within a short gate stimulus time (100 μs), even under elevated temperatures (75 and 125 °C). Conductance variability was determined by the number of gate stimuli reflected in the maximum excitatory postsynaptic current (EPSC) and the residual EPSC ratio. Moreover, we analyzed the Arrhenius relationship between the EPSC as a function of the gate pulse number (N = 1–100) and the measured temperatures (25, 75, and 125 °C), allowing us to deduce the charge trap activation energy. A learning simulation was performed to assess the pattern recognition capabilities of the neuromorphic computing system using the modified National Institute of Standards and Technology datasheets. This study demonstrates high-reliability silicon channel conductance modulation and proposes in-memory computing capabilities for artificial neural networks using SOI-based charge-trapping synaptic transistors. Full article

The Electroluminescence (EL) technique has garnered significant interest over time for its reliable outcomes that enrich our understanding of the onset of electrical degradation in polymeric material. There is growing interest in combining both the EL technique and space charge measurement methods to obtain a more profound knowledge of the degradation and ageing of insulation. The generation of charge carriers in polymeric materials is widely acknowledged to be a crucial aspect of EL, involving injection, de-trapping, and field dissociation processes. This research investigates the variables that influence how EL emissions behave, including applied voltage or electric field, applied electrical frequency, ageing of material, and selection of materials and gases employed. It was found that these factors can be helpful in predicting the process of electrical ageing in insulation to avoid any catastrophes that may occur. A mathematical approach relating these factors and the intensity of EL is proposed through the aid of Dimensional Analysis method. A close relationship is obtained that suggests this mathematical approach can be utilised as a tool to predict electrical ageing of insulation material. Full article

The aim of this paper is to model the effects of threading dislocations on both gate and drain currents of AlGaN/GaN high electron mobility transistors (HEMTs). The fraction of filled traps increases with the threading dislocations, while the trapping effects cause a decrease in drain current and an increase in gate leakage current. To model the drain current drop, the two simplified RC subcircuits with diodes are proposed to capture the charge trapping/detrapping characteristics. The trap voltages V_{g_trap} and V_{d_trap} generated by RC networks are fed back into the model to capture the effects of traps on drain current. Considering acceptor-decorated dislocations, we present a novel Poole–Frenkel (PF) model to precisely describe the reverse leakage gate current, which plays a dominant role in the gate leakage current. The proposed model, which uses physical parameters only, is implemented in Verilog-A. It is in excellent agreement with the experimental data. Full article

In this paper, we demonstrate a device using a Ni/SiN/BN/p⁺-Si structure with improved performance in terms of a good ON/OFF ratio, excellent stability, and low power consumption when compared with single-layer Ni/SiN/p⁺-Si and Ni/BN/p⁺-Si devices. Its switching mechanism can be explained by trapping and de-trapping via nitride-related vacancies. We also reveal how higher nonlinearity and rectification ratio in a bilayer device is beneficial for enlarging the read margin in a cross-point array structure. In addition, we conduct a theoretical investigation for the interface charge accumulation/depletion in the SiN/BN layers that are responsible for defect creation at the interface and how this accounts for the improved switching characteristics. Full article

The effect of isothermal conditions on the trapping/detrapping process of charges in e-beam irradiated thermally aged XLPE insulation in scanning electron microscopy (SEM) has been investigated. Different isothermal conditions ranging from room temperature to 120 °C are applied on both unaged and aged XLPE samples (2 mm thick) by a suitable arrangement associated with SEM. For each applied test temperature, leakage, and influence currents have been measured simultaneously during and after e-beam irradiation. Experimental results show a big difference between the fresh and aged material regarding trapping and detrapping behavior. It has been pointed out that in the unaged material deep traps govern the process, whereas the shallow traps take part in the aged one. Almost all obtained results reveal that the trapped charge decreases and then increases as the temperature increases for the unaged sample. A deflection temperature corresponding to a minimum is observed at 50 °C. However, for the aged material, the maximum trapped charge decreases continuously with increasing temperature, and the material seems to trap fewer charges under e-beam irradiation at high temperature. Furthermore, thermal aging leads to the occurrence of detrapping process at high temperatures even under e-beam irradiation, which explains the decrease with time evolution of trapped charge during this period. The recorded leakage current increases with increasing temperature for both cases with pronounced values for aged material. The effect of temperature and thermal aging on electrostatic influence factor (K) and total secondary electron emission yield (σ) were also studied. Full article

The top-gated graphene field effect transistor (GFET) with electric-field induced doping polarity conversion has been demonstrated. The polarity of channel conductance in GFET can be transition from p-type to n-type through altering the gate electric field scanning range. Further analysis indicates that this complementary doping is attributed to the charge exchange between graphene and interface trap sites. The oxygen vacancies in Al₂O₃filmare are considered to be the origin of the trap sites. The trapping–detrapping process, which may be tuned by the electric field across the metal/oxide/graphene gate stack, could lead to the changing of the intrinsic electric property of graphene. This study promises to produce the complementary p- and n-type GFET for logic applications. Full article

Simulating and modelling electric field dynamics in the insulation of medium- and high-voltage DC electrical systems is needed to support insulation design optimization and to evaluate the impact of voltage transients on ageing mechanisms and insulation reliability. In order to perform accurate simulations, appropriate physical models must be adopted for the insulating material properties, particularly conductivity, which drives the electric field in a steady-state condition and contributes to determining the field behavior during voltage and load transients. In order to model insulation conductivity, polarization, and conduction, mechanisms must be inferred through charging and discharging current measurements, generally performed at different values of electric field and temperatures in flat specimens of the material under study. In general, both mechanisms are present, but one of them may be predominant with respect to the other depending on type of material. In this paper, we showed that models based on predominant polarization mechanisms were suitable to describe impregnated paper, but not polymers used for HV and MV DC insulation. In the latter case, indeed, trapping–detrapping and conduction phenomena were predominant compared to polarization, thus conductivity models had to be considered, in addition to or as a replacement of the polarization model, in order to carry out proper electric field simulations. Full article

This work showcases the physical insights of a core-shell dual-gate (CSDG) nanowire transistor as an artificial synaptic device with short/long-term potentiation and long-term depression (LTD) operation. Short-term potentiation (STP) is a temporary potentiation of a neural network, and it can be transformed into long-term potentiation (LTP) through repetitive stimulus. In this work, floating body effects and charge trapping are utilized to show the transition from STP to LTP while de-trapping the holes from the nitride layer shows the LTD operation. Furthermore, linearity and symmetry in conductance are achieved through optimal device design and biases. In a system-level simulation, with CSDG nanowire transistor a recognition accuracy of up to 92.28% is obtained in the Modified National Institute of Standards and Technology (MNIST) pattern recognition task. Complementary metal-oxide-semiconductor (CMOS) compatibility and high recognition accuracy makes the CSDG nanowire transistor a promising candidate for the implementation of neuromorphic hardware. Full article

Two-dimensional materials, including molybdenum disulfide (MoS${}_2$), present promising sensing and detecting capabilities thanks to their extreme sensitivity to changes in the environment. Their reduced thickness also facilitates the electrostatic control of the channel and opens the door to flexible electronic applications. However, these materials still exhibit integration difficulties with complementary-MOS standardized processes and methods. The device reliability is compromised by gate insulator selection and the quality of the metal/semiconductor and semiconductor/insulator interfaces. Despite some improvements regarding mobility, hysteresis and Schottky barriers having been reported thanks to metal engineering, vertically stacked heterostructures with compatible thin-layers (such as hexagonal boron nitride or device encapsulation) variability is still an important constraint to sensor performance. In this work, we fabricated and extensively characterized the reliability of as-synthesized back-gated MoS${}_2$ transistors. Under atmospheric and room-temperature conditions, these devices present a wide electrical hysteresis (up to 5 volts) in their transfer characteristics. However, their performance is highly influenced by the temperature, light and pressure conditions. The singular signature in the time response of the devices points to adsorbates and contaminants inducing mobile charges and trapping/detrapping carrier phenomena as the mechanisms responsible for time-dependent current degradation. Far from being only a reliability issue, we demonstrated a method to exploit this device response to perform light, temperature and/or pressure sensors in as-synthesized devices. Two orders of magnitude drain current level differences were demonstrated by comparing device operation under light and dark conditions while a factor up to 10${}^5$ is observed at vacuum versus atmospheric pressure environments. Full article

In this study, we demonstrate solution-processed memristor devices using a CdSe/ZnS colloidal quantum dot (CQD)/poly(methyl methacrylate) (PMMA) composite and their electrical characteristics were investigated. Particularly, to obtain stable memristive characteristics with a large current switching ratio, the concentration of CdSe/ZnS QDs in the PMMA matrix was optimized. It was found that with the CdSe/ZnS QD concentration of 1 wt%, the memristor device exhibited a high current switching ratio of ~10⁴ and a retention time over 10⁴ s, owing to the efficient charge trapping and de-trapping during the set and reset processes, respectively. In addition, we investigated the operational stability of the device by carrying out the cyclic endurance test and it was found that the memristor device showed stable switching behavior up to 400 cycles. Furthermore, by analyzing the conduction behavior of the memristor device, we have deduced the possible mechanisms for the degradation of the switching characteristics over long switching cycles. Specifically, it was observed that the dominant conduction mechanism changed from trap-free space charge-limited current conduction to trap charge-limited current conduction, indicating the creation of additional trap states during the repeated operation, disturbing the memristive operation. Full article

Interface traps between a gate insulator and beta-gallium oxide (β-Ga₂O₃) channel are extensively studied because of the interface trap charge-induced instability and hysteresis. In this work, their effects on mobility degradation at low temperature and hysteresis at high temperature are investigated by characterizing electrical properties of the device in a temperature range of 20–300 K. As acceptor-like traps at the interface are frozen below 230 K, the hysteresis becomes negligible but simultaneously the channel mobility significantly degrades because the inactive neutral traps allow additional collisions of electrons at the interface. This is confirmed by the fact that a gate bias adversely affects the channel mobility. An activation energy of such traps is estimated as 170 meV. The activated trap charges’ trapping and de-trapping processes in response to the gate pulse bias reveal that the time constants for the slow and fast processes decrease due to additionally activated traps as the temperature increases. Full article