Search Results (14)

Time-to-Digital Converters (TDCs) implemented on Field-Programmable Gate Arrays (FPGAs) have become increasingly prevalent across a wide range of scientific and engineering disciplines, such as high-energy physics experiments, autonomous driving, robotic navigation, and medical imaging, owing to their cost-effectiveness, high precision, and rapid development cycles. This article presents a 3-tap heterogeneous tapped delay-line (TDL) architecture for a FPGA-based TDC that can be employed for multi-channel time-of-flight measurement. The TDC desgin is based on the open-source jTDC, featuring single-cycle dead time and multi-channel expansion capabilities, with an original precision of 30 ps. Combined with jTDC’s dynamic caching mechanism using dual-page memory, this work employs a dual-cycle encoding and calibration. The proposed architecture has been implemented on a Xilinx Artix-7 FPGA. According to the experimental results, an optimal 3-tap heterogeneous TDL architecture achieves a resolution of 23.220 ps and a typical precision of 17.520 ps, whereas an optimal 4-tap heterogeneous TDL architecture demonstrates a resolution of 17.530 ps and a typical precision of 17.213 ps. A comparison with recently published state-of-the-art FPGA-based TDCs is provided at the end of the article. Full article

Time-to-Digital Converters (TDCs) are increasingly vital in modern measurement systems, with Field-Programmable Gate Arrays (FPGAs) offering a cost-effective platform despite challenges in asynchronous circuit design. Among various solutions, Tapped Delay-Line (TDL)-TDCs stand out for balancing precision, speed, and resource efficiency. However, a primary concern in FPGA-based TDL-TDCs are the Bubble Errors (BEs), i.e., spurious zeros introduced in the information code in the TDL that put the measurement precision at severe risk. The main goal of this contribution is to investigate the distribution of BEs, utilizing the Clock Region Crossing (CRC) within the FPGA as a case study, in order to demonstrate theoretically and experimentally that if BEs are manipulated properly, they create an interpolation effect that reduces the quantization error of the TDL-TDC. The analysis is carried out on a 256-tap fully integrated TDL-TDC implemented in a 28 nm Xilinx Artix 100T FPGA. The outcome confirms the potential to use CRC-BEs instead of suppressing them with precision increasing up to 0.17 ps r.m.s., or by almost 2% while also supporting the correctness of the model. Full article

This study investigated implementation strategies to optimize the precision of Tapped Delay Line (TDL) Time-to-Digital Converters (TDCs) designed for Xilinx 20 nm UltraScale Field-Programmable Gate Arrays (FPGAs). This optimization process aims to bridge the performance gap between FPGA-based TDCs, which are more flexible and suitable for fast prototyping, and the better-performing Application-Specific Integrated Circuit (ASIC) solutions, making FPGA-based TDCs viable for cutting-edge applications. Our key areas of focus included the optimal design of the decoder, the degree of sub-interpolation, and the placement of TDLs, with particular emphasis on the clocking distribution scheme within the Configurable Logic Block (CLB) to minimize the effects of Bubble Errors (BEs) and quantization error. The research led to the development and comparison of multiple TDL TDC solutions implemented on a Kintex UltraScale device (i.e., XCKU040-2FFVA1156E) housed on a KCU105 general-purpose Evaluation Board (EVB). From these, two main solutions emerged: one with high precision and one with low area. The first one was characterized by a Single-Shot Precision (SSP) of 2.64 ps r.m.s., and by Differential and Integral Non-Linearity (DNL/INL) Errors of 0.523 ps and 16.939 ps, respectively, occupying 883 CLBs and 126 kb of Block RAM (BRAM). The second one had an SSP of 3.75 ps r.m.s., a DNL of 0.599 ps, and an INL of 7.151 ps, and it occupies only 259 CLBs and 72 kb of BRAM. Full article

Fixed-wing unmanned aerial vehicles (UAVs) are widely considered as a vital candidate of aerial base station in beyond Fifth Generation (B5G) systems. Accurate knowledge of air-to-ground (A2G) wireless propagation is important for A2G communication system development and testing where, however, there is still a lack of A2G wideband channel models for such a purpose. In this paper, we present a wideband fixed-wing UAV-based A2G channel measurement campaign at 2.7 GHz, and consider typical flight phases, based on which a wide-sense stationary uncorrelated scattering (WSSUS)-based tapped delay line (TDL) wideband channel model is proposed. Parameters of individual channel taps are analyzed in terms of gain, amplitude distribution, Rice factor and delay-Doppler spectrum. It is shown that UAV flight phases significantly influence the channel tap parameters. Particularly, the “Bell”-type spectrum is found to be the most suitable model for the delay-Doppler spectrum under various flight scenarios for A2G propagation. The proposed channel model can provide valuable assistance and guidance for UAV communication system evaluation and network planning. Full article

Phase alignment of periodic events between multiple systems is required in multiple fields and applications. Most of the existing solutions focus on either low frequency and relatively low accuracy or high complexity, high accuracy and precision. In contrast, this work aimed to develop an intermediate solution, supporting high frequencies and relatively high accuracy and precision, with relatively low complexity. A hypothetical concept and mathematical model is presented with a hardware test implementation based entirely on FPGA resources. Deliberate resource selection and utilization enables a significant simplification of calculations and, as a result, a reduction in logic resource utilization. The proposed concept was implemented and verified using the AMD/Xilinx Artix 7 35T FPGA platform. Full article

Time-to-digital converters (TDCs) with superior performance are in high demand in application domains like light detection and ranging (LIDAR), nuclear physics, and time interval counters. One of the interesting architectures for field-programmable gate array (FPGA)-based TDCs is the tapped delay line (TDL) approach with carry chains as delay elements. However, the resolution of TDL-TDCs is limited, and linearity is weakened by the ultra-wide bins that correspond to the FPGA’s long routing wires crossing into another clock area. This paper presents wave union TDC using FPGA internal routing wires as delay elements to subdivide ultra-wide bins. The Zynq Evaluation and Development (ZED) board is used to implement and test the wave union types: A (WU-A) and B (WU-B) TDCs. According to experimental data, the WU-A TDC based on an 8 × 128 matrix of counters has a resolution of 5.7 ps, an integral nonlinearity (INL) of 1.1170 LSB (RMS), and a differential nonlinearity of 0.329 LSB (RMS). WU-A TDC improves DNL and INL by 19% and 57%, respectively, over ordinary TDC. The WU-B TDC uses an average of sixteen different time measurements, resulting in an effective resolution of up to 0.356 ps, a DNL of 0.60 LSB (RMS), and an INL of 1.04 LSB (RMS). These characteristics make the TDC suitable for time-of-flight applications such as LIDAR and for other general-purpose scientific instruments. Full article

Phase jitter is one of the crucial factors in modern digital electronics, determining the reliability of a design. This paper presents a novel approach to designing a jitter comparison system and methodology for FPGA chips using a Tapped Delay Line (TDL)—commonly used to implement a Time-to-Digital Converter (TDC). The design and its revision utilizing latches replacing some of the flip-flops are presented and discussed, with potential further improvements. A minimal temperature influence is verified and presented. The methodology of automated relative jitter measurements is discussed. Multiple different FPGA clock signal path configurations are measured, and the results are presented. The influence of clock routing is identified as critical when MMCM or PLL modules are omitted. It is demonstrated that with careful resource and routing allocation, the clock signal’s jitter performance does not have to be deteriorated by the absence of jitter filtering blocks. The proposed technique was implemented and verified and relative jitter performance was measured in the AMD/Xilinx Artix 7 35T FPGA platform. Full article

We describe a study on the effect of temperature variations on multi-channel time-to-digital converters (TDCs). The objective is to study the impact of ambient thermal variations on the performance of field-programmable gate array (FPGA)-based tapped delay line (TDL) TDC systems while simultaneously meeting the requirements of high-precision time measurement, low-cost implementation, small size, and low power consumption. For our study, we chose two devices, Artix-7 and ProASIC3L, manufactured by Xilinx and Microsemi, respectively. The radiation-tolerant ProASIC3L device offers better stability in terms of thermal sensitivity and power consumption compared to the Artix-7. To assess the performance of the TDCs under varying thermal conditions, a laboratory thermal chamber was utilized to maintain ambient temperatures ranging from −75 to 80 °C. This analysis ensured a comprehensive evaluation of the TDCs’ performance across a wide operational range. By utilizing the Artix-7 and ProASIC3L devices, we achieved root mean square (RMS) resolution of 24.7 and 554.59 picoseconds, respectively. Total on-chip power of 0.968 W was achieved using Artix-7, while 1.997 mW of power consumption was achieved using the ProASIC3L device. We worked to determine the temperature sensitivity for both FPGA devices, which could help in the design and optimization of FPGA-based TDCs for many applications. Full article

A tapped delay line (TDL)-based time-to-digital converter (TDC) implemented on an FPGA (Field Programmable Gate Array) is sensitive to nonlinearities because of significant variations in the delay of the delay elements. Most of the nonlinearity of FPGA-based TDCs comes from the routing of the design. It is promising to realize TDCs using internal routing resources available in FPGAs, as these devices contain a lot of routing resources and are resistant to voltage and temperature changes. This work implements and tests a TDC based on a series of counters driven by a variable delay line that exploits the internal routing resources available in the FPGA as delay elements. A manual placement and routing technique that results in greater resolution and linearity is proposed. The time-interleaving concept is used to improve the resolution of the TDC. A measurement matrix with 512 and 1024 parallel counters is implemented on a Zynq Evaluation and Development (ZED) board. The result of the 1024-unit TDC showed that a dynamic range of 93.6 ns can be measured using a 4-bit coarse gray code counter running at a reference frequency of 171 MHz, and a resolution of 5.7 ps is achieved. The implemented TDC is low-cost, has a fast time to market, and it benefits from the abundant routing resources in the FPGA. Full article

We present a Tapped Delay Line (TDL)-based Time to Digital Converter (TDC) using Wave Union type A (WU-A) architecture for applications that require high-precision time interval measurements with low size, weight, power, and cost (SWaP-C) requirements. The proposed TDC is implemented on a low-cost Field-Programmable Gate Array (FPGA), Artix-7, from Xilinx. Compared to prior works, our high-precision multi-channel TDC has the lowest SWaP-C requirements. We demonstrate an average time precision of less than 3 ps and a Root Mean Square resolution of about 1.81 ps. We propose a novel Wave Union type A architecture where only the first multiplexer is used to generate the wave union pulse train at the arrival of the start signal to minimize the required computational processing. In addition, an auto-calibration algorithm is proposed to help improve the TDC performance by improving the TDC Differential Non-Linearity and Integral Non-Linearity. Full article

Non-terrestrial network (NTN) systems can offer wide area coverage for applications requiring high mobility, which is expected in the sixth generation (6G) of telecommunication systems. This paper proposes a high-mobility support system based on the 5G-NR physical layer components for NTN connectivity. In this paper, we propose the optimization of 5G-NR numerologies and the impact of various modulation and coding schemes (MCS), 3GPP NR-NTN channel models, and MIMO/beamforming schemes with link-level simulation under pilot-aided-based perfect and DM-RS-based practical channel estimation at stationary UE and high mobility of 500 km/h, respectively. This paper also develops a link-level simulation of the 5G-NR physical downlink shared channel (PDSCH) under the 3GPP NR-NTN tapped delay line (TDL) channel model to support UE mobility up to 500 km/h. The bit error rate (BER), maximum achievable throughput (Mbps), and spectral efficiency (bps/Hz) are analyzed for the 5G-NR-based potential elements to be utilized in the evolution of NTN. Furthermore, the denser DM-RS symbol pattern is proposed for utilization in channel estimation to support high mobility, as simulation results prove their capability of fast decoding while using the front-loaded symbol structure. The simulation results show that the large 5G-NR numerologies, such as 120 kHz and DM-RS-based channel estimation, support the high UE mobility by providing high link reliability and the maximum achievable throughput of 368.832 Mbps and spectral efficiency of 3.68 bps/Hz under 64-QAM for TDL-E (LOS) channel model, which can also be a potential solution to support transonic speed mobility in the NTN of 6G services. Full article

The operational costs of the advanced Air Traffic Management (ATM) solutions are often prohibitive in low- and medium-sized airports. Therefore, new and complementary solutions are currently under research in order to take advantage of existing infrastructure and offer low-cost alternatives. The 5G signals are particularly attractive in an ATM context due to their promising potential in wireless positioning and sensing via Time-of-Arrival (ToA) and Angle-of-Arrival (AoA) algorithms. However, ToA and AoA methods are known to be highly sensitive to the presence of multipath and Non-Line-of-Sight (NLOS) scenarios. Yet, LOS detection in the context of 5G signals has been poorly addressed in the literature so far, to the best of the Authors’ knowledge. This paper focuses on LOS/NLOS detection methods for 5G signals by using both statistical/model-driven and data-driven/machine learning (ML) approaches and three challenging channel model classes widely used in 5G: namely Tapped Delay Line (TDL), Clustered Delay Line (CDL) and Winner II channel models. We show that, with simulated data, the ML-based detection can reach between 80% and 98% detection accuracy for TDL, CDL and Winner II channel models and that TDL is the most challenging in terms of LOS detection capabilities, as its richness of features is the lowest compared to CDL and Winner II channels. We also validate the findings through in-lab measurements with 5G signals and Yagi and 3D-vector antenna and show that measurement-based detection probabilities can reach 99–100% with a sufficient amount of training data and XGBoost or Random Forest classifiers. Full article

In this paper, we present a proposed field programmable gate array (FPGA)-based time-to-digital converter (TDC) architecture to achieve high performance with low usage of resources. This TDC can be employed for multi-channel direct Time-of-Flight (ToF) applications. The proposed architecture consists of a synchronizing input stage, a tuned tapped delay line (TDL), a combinatory encoder of ones and zeros counters, and an online calibration stage. The experimental results of the TDC in an Artix-7 FPGA show a differential non-linearity (DNL) in the range of [−0.953, 1.185] LSB, and an integral non-linearity (INL) within [−2.750, 1.238] LSB. The measured LSB size and precision are 22.2 ps and 26.04 ps, respectively. Moreover, the proposed architecture requires low FPGA resources. Full article

This paper presents a time-to-digital converter (TDC) based on a field programmable gate array (FPGA) with a tapped delay line (TDL) architecture. This converter employs dual delay lines (DDLs) to enable real-time calibrations, and the proposed DDL-TDC measures the statistical distribution of delays to permit the calibration of nonuniform delay cells in FPGA-based TDC designs. DDLs are also used to set up alternate calibrations, thus enabling environmental effects to be immediately accounted for. Experimental results revealed that relative to a conventional TDL-TDC, the proposed DDL-TDC reduced the maximum differential nonlinearity by 26% and the integral nonlinearity by 30%. A root-mean-squared value of 32 ps was measured by inputting the constant delay source into the proposed DDL-TDC. The proposed scheme also maintained excellent linearity across a range of temperatures. Full article