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15 pages, 6026 KB

Open AccessArticle

A 3.3 kV SiC Semi-Superjunction MOSFET with Trench Sidewall Implantations

by Marco Boccarossa, Kyrylo Melnyk, Arne Benjamin Renz, Peter Michael Gammon, Viren Kotagama, Vishal Ajit Shah, Luca Maresca, Andrea Irace and Marina Antoniou

Micromachines 2025, 16(2), 188; https://doi.org/10.3390/mi16020188 - 6 Feb 2025

Cited by 1 | Viewed by 2194

Abstract

Superjunction (SJ) technology offers a promising solution to the challenges faced by silicon carbide (SiC) Metal Oxide Semiconductor Field-Effect Transistors (MOSFETs) operating at high voltages (>3 kV). However, the fabrication of SJ devices presents significant challenges due to fabrication complexity. This paper presents a comprehensive analysis of a feasible and easy-to-fabricate semi-superjunction (SSJ) design for 3.3 kV SiC MOSFETs. The proposed approach utilizes trench etching and sidewall implantation, with a tilted trench to facilitate the implantation process. Through Technology Computer-Aided Design (TCAD) simulations, we investigate the effects of the p-type sidewall on the charge balance and how it affects key performance characteristics, such as breakdown voltage (BV) and on-state resistance (R_DS-ON). In particular, both planar gate (PSSJ) and trench gate (TSSJ) designs are simulated to evaluate their performance improvements over conventional planar MOSFETs. The PSSJ design achieves a 2.5% increase in BV and a 48.7% reduction in R_DS-ON, while the TSSJ design further optimizes these trade-offs, with a 3.1% improvement in BV and a significant 64.8% reduction in R_DS-ON compared to the benchmark. These results underscore the potential of tilted trench SSJ designs to significantly enhance the performance of SiC SSJ MOSFETs for high-voltage power electronics while simplifying fabrication and lowering costs. Full article

(This article belongs to the Special Issue SiC Based Miniaturized Devices, 3rd Edition)

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19 pages, 2271 KB

Open AccessArticle

Sensorless Junction Temperature Estimation of Onboard SiC MOSFETs Using Dual-Gate-Bias-Triggered Third-Quadrant Characteristics

by Yansong Lu, Yijun Ding, Jia Li, Hao Yin, Xinlian Li, Chong Zhu and Xi Zhang

Sensors 2025, 25(2), 571; https://doi.org/10.3390/s25020571 - 20 Jan 2025

Cited by 1 | Viewed by 2001

Abstract

Silicon carbide (SiC) metal oxide semiconductor field-effect transistors (MOSFETs) are a future trend in traction inverters in electric vehicles (EVs), and their thermal safety is crucial. Temperature-sensitive electrical parameters’ (TSEPs) indirect detection normally requires additional circuits, which can interfere with the system and increase costs, thereby limiting applications. Therefore, there is still a lack of cost-effective and sensorless thermal monitoring techniques. This paper proposes a high-efficiency datasheet-driven method for sensorless estimation utilizing the third-quadrant characteristics of MOSFETs. Without changing the existing hardware, the closure degree of MOS channels is controlled through a dual-gate bias (DGB) strategy to achieve reverse conduction in different patterns with body diodes. This method introduces a MOSFET operating current that TSEPs are equally sensitive to into the two-argument function, improving the complexity and accuracy. A two-stage current pulse is used to decouple the motor effect in various conduction modes, and the TSEP-combined temperature function is built dynamically by substituting the currents. Then, the junction temperature is estimated by the measured bus voltage and current. Its effectiveness was verified through spice model simulation and a test bench with a three-phase inverter. The average relative estimation error of the proposed method is below

7.2 %

in centigrade. Full article

(This article belongs to the Section Electronic Sensors)

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16 pages, 9608 KB

Open AccessArticle

A Non-Isolated High Voltage Gain DC–DC Converter Suitable for Sustainable Energy Systems

by Mamdouh L. Alghaythi

Sustainability 2023, 15(15), 12058; https://doi.org/10.3390/su151512058 - 7 Aug 2023

Cited by 10 | Viewed by 1946

Abstract

A non-isolated high gain DC–DC converter with magnetic coupling and a VM circuit is proposed in this study. By the use of the appropriate coupled inductor turn ratio, the output voltage of the recommended topology can be raised. The VM circuit is used to boost the voltage gain even further as well as to clamp the voltage spike across the switch, which results in a lower voltage on the switch. As a result, a MOSFET switch with a lower ON-state resistance (R_DS-ON) is used which, in turn, causes the conduction losses to be reduced and the entire system efficiency to be raised. Another advantage of the proposed structure is the ZCS of the diodes, which reduces the voltage drop losses caused by the regenerative diodes. The function modes analysis and the theoretical equations are accomplished. A comparison survey with other prior works is being developed to investigate the competency of the proposed converter. Based on this, the higher voltage gain and efficiency as well as the lower voltage stress on the semiconductors can be achieved by the proposed converter compared to the other converters. The effectiveness of the proposed converter is confirmed by the experimental results at a laboratory-scale operating under 150 V output voltage with a 96% efficiency at the 150 W full load and a 25 kHz switching frequency. Full article

(This article belongs to the Special Issue Renewable and Sustainable Energy Technologies, Opportunities, Challenges, and Promising Solutions)

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15 pages, 4344 KB

Open AccessArticle

A Precise Current Detection Method Using a Single Shunt and FET Rds(on) of a Low-Voltage Three-Phase Inverter

by Jae-Yeob Hwang, Ji-Hwan Park, Ji-Ho Choi, Jun-Ik Uhm, Geun-Ho Lee and Hee-Sun Lim

Electronics 2022, 11(1), 9; https://doi.org/10.3390/electronics11010009 - 22 Dec 2021

Cited by 4 | Viewed by 6043

Abstract

In this study, a low-voltage three-phase inverter was used alongside a shunt resistor to measure the current. However, it is known that this type of inverter and shunt resistor system has a region where the measurement of current is impossible due to structural limitations. As a result, many studies have focused on this region through the use of additional algorithms. Most studies measured current by forcibly adjusting the PWM duty in order to measure the current at the region where it could not be sensed. However, unfortunately, the total harmonic distortion (THD) increases in the current due to PWM adjustment. This causes an increase in torque ripple and inverter control instability. Therefore, in this paper, current was measured using the Rds(on) value between the drain source resistor when MOSFET was turned on and the Kalman filter in a low-voltage three-phase inverter with a single shunt. Additionally, the value was verified via comparison with the values achieved when a Hall-type current sensor and single shunt were used. As a result, this study confirmed that the inverter with a single shunt performs the same as a Hall-type sensor at the region where current cannot be detected. Full article

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18 pages, 7082 KB

Open AccessArticle

V_DS and V_GS Depolarization Effect on SiC MOSFET Short-Circuit Withstand Capability Considering Partial Safe Failure-Mode

by Yazan Barazi, Frédéric Richardeau, Wadia Jouha and Jean-Michel Reynes

Energies 2021, 14(23), 7960; https://doi.org/10.3390/en14237960 - 29 Nov 2021

Cited by 4 | Viewed by 3659

Abstract

This paper presents a detailed analysis of 1200 V Silicon Carbide (SiC) power MOSFET exhibiting different short-circuit failure mechanisms and improvement in reliability by V_DS and V_GS depolarization. The device robustness has undergone an incremental pulse under different density decreasing; either drain-source voltage or gate-driver voltage. Unlike silicon device, the SiC MOSFET failure mechanism firstly displays specific gradual gate-cracks mechanism and progressive gate-damage accumulations greater than 4 µs/9 J·cm⁻². Secondly, a classical drain-source thermal runaway appears, as for silicon devices, in a time greater than 9 µs. Correlations with short-circuit energy measurements and temperature simulations are investigated. It is shown that the first mechanism is an incremental soft gate-failure-mode which can be easily used to detect and protect the device by a direct feedback on the gate-driver. Furthermore, it is highlighted that this new mechanism can be sufficiently consolidated to avoid the second drain-source mechanism which is a hard-failure-mode. For this purpose, it is proposed to sufficiently depolarize the on-state gate-drive voltage to reduce the chip heating-rate and thus to decouple the failure modes. The device is much more robust with a short-circuit withstand time higher than 10 µs, as in silicon, no risk of thermal runaway and with an acceptable penalty on R_DS-ON. Full article

(This article belongs to the Special Issue Safety Design and Management of Power Devices including Gate-Drivers)

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11 pages, 3853 KB

Open AccessArticle

A Low-Voltage, Low-Power Reconfigurable Current-Mode Softmax Circuit for Analog Neural Networks

by Massimo Vatalaro, Tatiana Moposita, Sebastiano Strangio, Lionel Trojman, Andrei Vladimirescu, Marco Lanuzza and Felice Crupi

Electronics 2021, 10(9), 1004; https://doi.org/10.3390/electronics10091004 - 22 Apr 2021

Cited by 12 | Viewed by 4481

Abstract

This paper presents a novel low-power low-voltage analog implementation of the softmax function, with electrically adjustable amplitude and slope parameters. We propose a modular design, which can be scaled by the number of inputs (and of corresponding outputs). It is composed of input current–voltage linear converter stages (1st stages), MOSFETs operating in a subthreshold regime implementing the exponential functions (2nd stages), and analog divider stages (3rd stages). Each stage is only composed of p-type MOSFET transistors. Designed in a 0.18 µm CMOS technology (TSMC), the proposed softmax circuit can be operated at a supply voltage of 500 mV. A ten-input/ten-output realization occupies a chip area of 2570 µm² and consumes only 3 µW of power, representing a very compact and energy-efficient option compared to the corresponding digital implementations. Full article

(This article belongs to the Special Issue Design of Ultra-Low Voltage/Power Circuits and Systems)

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19 pages, 1352 KB

Open AccessArticle

MOS-FET as a Current Sensor in Power Electronics Converters

by Rok Pajer, Miro Milanoviĉ, Branko Premzel and Miran Rodiĉ

Sensors 2015, 15(8), 18061-18079; https://doi.org/10.3390/s150818061 - 24 Jul 2015

Cited by 12 | Viewed by 8873

Abstract

This paper presents a current sensing principle appropriate for use in power electronics’ converters. This current measurement principle has been developed for metal oxide semiconductor field effect transistor (MOS-FET) and is based on U_DS voltage measurement. In practice, shunt resistors and Hall effect sensors are usually used for these purposes, but the presented principle has many advantages. There is no need for additional circuit elements within high current paths, causing parasitic inductances and increased production complexity. The temperature dependence of MOS-FETs conductive resistance R_DS−ON is considered in order to achieve the appropriate measurement accuracy. The “MOS-FET sensor” is also accompanied by a signal acquisition electronics circuit with an appropriate frequency bandwidth. The obtained analogue signal is therefore interposed to an A-D converter for further data acquisition. In order to achieve sufficient accuracy, a temperature compensation and appropriate approximation is used (R_DS−ON = R_DS_−ON(V_j)). The MOS-FET sensor is calibrated according to a reference sensor based on the Hall-effect principle. The program algorithm is executed on 32-bit ARM M4 MCU, STM32F407. Full article

(This article belongs to the Section Physical Sensors)

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