Hardware Security and Trust, 2nd Edition

A special issue of Information (ISSN 2078-2489). This special issue belongs to the section "Information Security and Privacy".

Deadline for manuscript submissions: 31 July 2025 | Viewed by 974

Special Issue Editor


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Guest Editor
TIMA Laboratory, CNRS, 38031 Grenoble, France
Interests: hardware security; physical attacks; RTL countermeasures; secure test
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Special Issue Information

Dear Colleagues,

The presence of security functions at every level is becoming increasingly pervasive in all aspects of society due the growing number of connected devices and heavy data processing. Moreover, advances in processing power and computing paradigms also promote research into novel schemes and protocols, which pose new challenges in terms of implementation. The search for new cryptographic schemes (to find strong successors to the existing standards) and novel computing approaches requires continuous effort from the engineering community in order to achieve the best results.

In many domains, the need for adequate performance will require recurring hardware acceleration, at least partially: the presence of cryptographic functions in embedded processors as software or hardware implementations is now established, and the trend shows that all sorts of devices will soon be equipped with security features to guarantee confidentiality and authenticity. On the other hand, the possibilities available to attackers aiming to bypass the security of a system have also increased. Microarchitectural vulnerabilities found in modern CPUs (e.g., Spectre, Meltdown, Spoiler, and RowHammer) are very recent, proving that possible breaches may be discovered at any time. “Traditional” implementation attacks (side channel analysis and fault attacks) are still a major concern, which necessitates continuous efforts from the research community in both directions (attacks and countermeasures), from the lowest to the highest level of abstraction.

This Special Issue seeks novel contributions to improve the current state-of-the-art literature on methodologies, tools, and results on architectures, experimental attacks, and countermeasures for embedded systems in the field of hardware security and trust. Topics of interest include but are not limited to the following:

  • Embedded implementation of cryptographic algorithms;
  • Physical attacks against embedded implementations and related countermeasures;
  • Security of test infrastructures;
  • Hardware Trojans and detection techniques;
  • Hardware security primitives;
  • Secure processors and architectures;
  • Microarchitectural attacks: characterization, exploitation, and protections;
  • Post-quantum cryptographic implementations;
  • Lightweight cryptographic implementations;
  • Secure implementation in constrained environments.

Dr. Paolo Maistri
Guest Editor

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Keywords

  • secure hardware
  • physical attacks
  • IC trust

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Related Special Issue

Published Papers (2 papers)

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Research

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20 pages, 1792 KiB  
Article
A Lightweight Deep Learning Model for Profiled SCA Based on Random Convolution Kernels
by Yu Ou, Yongzhuang Wei, René Rodríguez-Aldama and Fengrong Zhang
Information 2025, 16(5), 351; https://doi.org/10.3390/info16050351 - 27 Apr 2025
Viewed by 62
Abstract
In deep learning-based side-channel analysis (DL-SCA), there may be a proliferation of model parameters as the number of trace power points increases, especially in the case of raw power traces. Determining how to design a lightweight deep learning model that can handle a [...] Read more.
In deep learning-based side-channel analysis (DL-SCA), there may be a proliferation of model parameters as the number of trace power points increases, especially in the case of raw power traces. Determining how to design a lightweight deep learning model that can handle a trace with more power points and has fewer parameters and lower time costs for profiled SCAs appears to be a challenge. In this article, a DL-SCA model is proposed by introducing a non-trained DL technique called random convolutional kernels, which allows us to extract the features of leakage like using a transformer model. The model is then processed by a classifier with an attention mechanism, which finally outputs the probability vector for the candidate keys. Moreover, we analyze the performance and complexity of the random kernels and discuss how they work in theory. On several public AES datasets, the experimental results show that the number of required profiling traces and trainable parameters reduce, respectively, by over 70% and 94% compared with state-of-the-art works, while ensuring that the number of power traces required to recover the real key is acceptable. Importantly, differing from previous SCA models, our architecture eliminates the dependency between the feature length of power traces and the number of trainable parameters, which allows for the architecture to be applied to the case of raw power traces. Full article
(This article belongs to the Special Issue Hardware Security and Trust, 2nd Edition)
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Review

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22 pages, 269 KiB  
Review
Countermeasures Against Fault Injection Attacks in Processors: A Review
by Roua Boulifa, Giorgio Di Natale and Paolo Maistri
Information 2025, 16(4), 293; https://doi.org/10.3390/info16040293 - 5 Apr 2025
Viewed by 362
Abstract
Physical attacks pose a significant threat to the security of embedded processors, which have become an integral part of our daily lives. Processors can be vulnerable to fault injection attacks that threaten their normal and secure behavior. Such attacks can lead to serious [...] Read more.
Physical attacks pose a significant threat to the security of embedded processors, which have become an integral part of our daily lives. Processors can be vulnerable to fault injection attacks that threaten their normal and secure behavior. Such attacks can lead to serious malfunctions in applications, compromising their security and correct behavior. Therefore, it is crucial for designers and manufacturers to consider these threats while developing embedded processors. These attacks may require only a moderate level of knowledge to execute and can compromise the normal behavior of the targeted devices. These attacks can be faced by developing effective countermeasures. This paper explores the main existing countermeasures against fault injection attacks in embedded processors, to understand and implement effective solutions against those threats. Subsequently, we further investigate solutions related to RISC-V, focusing on its hardware and architecture security. Full article
(This article belongs to the Special Issue Hardware Security and Trust, 2nd Edition)
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