Time-Interleaved SAR ADC in 22 nm Fully Depleted SOI CMOS

Abstract

This work presents the design and simulation of a time-interleaved successive approximation register (SAR) analog-to-digital converter (ADC) implemented in GlobalFoundries’ 22 nm Fully Depleted Silicon-on-Insulator (FD-SOI) CMOS process. Motivated by the increasing demand for high-speed electrical links in data center and AI/ML applications, the proposed ADC architecture targets medium-resolution, high-throughput conversion with optimized power and area efficiency. The design leverages asynchronous SAR operation, bootstrapped sampling switches, and a hybrid binary/non-binary capacitive digital-to-analog converter (DAC) to achieve robust performance across process, voltage, and temperature (PVT) variations. System-level modeling using channel operating margin (COM) methodology guided the specification of key circuit blocks, enabling efficient trade-offs between resolution, speed, and power. Post-layout simulations demonstrated effective number of bits (ENOB) performance consistent with system requirements, while Monte Carlo analysis confirmed the statistical yield. The converter achieved competitive figures of merit compared to state-of-the-art designs, as benchmarked against the Murmann ADC survey. This work highlights critical design considerations for scalable mixed-signal architectures in advanced CMOS nodes and lays the foundation for future integration in high-speed SerDes systems.

1. Introduction

The exponential growth of data-intensive applications such as artificial intelligence (AI), machine learning (ML), and cloud computing has driven the demand for high-speed, low-power interconnects in modern data centers and edge computing platforms. These systems rely on massively parallel accelerator application-specific integrated circuits (ASICs), often fabricated in advanced CMOS nodes, to meet performance and energy efficiency targets. However, the bottleneck in such systems increasingly lies in the interconnect infrastructure—specifically, the serializer/deserializer (SerDes) links that enable chip-to-chip and rack-to-rack communication [1,2].

Traditional analog SerDes architectures face challenges in scaling to higher data rates due to power inefficiencies and sensitivity to channel loss. As shown in Figure 1, Ethernet switch bandwidth has increased dramatically over the past two decades, necessitating new receiver architectures that can operate reliably over lossy channels.

To address these challenges, ADC-based SerDes architectures have emerged as a promising solution. These systems leverage time-interleaved analog-to-digital converters (ADCs) and digital equalization to achieve high-speed data recovery with improved robustness to channel impairments. In particular, successive approximation register (SAR) ADCs are attractive due to their low power consumption, scalability in advanced CMOS nodes, and suitability for medium-resolution, medium-speed applications [3].

Modern server architectures, such as AMD’s Zen 5 Ryzen 9000 SiP, illustrate the trend toward heterogeneous integration, where compute and I/O dies are co-packaged to manage high-speed signaling and power delivery. These systems often employ PAM-4 modulation to double data throughput without increasing bandwidth, further motivating the need for efficient ADC-based receivers [4].

This work presents the design and simulation of a time-interleaved SAR ADC implemented in GlobalFoundries’ 22 nm FD-SOI CMOS process. The converter is optimized for use in ADC-based SerDes front-ends and demonstrates competitive performance in terms of area, power, and effective number of bits (ENOB). The remainder of this paper is organized as follows: Section 2 describes the process technology, system-level modeling, and circuit implementation. Section 3 presents simulation results and performance metrics. Section 4 compares the design to state-of-the-art converters, and Section 5 concludes with future directions.

2. Materials and Methods

2.1. Process Technology

The ADC was implemented in GlobalFoundries’ 22 nm FD-SOI CMOS process (22FDX), a silicon-on-insulator (SOI) technology featuring an ultra-thin buried oxide layer. This structure reduces parasitic capacitance and enables body biasing for performance tuning. The process supports both thin-oxide core devices for high-speed logic and thick-oxide devices for I/O and power management. Analog designers benefit from high substrate resistivity and the ability to apply forward or reverse body bias to modulate the threshold voltage and leakage [5,6,7].

2.2. SAR ADC Architecture

The SAR ADC operates asynchronously at 810 MHz with a 25% duty cycle sampling clock. Asynchronous operation reduces clock distribution complexity and improves metastability resilience. The converter is designed for low-input-capacitance and small-area conditions, making it suitable for time-interleaved arrays. The architecture includes a bootstrapped track-and-hold, a StrongArm comparator, a split capacitive DAC, and asynchronous SAR logic. Figure 2 details the overall ADC architecture and block layout overview.

2.3. Track-and-Hold Circuit

The track-and-hold circuit uses a bootstrapped switch to maintain a constant gate-to-source voltage ($V_{GS}$), minimizing distortion due to input-dependent on-resistance. The switch topology is based on the Kaiser configuration [8], with cross-coupled always-off NMOS devices to stabilize off-state impedance. Simulations showed a 20 dB improvement in total harmonic distortion (THD) compared to a complementary CMOS switch. Figure 3 shows the bootstrapped switch utilized within the track-and-hold circuit.

2.4. Comparator Design

The comparator is a StrongArm latch (shown in Figure 4), chosen for its high-speed, low-power operation and compact layout. It operates in two phases: precharge and evaluation. During precharge, PMOS devices charge internal nodes to $V_{DD}$. When the clock transitions, the differential input voltage is amplified by the input pair, and positive feedback rapidly resolves the output to a full-swing digital level. The comparator’s gain phase lasts approximately 20% of the conversion cycle, with a simulated propagation delay of less than 60 ps for a 100 µV input at worst-case corners.

2.5. Capacitive DAC

The capacitive DAC (CDAC) uses a split, non-binary weighted array to reduce total capacitance and switching energy (see Figure 5). The most significant bits (MSBs) are binary-weighted, while the least significant bits (LSBs) use a split array for improved linearity and reduced area. The DAC supports energy-efficient switching schemes such as monotonic and set-and-down switching [9,10]. The base unit capacitor used for the CDAC is a metal-oxide–metal (MOM) capacitor with a capacitance of 2.726 fF. Each capacitor is 1 $\mathsf{\mu }$m² between metal layers 5 and 7.

2.6. SAR Logic and Clock Generation

The SAR logic is implemented using a ring counter and an asynchronous control scheme, shown in Figure 6. The ring counter generates timing signals for each bit decision, while the SAR register stores the comparator outputs and updates the DAC control word. The asynchronous operation allows the converter to adaptively allocate time for each bit decision, improving energy efficiency and robustness to PVT variations.

A handful of the most critical SAR signals are shown in Figure 7. The progression of the circuit through a single conversion cycle is shown within this diagram. The differential voltage near the top shows the progression from the MSB conversion to the LSB conversion with the residue beginning to approach zero as the conversion progresses. The converter’s response is used to form the next CDAC signal (only the positive portion is shown for brevity).

2.7. Design for Test

To facilitate post-fabrication testing, the design includes the following components:

• Output Latch: This captures the final conversion result and drives it to external pads.
• Level Shifters: These convert the core voltage (0.8 V) into I/O voltage (1.8 V) for compatibility with test equipment (shown in Figure 8).
• Output Drivers: These are full-swing CMOS drivers designed to drive oscilloscope probe capacitance.

2.8. Layout and Physical Design Considerations

The SAR ADC layout was integrated into a time-interleaved architecture. The design was constrained to a narrow horizontal footprint to accommodate multiple ADC instances in parallel. Power integrity was ensured through a low-impedance power grid and careful placement of decoupling capacitors. Clock distribution was routed on the highest metal layers to minimize resistance and skew. The total area is 53 $\mathsf{\mu }$m in height by 15.5 $\mathsf{\mu }$m in width giving, a total area of 821.5 $\mathsf{\mu }$m². Figure 9 shows the narrow structure of the layout, which maintains the large interleaving ratio for the converter. The capacitors flank the sides on the top and bottom and represent a minor portion of the layout (1.4 $\mathsf{\mu }$m by 20 $\mathsf{\mu }$m), whereas the bulk of the layout in the center focuses on the individual circuit blocks within the architecture.

Parasitic extraction was performed using foundry-provided rule-based tools. Special attention was given to the capacitive DAC array, where fringe capacitance and metal density effects can significantly impact matching. For high-accuracy modeling, 3D electromagnetic simulation is recommended in future iterations.

2.9. Time-Interleaved Integration

The ADC is designed to be used in a time-interleaved configuration, where multiple SAR ADCs operate in parallel with staggered sampling clocks (see Figure 10 for an example). This approach increases the effective sampling rate while maintaining the power and area efficiency of each individual converter. For this ADC design, the designers used two channels in parallel, with the effective sampling rate being 810 MS/s for the system with each parallel ADC operating at 405 MS/s.

Each ADC channel includes its own track-and-hold, comparator, DAC, and SAR logic. Clock skew and gain mismatches between channels are mitigated through careful layout symmetry and digital calibration. The asynchronous nature of the SAR logic simplifies the clock distribution, as only the sampling edge must be aligned across channels.

2.10. Testability and I/O Design

To support post-silicon validation, the design includes the following components:

• Digital Output Latch: This captures the final conversion result and drives it to external pads.
• Level Shifters: These translate the 0.8 V core logic into 1.8 V I/O levels.
• Output Drivers: These refer to full-swing CMOS drivers capable of driving oscilloscope probe capacitance.
• ESD Protection: This refers to minimal diode-based protection to preserve analog performance, with separate clamps for core and I/O domains.

Figure 11 details the connections between the output drivers, pads, and corresponding ESD protection.

3. Results

3.1. Simulation Methodology

Time-domain, large-signal simulations were conducted using foundry-provided SPICE models. The testbench included non-idealities such as finite supply resistance and realistic clock skew modeled using digital library cells. An ideal digital-to-analog converter (DAC) was used to reconstruct the analog output for spectral analysis.

Simulations targeted the typical–typical (tt) process corner at 60 °C, representative of co-location with high-power digital cores. Additional corners, such as slow–slow at −40 °C, were used to evaluate robustness across process–voltage–temperature (PVT) variations. Monte Carlo simulations with post-layout parasitic extraction were used to estimate yield. Figure 12 shows a simplified simulation testbench utilized for the design verification process.

3.2. Track-and-Hold Performance

Three sampling switch topologies were evaluated: NMOS, CMOS, and bootstrapped. The bootstrapped switch demonstrated the best linearity, achieving a total harmonic distortion (THD) of −43 dB.

Table 1. THD comparison of sampling topologies at the Nyquist input (Fs = 810 MHz, tt@60 °C).

Sampler Topology	THD (dB)
Ideal	−66
NMOS	−12
CMOS	−31
Bootstrapped	−43

details the difference in THD performance for a variety of sampler topologies.

3.3. Comparator Performance

The StrongArm latch comparator exhibited a propagation delay of less than 60 ps for a 100 µV input at worst-case corners. The input-referred noise was below 500 µV, well within the LSB of the six-bit converter. In Figure 13, the process corners with their given temperatures are used in the figure legend, with ff, ss, and tt representing the speed of a PMOS or an NMOS transistor (fast—f; slow—s; typical—t) in terms of expected model parameters.

3.4. Spectral Performance

FFT-based analysis was used to evaluate dynamic performance. The converter achieved a SINAD of approximately 38 dB at the Nyquist input, corresponding to an ENOB of 6.1 bits. Figure 14 and Figure 15 demonstrate the simulated results for the spectral performance of the design.

3.5. Linearity and DC Response

The converter’s DC transfer function exhibited expected stair-step behavior. However, the integral and differential nonlinearity (INL/DNL) was higher than expected (shown in Figure 16), likely due to an artifact of the converter being designed for a smaller-than-average input range that has a common mode voltage that is set high when compared to standard $V_{DD}/2$ levels. The DC transfer characteristics visually support this observation with the stair-steps in Figure 17 at high-voltage amplitudes appearing considerably more defined than those at lower voltages. Additionally, Figure 17 shows signal distortion every three to four bits in the “stair-step” response, possibly due to every reset occurrence generating a small amount of noise in the DC transfer characteristic plot.

3.6. Monte Carlo Yield Estimation

Monte Carlo simulations with mismatch models and parasitic extraction showed that the converter met the ENOB target with one standard deviation margin, which is shown in Figure 18. The distribution was slightly leptokurtic, suggesting more samples would improve confidence. The Monte Carlo yield estimation was run with 1047 samples, with a standard deviation of 0.0726 dB.

3.7. Benchmarking

The design was benchmarked against state-of-the-art ADCs using the Walden figure of merit. It performed above average for its class, as shown in Figure 19.

3.7.1. Waldon Figure of Merit

To evaluate energy efficiency, the Walden Figure of Merit (FoM) is used, defined as follows:

$${\mathrm{FoM}}_{\mathrm{Walden}}={\displaystyle \frac{P}{2^{\mathrm{ENOB}}·f_s}}$$

(1)

where P is the power consumption, $f_s$ is the sampling frequency, and ENOB is the effective number of bits. This metric, introduced by Walden [14], enables comparison across ADCs with varying resolutions and speeds. Lower values indicate better energy efficiency.

In this work, the ADC achieves a FoM of 42 fJ/conversion step, which is competitive with state-of-the-art designs in similar technology nodes.

3.7.2. Schreier Figure of Merit

In addition to the Walden FoM, the Schreier Figure of Merit provides a logarithmic measure of ADC efficiency, defined as follows:

$${\mathrm{FoM}}_{Schreier}=\mathrm{SNDR}+10{log}_{10}\left({\displaystyle \frac{f_s}{P}}\right)$$

(2)

where $f_s$ is the sampling frequency, P is the power consumption, and SNDR is the signal-to-noise-and-distortion ratio, approximated as $6.02\times \mathrm{ENOB}+1.76$. Using an ENOB of 5.5 and a power consumption of 1539 µW, the Schreier FoM is calculated and is as follows:

$${\mathrm{FoM}}_{Schreier}=152.08\mathrm{dB}$$

This value reflects a strong balance between resolution, speed, and power and suggests competitiveness with other ADCs in similar technology nodes [15]. Figure 20 details this design as compared to others utilizing the Schreier FoM with this design represented by the red star.

3.7.3. Performance Summary

To contextualize the performance of the proposed ADC,

Table 2. Performance summary and comparison with prior work.

Metric	This Work	[9]	[10]
Technology	22FDX FD-SOI	90 nm CMOS	65 nm CMOS
Resolution (bits)	6	10	8
Sampling Rate (MS/s)	810	50	500
ENOB (bits)	5.5	8.6	7.2
Power (µW)	1539	900	600
FoMW (fJ/conv-step)	42	46	68
FoMS (dB)	152.08	160.81	164.17
Results	Simulated	Experimental	Simulated

summarizes key metrics and compares them with representative designs from the literature. The converter achieves competitive dynamic performance while maintaining a compact layout and low power consumption, making it suitable for integration into time-interleaved SerDes front-ends. The power performance for this work relates to the total simulated power for post-layout extraction simulation with reference to Figure 9. Comparing the FoMs, this ADC design shows a better Walden FoM since it utilizes a higher sampling rate while exhibiting a lower Schreier FoM, since its ENOB is considerably lower with the higher power draw.

4. Discussion

The presented SAR ADC demonstrates a compelling balance between performance, area, and power efficiency, particularly in the context of time-interleaved architectures for high-speed wireline communication. The simulated effective number of bits (ENOB) of approximately 6.1 and SINAD of 38 dB align well with the design target derived from system-level modeling using the COM methodology [16]. This confirms the hypothesis that moderate-resolution ADCs, when interleaved and digitally equalized, can meet the demands of modern SerDes links operating at 100 Gb/s and beyond. Compared to prior work, such as the architectural models in [16], this design achieves competitive performance while occupying a smaller footprint, enabled by the use of 22FDX FD-SOI technology.

The bootstrapped switch topology significantly improved linearity over traditional CMOS and NMOS switches, validating prior findings by Dessouky and Kaiser [8]. However, the observed INL and DNL deviations suggest that further refinement of the DAC layout and common-mode control is necessary. These non-idealities, while not dominant in dynamic performance, could limit calibration-free operation in precision applications.

Monte Carlo simulations revealed that the design is robust to mismatch and process variation, though the kurtosis of the ENOB distribution indicates that additional statistical sampling or layout symmetry may be beneficial in future iterations. The asynchronous SAR logic proved effective in reducing timing margin constraints, supporting the use of event-driven architectures in deeply scaled CMOS.

In the broader context, this work supports the trend toward digital-centric ADC architectures that leverage process scaling and digital calibration to overcome analog limitations. The results reinforce the viability of SAR ADCs in high-speed, low-power applications, particularly when arrayed in time-interleaved configurations.

4.1. Scalability and Limitations

The architecture presented here is inherently scalable to higher sampling rates through time-interleaving. However, increasing the number of interleaved channels introduces challenges such as clock skew, gain mismatch, and increased input capacitance. While the asynchronous SAR logic simplifies timing, future designs will require robust digital calibration to maintain linearity and dynamic range across channels.

One limitation of the current implementation is the lack of on-chip calibration or background correction for static errors. Additionally, the relatively high common-mode voltage used in the DAC may contribute to the observed INL/DNL degradation. These issues can be addressed in future revisions through improved biasing schemes and layout symmetry.

4.2. Future Work

Future research should focus on the following:

• Implementing digital background calibration for gain and offset mismatch across interleaved channels.
• Exploring monotonic or set-and-down switching schemes to further reduce DAC energy and improve linearity [9,10].
• Enhancing ESD protection without compromising analog performance, potentially through custom RF-tuned clamps.
• Investigating the use of machine learning for adaptive calibration and performance prediction across PVT corners.

These directions aim to improve the converter’s scalability and integration into next-generation SerDes and AI accelerator platforms.

5. Conclusions

This work presents the design, simulation, and analysis of a six-bit asynchronous SAR ADC implemented in GlobalFoundries’ 22FDX FD-SOI CMOS technology, optimized for integration into time-interleaved architectures targeting high-speed wireline communication systems. The converter achieves a simulated ENOB of 6.1 bits and a SINAD of 38 dB at the Nyquist input, validating the system-level modeling approach used to derive its specifications.

Key design features include a bootstrapped track-and-hold switch for improved linearity, a StrongArm latch comparator with sub-60 ps delay, and a split capacitive DAC with energy-efficient switching. The asynchronous SAR logic enables adaptive timing and reduces clock distribution complexity, which is particularly advantageous in interleaved systems.

Simulation results confirm the converter’s robustness across PVT corners and process mismatch, with Monte Carlo analysis indicating high yield. While static linearity metrics such as INL and DNL require further optimization, the dynamic performance meets the requirements for ADC-based SerDes front-ends operating at 100 Gb/s and beyond.

The design demonstrates the viability of FD-SOI technology for mixed-signal applications. Benchmarking against state-of-the-art designs shows that this converter achieves competitive performance with a compact footprint and low power consumption.

In summary, this SAR ADC contributes to the growing body of work supporting digitally assisted, interleaved ADC architectures for next-generation communication systems. Future work will focus on improving linearity, implementing digital calibration, and exploring advanced switching schemes to further enhance performance and scalability, with the aim of moving the red star in Figure 19 lower on the y-axis, decreasing the FoM.