Optimised Extension of an Ultra-Low-Power RISC-V Processor to Support Lightweight Neural Network Models

Abstract

With the increasing demand for efficient deep learning models in resource-constrained environments, Binary Neural Networks (BNNs) have emerged as a promising solution due to their ability to significantly reduce computational complexity while maintaining accuracy. Their integration into embedded and edge computing systems is essential for enabling real-time AI applications in areas such as autonomous systems, industrial automation, and intelligent security. Deploying BNN on FPGA using RISC-V, rather than directly deploying the model on FPGA, sacrifices detection speed but, in general, reduces power consumption and on-chip resource usage. The AI-extended RISC-V core is capable of handling tasks beyond BNN inference, providing greater flexibility. This work utilises the lightweight Zero-Riscy core to deploy a BNN on FPGA. Three custom instructions are proposed for convolution, pooling, and fully connected layers, integrating XNOR, POPCOUNT, and threshold operations. This reduces the number of instructions required per task, thereby decreasing the frequency of interactions between Zero-Riscy and the instruction memory. The proposed solution is evaluated on two case studies: MNIST dataset classification and an intrusion detection system (IDS) for in-vehicle networks. The results show that for MNIST inference, the hardware resources required are only 9% of those used by state-of-the-art solutions, though with a slight reduction in speed. For IDS-based inference, power consumption is reduced to just 13% of the original, while resource usage is only 20% of the original. Although some speed is sacrificed, the system still meets real-time monitoring requirements.

1. Introduction

Deep learning has been widely adopted across various domains, including embedded systems, industrial automation, and edge computing applications [1]. However, conventional deep neural networks (DNNs) require significant computational power, memory bandwidth, and energy resources, making their deployment challenging in resource-constrained environments [2]. Edge devices and embedded systems often have strict limitations on power consumption and available hardware resources, necessitating more efficient solutions for neural network inference [3].

To address these constraints, BNNs have been explored as a promising alternative. By binarising both weights and activations to 1-bit precision, BNNs eliminate the need for floating-point multiplications and instead rely on efficient XNOR and POPCOUNT operations [4]. These operations significantly reduce computational complexity, memory access, and power consumption, making BNNs well suited for resource-limited hardware platforms such as FPGAs and embedded processors [5]. While BNNs can achieve competitive accuracy in various applications, their deployment requires a suitable hardware architecture that fully utilises their computational efficiency [6].

Among the available hardware architectures, RISC-V has emerged as a flexible and power-efficient solution for deploying deep learning models in embedded environments [7]. Unlike proprietary ISAs, the open-source RISC-V ISA allows for custom instruction extensions, enabling designers to optimise hardware for specific workloads [8]. This capability is particularly beneficial for BNN inference, where dedicated instructions can streamline key operations such as binary convolution, pooling, and activation functions, reducing instruction overhead, memory access latency, and execution cycles [9]. The flexibility of RISC-V has been demonstrated in various low-power AI accelerators, where customised processing pipelines have significantly improved power efficiency compared with other general-purpose processors [10]. For example, Zero-Riscy, a lightweight 32-bit RISC-V implementation featuring architectural modifications, achieves lower power consumption and enhanced instruction execution efficiency, enabling a more optimised deployment of BNNs [11].

Integrating BNN inference within a RISC-V core provides additional advantages beyond domain-specific hardware acceleration. Unlike traditional FPGA-based deep learning accelerators that rely solely on dedicated processing units, an FPGA-deployed RISC-V processor can execute BNN inference while simultaneously handling other instructions, eliminating the need for an additional processing unit [12]. This hybrid capability has been shown to enhance real-time AI applications, particularly in scenarios requiring dynamic task execution alongside deep learning inference [13].

Deploying a RISC-V processor on an FPGA for BNN inference offers a practical and effective approach to achieving cost- and energy-efficient deep learning acceleration [14]. Moreover, the adaptability of RISC-V-based architectures, combined with FPGA-based implementations, enables continuous refinement to ensure compatibility with evolving AI workloads while maintaining power and resource efficiency [15].

This work presents a low-cost, energy-efficient RISC-V processor based on Zero-Riscy, specifically designed to accelerate BNN inference. This design is implemented and validated on a cost-effective FPGA platform, prioritising resource and energy efficiency, while meeting the real-time performance requirements of practical applications rather than emphasising maximum inference speed. Although further performance enhancements, such as increasing pipeline stages or utilising cache memory, could improve inference speed, a trade-off was applied to prioritise low resource and energy consumption. This approach ensures suitability for BNN applications while avoiding unnecessary speed-ups. Three custom instructions are introduced for convolution, pooling, and fully connected layers, optimising execution efficiency without adding substantial resource overhead relative to the baseline processor.

Key contributions of the paper include the following:

• A RISC-V processor optimised for BNN inference that embeds custom instructions to accelerate key layers while minimising hardware cost.
• Extensive validation through two case studies, one on MNIST dataset classification and another on an automotive in-vehicle network intrusion detection system, demonstrating efficiency across diverse workloads.
• A comprehensive comparison and analysis of the implementations, which reveal a power-efficient, resource-aware design suited for edge AI applications. The design significantly reduces on-chip resource usage and power consumption compared with existing FPGA-based solutions, all while maintaining real-time performance.

The rest of this paper is structured as follows. Section 2 introduces the background and key techniques underlying the processor architecture. Section 3 details the hardware implementation. Section 4 presents experimental results on the MNIST and CAN bus datasets, comparing performance with alternative designs. Finally, Section 5 concludes with key findings and outlines future research directions.

2. Background and Related Works

This section provides the fundamental knowledge and technical background for constructing the proposed RISC-V-based low-cost hardware acceleration solution for BNN inference. It covers the principles of BNNs, highlights the advantages of implementing low-cost neural network inference on RISC-V, and introduces Zero-Riscy, a minimalistic RISC-V processor.

2.1. Binary Neural Networks

DNNs have achieved remarkable success in various applications, but their high computational cost and memory requirements limit their deployment on resource-constrained devices. BNNs mitigate this challenge by reducing weights and activations to just two states, +1 and −1, replacing computationally expensive floating-point operations with efficient bitwise logic. This significantly reduces power consumption and computational and storage requirements [16]. Given a weight matrix W and an input activation X, BNNs approximate the standard matrix multiplication as:

$$Y=sign\left(X\right)·sign\left(W\right)$$

(1)

where $sign(·)$ binarises the inputs to $\pm 1$, allowing inference to be performed using XNOR and POPCOUNT operations instead of traditional multiplications [17]:

$$X·W=POPCOUNT\left(XNOR\right(X,W\left)\right)$$

(2)

In addition to significantly reducing inference computational complexity through highly parallelisable bitwise operations, BNNs achieve up to 32× memory compression compared with full-precision DNNs [16,18]. However, the aggressive quantisation introduces accuracy degradation due to the loss of representational capacity. To mitigate this, techniques like real-valued scaling factors, gradient approximation via Straight-Through Estimator (STE), and hybrid quantisation have been explored to balance efficiency and accuracy [19].

Due to their efficiency benefits, BNNs are well suited for edge computing and embedded AI applications, especially when deployed on an AI-enhanced processor. Open-source RISC-V architectures have gained prominence in domain-specific acceleration due to their flexibility in hardware customisation. Recent advancements include custom instructions for various domain-specific operations, reducing instruction overhead and enhancing execution efficiency on RISC-V-based FPGA accelerators [5]. Integrating these optimisations enables real-time inference while maintaining minimal power consumption.

As BNN research advances, improvements in training algorithms, hardware-aware quantisation, and specialised instruction sets are bridging the gap between power-efficient inference and competitive accuracy. The convergence of BNNs and RISC-V architectures is driving the development of ultra-low-power, high-performance AI solutions for real-world applications, particularly in security-critical and autonomous embedded systems [5].

2.2. RISC-V Architecture

RISC-V has rapidly emerged as a competitive alternative to proprietary instruction set architectures (ISAs), offering a fully open, modular, and scalable framework suited for a wide range of computing applications. Unlike x86 and ARM, which are tightly controlled by industry giants, RISC-V’s open-source nature allows for extensive hardware customisation, making it particularly well suited for AI acceleration and deep-learning inference on embedded and edge devices [20]. Its simplicity and efficiency, combined with rapidly growing industry support, have driven its adoption in low-power AI computing.

The architecture’s reduced instruction set computing (RISC) design allows for streamlined instruction execution, leading to higher efficiency in processing vectorised and parallel workloads. AI inference, particularly neural network acceleration, benefits from RISC-V’s extensible vector processing capabilities. The RISC-V Vector Extension (RVV) enables hardware-accelerated tensor operations by processing multiple data points in parallel, significantly boosting the throughput of convolutional and fully connected layers in deep learning models [20]. Compared with traditional scalar architectures, RISC-V vector units provide higher computational density with lower power consumption, making them ideal for low-energy AI accelerators and embedded neural networks.

With the rise of quantised neural networks (QNNs) and energy-efficient AI models, RISC-V has proven particularly effective in handling low-precision arithmetic. The support for sub-byte data types, including int4, int8, and float16, allows for efficient deep-learning inference with reduced memory bandwidth and computation overhead [5]. This capability is crucial in resource-constrained environments where power efficiency is as important as computational performance. Additionally, hardware implementations of RISC-V-based AI accelerators, such as those integrating systolic array architectures or in-memory computing techniques, have demonstrated significant gains in throughput and efficiency [14].

RISC-V’s capability to integrate vector processing, mixed-precision support, and modular extensions makes it a strong candidate for efficient AI acceleration, particularly in edge computing and embedded systems where power and cost constraints are critical [14].

2.3. Zero-Riscy: A Lightweight and Ultra-Low Power RISC-V Processor

Zero-Riscy [21] is a 32-bit RISC-V processor core developed as part of the PULP (Parallel Ultra-Low-Power) platform at ETH Zurich. The design goal of Zero-Riscy is to provide an efficient computing solution for resource-constrained embedded devices, making it particularly well suited for applications in IoT, sensor nodes, and wearable devices [22]. Zero-Riscy employs a simplified two-stage pipeline architecture consisting of the Instruction Fetch (IF) and Execute (EX) stages. This design prioritises reducing pipeline stalls and improving energy efficiency while maintaining sufficient computational capacity to support typical embedded applications. The structure of Zero-Riscy, including its two pipeline stages, is illustrated in Figure 1.

Additionally, Zero-Riscy supports hardware interrupts, low-power modes, and clock gating, enabling efficient operation across various application scenarios. For instance, in a sensor network, Zero-Riscy can wake up and execute data processing tasks upon detecting a sensor event, then enter a low-power mode until the next event occurs.

3. Proposed Ultra-Low-Power RISC-V Processor with BNN Support

This section introduces our novel ultra-low-power RISC-V processor, optimised for lightweight neural network inference. The hardware design is first introduced, followed by the integration of three custom instructions for BNN acceleration.

3.1. Zero-Riscy with the Proposed BNN Unit

Using an RISC-V processor to implement the inference phase of binarised neural networks is a more flexible approach compared with directly deploying BNNs on FPGAs with frameworks such as Xilinx FINN. This allows RISC-V to be used for both standard applications and neural network tasks without dedicating any additional area specifically for neural network operations. RISC-V is an open-source ISA that can be customised for specific applications. Developers can add custom instructions to optimise specific neural network operations, providing valuable flexibility during the development and debugging phases. This allows for easy code modification and algorithm updates.

This study aims to implement the fully binarised neural network inference phase using Zero-Riscy. Given the large computational workload and high data reuse, three custom instructions are introduced for acceleration. These instructions are specifically designed for the convolutional layer, max pooling layer, and fully connected layer. The functionality supporting these instructions is encapsulated within the BNN unit. The structure of Zero-Riscy, incorporating the BNN unit, is shown in Figure 2. Since the custom instructions require multiple lines of input data, three dedicated output ports were added to the register file to efficiently transfer all necessary data to the BNN unit within a single instruction. These output ports exclusively serve the BNN unit, ensuring they do not interfere with other functions within Zero-Riscy.

3.2. Proposed Custom Instructions

The proposed custom instructions are tailored for the convolutional, pooling, and fully connected layers in the BNN model. The convolutional layer and fully connected layer combine sliding window, XNOR, POPCOUNT, thresholding, and accumulation into a single instruction, though they differ in their implementation. Details of these approaches will be discussed in the following paragraphs. The custom instruction for max pooling incorporates a sliding window and OR operations to efficiently compute the maximum value matrix. The format of these three custom instructions is presented in

Table 1. Encoding of proposed custom instructions for BNN acceleration in Zero-Riscy processor.

	31:25	24:20	19:15	14:12	11:7	6:0
CONV	funct7 (0000000)	rs2	rs1	funct3 (011)	rd	op (1111011)
Max Pooling	funct7 (0000000)	rs2	rs1	funct3 (100)	rd	op (1111011)
FC	funct7 (0000000)	rs2	rs1	funct3 (101)	rd	op (1111011)

. This design maximises data reuse, enhances computational parallelism, and improves overall efficiency.

The custom convolutional instruction integrates sliding window, XNOR, POPCOUNT, accumulation, and thresholding operations. This integration increases the utilisation of a single instruction, reduces the total number of instructions needed, and enhances the reuse of weights. The operation of the proposed binarised convolutional instruction is illustrated in Figure 3. In this example, the filter window size is $3\times 3$, meaning each input feature map (IFM) corresponds to a 9-bit weight and a threshold in a node. The convolutional operation involves extracting each 9-bit data segment from the IFM using the filter window and performing an XNOR operation with the corresponding weight. The result is then processed using a POPCOUNT to count the number of ones, which is stored in an intermediate matrix. Once all IFMs corresponding to a node have been processed, the POPCOUNT results stored in the intermediate matrix are summed. The final value is compared with the threshold: if it is greater than or equal to the threshold, the corresponding position in the output feature map (OFM) is set to 1; otherwise, it is set to 0.

The input to the max pooling layer comes from the previous convolution layer. For instance, with a max pooling window of size 2 × 2 and no padding, the operation reduces the input dimensions by half. The primary function of this layer is to select the maximum value within the window. Given that the elements in the matrix are binary (0 or 1), the output will be 1 if at least one element in the window is 1; otherwise, it remains 0. As a result, binary max pooling can be simplified to an OR operation across the four elements within the window. The window moves with a stride of 2, ensuring non-overlapping pooling regions. The custom max pooling instruction takes two consecutive rows of the input matrix and generates a single output row with dimensions reduced by half, storing the results in the designated memory location.

The main operation of the fully connected layer involves performing an XNOR operation between the input and the weights, followed by a POPCOUNT on the results. Since the fully connected layer is the final stage of the model, its input comes from the output of the preceding max pooling layer. In our example, this output is a 5 × 5 matrix. The 5 × 5 matrix is stored in five consecutive bytes, with the lower 5 bits of each byte holding a row of matrix data, while the upper 3 bits are padded with 0s. Similarly, the weights are stored in the lower 5 bits of consecutive bytes, but the upper 3 bits are set to 1s. This padding ensures correct computation because if the upper bits of both the input and the weights were 0, their XNOR result would be 1, incorrectly increasing the POPCOUNT value by 3. The operation of the fully connected layer is illustrated in Figure 4.

4. Experimental Results

In this study, we conducted two experiments. The first experiment involved handwritten Arabic numeral classification using a BNN model trained on the grayscale MNIST dataset. The BNN model was trained and evaluated using Larq. The second experiment focused on an automotive intrusion detection system (IDS) model trained on the Car-Hacking dataset. The Car-Hacking data used in this evaluation are sourced from [24], while the IDS model is based on [25]. This experiment specifically assessed the deployment of the model on the proposed low-power RISC-V processor to evaluate its performance and efficiency.

The target device in this study is the ZedBoard, a development platform equipped with a Xilinx Zynq-7000 SoC. This SoC combines a dual-core ARM Cortex-A9 processor with programmable logic, offering a versatile solution for FPGA-based system development. The ZedBoard provides a balance between performance, flexibility, and cost-effectiveness, making it well suited for prototyping embedded systems and hardware-accelerated designs.

4.1. BNN Inference on the MNIST Dataset Using the Proposed RISC-V Processor

The MNIST dataset is a widely used benchmark for handwritten digit recognition, containing 70,000 grayscale images (60,000 for training and 10,000 for testing). Each image is a 28 × 28-pixel representation of a handwritten digit (0–9) [26]. Originally introduced by LeCun et al., MNIST provides a structured and standardised dataset that has become a fundamental testbed for evaluating neural network architectures, feature extraction techniques, and hardware acceleration strategies [27]. While modern deep learning models have significantly surpassed human-level performance on MNIST, the dataset remains a key reference for network optimisation, quantised inference, and low-power AI applications [28].

This case study utilises a BNN model trained with Larq, where the MNIST dataset is binarised at an early stage of training. The model consists of multiple convolutional layers, pooling layers, batch normalisation layers, and fully connected layers, totalling 93.6 k parameters and achieving 97.62% accuracy. The architecture is illustrated in Figure 5. The parameters of the BNN model trained with Larq are transferred to the Xilinx Vitis environment, synthesised, and implemented by Xilinx Vitis HLS 2022. When implemented on the target device Zedboard, the system operates at 66 MHz and a temperature of 28.4 °C, with a dynamic power consumption of 0.187 W and a static power consumption of 0.107 W, resulting in a total power consumption of only 0.294 W, as shown in Figure 6. The comparison between the number of basic instructions required to complete one MNIST classification task before using the proposed instructions and the number of instructions required after optimisation is shown in

Table 2. Instruction cycles for MNIST dataset classification.

Normal Instruction Cycles	Proposed Instruction Cycles
135,551	20,276 (↓ 85.1%)

. The total number of instructions has been reduced by 85.1%.

Figure 7 presents a comparison of FPGA-based MNIST accelerators in terms of inference time, power consumption, and resource utilisation. Prior works [29,30,31] have focused on optimising throughput using parallel pipelines, floating-point computation, and memory-efficient architectures, achieving low latency at the expense of high DSP and LUT utilisation.

The accelerator in [29] operates at 200 MHz, using a multi-channel pipeline to achieve a 25.9 µs inference time but consuming 242 DSPs and over 130 k LUTs, making it resource-intensive. In [30], inference time is further reduced to 25.4 µs by incorporating floating-point operations with line buffering; however, this approach demands 638 DSPs, limiting its feasibility for edge computing. Meanwhile, ref. [31] prioritises memory efficiency by employing fixed-point computation and utilising 3.38 Mb of BRAM, reducing logic usage but increasing inference time to 151 µs.

Our approach adopts a different strategy, prioritising hardware efficiency over raw throughput. Directly comparing the inference time of processors running at different frequencies can be misleading. To address this, we employ a normalised time method, defined by the following formula:

$$\mathrm{Normalised}\mathrm{time}={\displaystyle \frac{\mathrm{Actual}\mathrm{time}}{\mathrm{Clock}\mathrm{cycle}}}$$

(3)

where “Actual time” refers to the duration required to execute a task, and “Clock cycle” is calculated as 1/Processor frequency.

The normalized times calculated for [29,30,31] and this work are 5180, 3810, 25,066, and 25,075.2, respectively. Compared with other FPGA-based implementations of MNIST neural network inference, our proposed method significantly reduces hardware overhead, consuming only 9% of the power required by [30] while also eliminating the need for a large number of DSP units. However, this reduced hardware footprint results in an increased inference time, with a normalised execution time approximately eight times longer than [30], but nearly equivalent to [31], which also does not rely on DSP units. Despite this tradeoff, our method achieves an accuracy of 97.62%, making it a scalable and power-efficient solution for embedded AI applications. Despite its lower performance, our ultra-lightweight and power-efficient approach still meets the real-time requirements of many edge-AI applications, providing a resource-efficient solution for real-world problems.

4.2. Implementing a Low-Cost IDS for In-Vehicle Networks Using BNN

The increasing number of sensors used in smart vehicles has significantly raised concerns about in-vehicle network security. The machine learning (ML)-based Intrusion Detection System (IDS) designed for the Controller Area Network (CAN) protocol has gained significant popularity due to its excellent performance in detecting attacks without introducing additional overhead [32].

4.2.1. CAN Bus Message

The CAN is a serial communication protocol developed by Bosch in the 1980s for automotive and industrial automation applications. Due to its low cost, it has become a widely adopted standard [33]. However, despite its emphasis on reliability during design, the lack of encryption or any authentication mechanisms in the CAN protocol has led to significant security vulnerabilities [34]. For instance, security researchers have demonstrated remote control of a Jeep Cherokee, manipulating critical systems such as the steering and braking system [35].

To address these security concerns, various defensive measures have been proposed, including ECU authentication [36] and hardware-enforced isolation [37]. IDSs have received widespread attention as an effective approach, as they do not introduce additional overhead to the CAN bus.

Unlike traditional point-to-point communication methods, the CAN bus is a multi-master system that allows multiple nodes to exchange data on the same bus. In a CAN bus system, data are transmitted in the form of frames, each consisting of several parts: Start of Frame (SOF), CAN ID, control bits, Remote Transmission Request (RTR), data field, Cyclic Redundancy Check (CRC), acknowledgement (ACK) field, and End of Frame (EOF). The CAN ID determines the priority of the data and their transmission target, while the data field contains the actual information being transmitted. There are two frame types, standard and extended, differentiated by identifier length: 11 bits for standard frames and 29 bits for extended frames [12]. The structure of a CAN message is illustrated in Figure 8.

The CAN bus uses priority-based arbitration to resolve access conflicts, ensuring the messages with the lowest identifier transmit first. This mechanism guarantees the timely delivery of critical data and optimises bus utilisation. It also features robust error detection and correction, including bit monitoring, bit stuffing, format checking, and cyclic redundancy check (CRC) validation, to ensure reliable data transmission. Additionally, faulty nodes are automatically isolated to prevent network disruption.

Reference [38] outlines several common attack methods. A Denial of Service (DoS) attack floods the bus with high-priority intrusive messages, delaying or blocking legitimate communication. Fuzzing attacks involve a malicious node randomly generating and sending messages with different CAN IDs to disrupt normal operations. Spoofing attacks specifically target certain CAN IDs, such as forging RPM or gear position data, potentially misleading drivers and compromising driving safety.

4.2.2. Model Structure and Performance

A promising FPGA-based IDS using BNN implements a two-stage Coarse-to-Fine (C2F) architecture [38], where a lightweight model initially detects potential intrusions, triggering a fine-grained model only when necessary. The structure of the C2F model is shown in Figure 9. The model’s architecture and parameters are identical to those in [39]. Therefore, the model’s accuracy, precision, and F1 score in this study remain consistent with the original work.

Table 3. Detection performance comparison of the Coarse model with state-of-the-art approaches.

Model	Accuracy (%)	Precision (%)	Recall (%)	F1 (%)
ACGAN [40]	-	99.23	99.24	99.23
DCNN [24]	99.94	99.98	99.87	99.92
CAAE [41]	99.90	99.97	99.72	99.84
CANTransfer [42]	99.37	94.84	95.57	95.25
MTH-IDS [43]	99.99	99.99	99.99	99.99
QMLP [12]	99.96	99.91	99.92	99.91
Coarse [39]	99.83	99.88	99.64	99.76

presents a performance comparison of the Coarse model, a binary classification model within the C2F framework. The CANTransfer model achieves the lowest accuracy due to its use of a newly developed dataset tailored for novel attacks. In contrast, the other models achieve accuracy, precision, recall, and F1 scores exceeding 99%, with variations of less than 1%.

4.2.3. Resource Utilisation and Power Consumption

The inference time for the Coarse model on Zero-Riscy was measured at 13.37 ms using Vivado’s behavioural simulation. Since the model requires assembling CAN IDs from 30 consecutive CAN messages to form a 2D array as input, real-time detection requires completing inference within the delay introduced by these 30 CAN messages. Based on the CAN message period statistics in the CH dataset [25], summarised in

Table 4. CAN message transmission periods for each sub-dataset in the CH dataset.

Dataset	Attack	Mean (ms)	Standard Deviation (ms)
CH [25]	Normal	0.512	0.712
	DoS	0.767	1.446
	Fuzzy	0.768	1.465
	Spoofing RPM	0.547	0.896
	Spoofing gear	0.527	0.889

, the input delay for the normal dataset is calculated as 30 × 0.512 = 15.36 ms. Since this delay is greater than the inference time achieved with Zero-Riscy, the study meets the requirements for real-time detection. However, the model can only determine which CAN ID data block contains an attack, without pinpointing the specific CAN ID within the block that is under attack.

In addition to the Zero-Riscy processor, the instruction and data memory required for model implementation are realised using BRAM IP blocks in Vivado. The resource utilisation and power consumption of this study, compared with the QMLP and original C2F implementations, are shown in Figure 10. The proposed approach significantly reduces both resource usage and power consumption compared with these methods. Specifically, QMLP consumes 11 times the LUTs used in this study, while C2F consumes 6 times as many. The flip-flop (FF) usage in this study is less than 5% of that in both QMLP and C2F. DSP resources are not required for model inference. The single DSP utilised in this study is due to the multiplication module inherently present in Zero-Riscy. Since the model and computational methods used in this study are identical to those in C2F, the intermediate values generated during computation remain the same. However, the BRAM usage in this study is only one-third of that in C2F. This reduction is due to the parallelism employed in C2F [39], where multiple intermediate results from different layers are stored in the data memory simultaneously. Figure 11 illustrates the implementation of this study on the Zynq SoC of the ZedBoard, with the utilised resources highlighted in blue.

By utilising BNNs in this study, multiplications are replaced with XNOR and POPCOUNT operations, and the computation order is optimised. As a result, the number of instructions required to complete an IDS detection task is also significantly reduced. The comparison between the number of basic instructions required to complete one IDS detection task before using the proposed instructions and the number required after optimisation is shown in

Table 5. Instruction cycles for IDS detection task.

Normal Instruction Cycles	Proposed Instruction Cycles
864.6 k	88.3 k (↓ 89.8%)

. The total number of instructions has been reduced by 89.8%.

As mentioned in the previous case study, the system operates at 65 MHz, with a dynamic power consumption of 0.187 W and a static power consumption of 0.107 W, resulting in a total power consumption of only 0.294 W, which is less than 13% of the power consumption in the original C2F implementation. The low power consumption and resource utilisation of the enhanced RISC-V processor make it feasible to deploy IDS systems across multiple critical ECUs. Figure 12 illustrates the interfaces and functionalities of a distributed IDS.

5. Conclusions

This paper proposes deploying an ultra-low-power RISC-V processor to support lightweight neural network models, utilising BNNs to simplify complex matrix operations into 1-bit XNOR and POPCOUNT operations, significantly reducing computational costs. The proposed BNN unit is integrated into the lightweight Zero-Riscy processor with a two-stage pipeline, ensuring efficient instruction execution.

To further optimise performance, three custom instructions are introduced, enabling 29 XNOR and POPCOUNT operations per data fetch without impacting Zero-Riscy’s critical path or operating frequency. These enhancements lead to substantial savings in power and hardware resources, with experiments demonstrating that the proposed design achieves over 80% hardware resource reduction while maintaining 97.62% accuracy in FPGA-based MNIST BNN inference. The proposed method consumes only 13% of the power and 20% of the hardware resources compared with state-of-the-art IDS implementations. Despite an increase in inference time, the approach meets real-time detection requirements, making it ideal for automotive intrusion detection, where timely attack detection on the CAN bus is crucial for vehicle security. By integrating this IDS within ECUs, vehicles can efficiently identify and mitigate attacks with minimal computational overhead, providing a practical and energy-efficient solution for modern automotive security systems. Future work will explore multi-core collaboration and in-memory computing to further enhance real-time detection capabilities.