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State-of-the-Art Power Factor Correction: An Industry Perspective
 
 
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Correction to Encyclopedia 2024, 4(3), 1324-1354.
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Correction

Correction: Adragna et al. State-of-the-Art Power Factor Correction: An Industry Perspective. Encyclopedia 2024, 4, 1324–1354

by
Claudio Adragna
1,*,
Alberto Bianco
2,
Giovanni Gritti
1 and
Matteo Sucameli
1
1
STMicroelectronics, 20864 Agrate Brianza, Italy
2
STMicroelectronics, 11100 Aosta, Italy
*
Author to whom correspondence should be addressed.
Encyclopedia 2025, 5(2), 69; https://doi.org/10.3390/encyclopedia5020069
Submission received: 8 May 2025 / Accepted: 13 May 2025 / Published: 23 May 2025
(This article belongs to the Collection Encyclopedia of Engineering)
Browse Figures
Versions Notes
The authors would like to make the following corrections to the originally published paper [1].
In the original publication, due to an oversight, there was a repeated mistake in Figures 1, 6–10 and 12 as published. The input bridge should be rotated by 90 degrees counterclockwise. The corrected Figure 1, Figure 6, Figure 7, Figure 8, Figure 9, Figure 10 and Figure 12 appear below. The authors state that the scientific conclusions are unaffected. This correction was approved by the Academic Editor. The original publication has also been updated.

Reference

  1. Adragna, C.; Bianco, A.; Gritti, G.; Sucameli, M. State-of-the-Art Power Factor Correction: An Industry Perspective. Encyclopedia 2024, 4, 1324–1354. [Google Scholar] [CrossRef]
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Figure 1. Front-end of a typical SMPS and related key waveforms.
Figure 1. Front-end of a typical SMPS and related key waveforms.
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Figure 6. An LC rectifier and related key waveforms.
Figure 6. An LC rectifier and related key waveforms.
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Figure 7. A Valley Fill circuit and related key waveforms.
Figure 7. A Valley Fill circuit and related key waveforms.
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Figure 8. A line-frequency-commutated PFC system.
Figure 8. A line-frequency-commutated PFC system.
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Figure 9. Typical architectures of a power-factor-corrected SMPS: (a) with a non-isolated PFC; (b) with an isolated PFC.
Figure 9. Typical architectures of a power-factor-corrected SMPS: (a) with a non-isolated PFC; (b) with an isolated PFC.
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Figure 10. Single-stage power-factor-corrected SMPS for ripple-tolerant loads.
Figure 10. Single-stage power-factor-corrected SMPS for ripple-tolerant loads.
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Figure 12. Single-stage power-factor-corrected SMPS with fast control loop.
Figure 12. Single-stage power-factor-corrected SMPS with fast control loop.
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MDPI and ACS Style

Adragna, C.; Bianco, A.; Gritti, G.; Sucameli, M. Correction: Adragna et al. State-of-the-Art Power Factor Correction: An Industry Perspective. Encyclopedia 2024, 4, 1324–1354. Encyclopedia 2025, 5, 69. https://doi.org/10.3390/encyclopedia5020069

AMA Style

Adragna C, Bianco A, Gritti G, Sucameli M. Correction: Adragna et al. State-of-the-Art Power Factor Correction: An Industry Perspective. Encyclopedia 2024, 4, 1324–1354. Encyclopedia. 2025; 5(2):69. https://doi.org/10.3390/encyclopedia5020069

Chicago/Turabian Style

Adragna, Claudio, Alberto Bianco, Giovanni Gritti, and Matteo Sucameli. 2025. "Correction: Adragna et al. State-of-the-Art Power Factor Correction: An Industry Perspective. Encyclopedia 2024, 4, 1324–1354" Encyclopedia 5, no. 2: 69. https://doi.org/10.3390/encyclopedia5020069

APA Style

Adragna, C., Bianco, A., Gritti, G., & Sucameli, M. (2025). Correction: Adragna et al. State-of-the-Art Power Factor Correction: An Industry Perspective. Encyclopedia 2024, 4, 1324–1354. Encyclopedia, 5(2), 69. https://doi.org/10.3390/encyclopedia5020069

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