Operational Efficiency Underpinning Sustainable Nanofabrication ^†

Abstract

In light of sustainable development and the growing global emphasis on implementing green practices across all scientific sectors, the present work introduces a comprehensive framework with contemporary sustainability imperatives in nanofabrication cleanrooms. Recognizing the unique characteristics of cleanroom-based environments, which demand controlled conditions and strict procedures, the aim of the current work is to evaluate diverse nanofabrication scenarios with regard to their sustainability perspective with focus on operations at research- and pilot-line-level facilities.

1. Introduction

Focusing on the European Green Deal and the 17 Sustainable Development Goals (SDGs) proposed by the United Nations, as well as a significant increase in the need for more environmentally friendly research and technology, a new scientific culture has been created following green processes [1,2]. Sustainable development in nanoelectronics cleanrooms started to follow the example of other research laboratories which have already made initial steps towards their sustainable transition in a variety of scientific procedures.

Besides the restrictions of the nanoelectronics cleanrooms, there is still space to introduce a set of good practices in order to align research with the principles of environmental responsibility and adopt more eco-friendly methods for nanoelectronics fabrication [3]. Previous studies about cleanroom sustainability have been published, integrating novel lithographic techniques, Life Cycle Assessment (LCA), as well as adoption of sustainable nanofabrication routes in cleanrooom energy consumption [4,5,6,7].

Based on our previous work, we have introduced five targeted sustainability pillars, each of them revealing critical aspects of facility operations [8]. These five key pillars include: 1. the establishment of standardized operating protocols and working policies, 2. systematic tracking of the general-use consumables, 3. monitoring of materials, chemicals and wastes, 4. planning operations carefully to optimize infrastructure use and personnel effort and 5. procurement of dedicated equipment to address specific operational demands. These lay the ground for possible sustainable proposals which may allow the integration of greener alternatives into these high-precision environments.

Although cleanroom protocols (i.e., mandatory gowning procedures, material and equipment use for nanofabrication, etc.) may not change, there is still space for integrating sustainable alternatives into processes and smart infrastructure use. Therefore, the aim of our current study is to present the use case of RF MEMS development which has been analytically monitored in material and instrumentation utilization and depicted in preliminary different scenarios highlighting possible green alternatives. Analyzing the scenarios and always bearing in our mind our equipment capabilities at the Foundation for Research and Technology—Hellas (FORTH), we have identified which processes could be optimized or not. Considering the operational time, the number of the wafers and the noble metals use, we have arrived at some “good practices” proposals analytically presented in two different scenarios.

2. Two Different Scenarios of RF MEMS Fabrication: A Use Case About Sustainability

Considering what is mentioned above and the five sustainable pillars that we have defined, two different scenarios about RF MEMS fabrication are presented in this section. A detailed inventory with all the infrastructure, chemicals and materials used throughout RF MEMS fabrication steps has been established.

In conjunction with this, good cleanroom practices as well as smart planning have been integrated in our operational procedures to improve working and fabrication efficiency. Based on this framework, two different scenarios about RF MEMS production are developed: the first involves the RF MEMS fabrication using a single wafer (Figure 1) and a second scenario in which three wafers are used. In both cases, the steps followed remain identical ensuring consistency in the workflow.

2.1. First Scenario

In the first scenario (Figure 1), the full fabrication cycle of the RF MEMS devices [9] on a single wafer is completed over eight days, followed by a ninth day dedicated to the characterization focusing only on the device functionality.

The process starts on Day 1 with the lithographic patterning of the coplanar waveguides (CPWs) using an appropriate photoresist. This is followed by metal deposition for the CPW on the substrate by electron gun (e-gun) evaporation and subsequent photoresist lift-off on Day 2. On Day 3, a dielectric layer is deposited using plasma-enhanced chemical vapor deposition (PECVD). Furthermore, several process steps are performed overnight to minimize total fabrication time and reduce waiting time during standard working hours (see Figure 1). On Day 4, a second lithography step is conducted to pattern a hard mask on top of the dielectric layer, after which the undesired dielectric regions are removed via reactive-ion etching (RIE). Day 5 involves lithography for defining the sacrificial layer and on Day 6, the seed layer is deposited by e-gun evaporation, as well as lithography performed to define the bridge structure. Subsequently, on Day 7, the bridge is fabricated through gold electroplating, after which the photoresist is removed using appropriate solvents, and the exposed seed layer is removed through wet etching. An overnight process follows, preceding Day 8 that involves the wet etching of the sacrificial layer to release the movable bridge. Finally, on Day 9, device characterization is conducted to assess the functionality of the fabricated RF MEMS devices. If the devices meet the fundamental performance specifications, further additional characterization is performed over the next 2–5 days in order to identify critical performance metrics depending on the intended application requirements.

2.2. Second Scenario

In the second scenario, the complete fabrication process of the RF MEMS devices employing three wafers requires ten days, representing only a two-day increase compared to the single-wafer process. The eleventh day is also dedicated to the characterization of the devices focusing on their functionality. If the devices are functional, 2–5 more days are spent for additional characterization. In this scenario, three wafers are processed in parallel and/or sequential. More specifically, during the first three days, all wafers undergo identical processing steps simultaneously or in a row (those depicted in Figure 1). This approach cannot be continued throughout the fabrication period either because of our infrastructure capabilities or because of the specific nature of the corresponding processes.

Therefore, from Day 4 and onwards the wafers are treated in a serial approach (i.e., Day i for wafer 1 is Day i + 1 for wafer 2 and i + 2 for wafer 3). As a result wafer 1 is finalized on Day 8, similarly to the first scenario, whilst one more day is required for wafer 2 and another one for wafer 3. Finally, the characterization is sequentially performed, resulting in completion of the assessment on Day 11.

This well-structured processing schedule enhances overall resource efficiency by reducing both energy consumption and material usage. Energy savings are achieved through optimized equipment utilization, as the instrumentation operates once for the processing of three wafers rather than being used individually for each wafer. Similarly, material efficiency is improved due to lower cumulative consumption of gold per wafer when multiple wafers are processed in parallel within a single fabrication step.

It is particularly noteworthy that extending the fabrication period by only two additional days enables the simultaneous processing of three wafers, resulting in a threefold increase in device output compared to the single-wafer process. Moreover, focusing on the overall gold consumption we have calculated, considering typically utilized gold film thicknesses, in the first scenario, approximately 1.2 g of gold is consumed for the fabrication of roughly 1500 devices, while in the second scenario, around 1.6 g of gold is enough for delivering three times more devices.

3. Conclusions

As research in sustainable technologies progresses, further study in the field may allow the integration of more environmentally friendly alternatives into these high-precision environments such as nanofabrication cleanrooms without compromising scientific outcomes. The scenarios presented in this study highlight the importance and the necessity of adopting more sustainable approaches as well as a more versatile way of thinking and acting within nanofabrication cleanrooms, based on the example of RF MEMS fabrication. As a result, through smart planning, adding two (2) more working days leads to a threefold increase in the number of the fabricated devices, also accompanied by an estimated gold saving of approximately 2 g.

Beyond enhancing a culture of sustainability, it is essential to emphasize the real benefits associated with the integration of green practices and smart planning. These benefits include improved resource efficiency, reduced environmental impact and enhanced overall process optimization, all of which contribute to more responsible and economically viable fabrication strategies. In summary, this is what our study is trying to attain, within either a short or long timeframe.