An Improved DTC Scheme Based on Common-Mode Voltage Reduction for Three Level NPC Inverter in Induction Motor Drive Applications

Abstract

Common-mode voltage (CMV) is a critical concern in motor drive applications employing multilevel inverters, as it can lead to significant issues such as high-frequency noise, electromagnetic interference, and motor bearing degradation. These effects can compromise the reliability, reduce the operational lifespan of electric machines, and introduce safety hazards. In this study, an enhanced Direct Torque Control (DTC) strategy incorporating Space Vector Modulation (SVM) is proposed to specifically address CMV-related challenges in induction motors (IM) driven by a three-level Neutral-Point-Clamped (NPC) inverter. The proposed DTC scheme utilizes a specialized modulation technique that effectively mitigates CMV while also minimizing current harmonic content, and torque and flux ripples with a constant switching frequency. The developed SVM algorithm simplifies the three-level space vector representation into six equivalent two-level diagrams, enabling more efficient control. The zero-voltage vector is synthesized virtually by combining two active vectors within a two-level hexagonal structure. The effectiveness of the proposed DTC approach is validated through both simulation and Hardware-In-the-Loop (HIL) testing. Compared to the conventional DTC method, the proposed solution demonstrates superior performance in CMV minimization and leakage current reduction. Notably, it limits the CMV amplitude to V_dc/6, a significant improvement over the V_dc/2 typically observed with the standard DTC approach.

1. Introduction

The rapid advancements in science and technology, propelled by the repercussions of economic globalization, has led to increased demands in industrial manufacturing. Thus, a concurrent surge in the advancement of electric drive applications has been witnessed over the past decade [1]. The prevailing commercial electric drives are assembled from an electric machine and a power converter, which regulates the input power to fulfill the demands of the motor and achieve the desired speed, torque, and efficiency. Hence, the variable frequency drive market has focused on advancing both the converter and the electric machine, aiming to improve the overall efficiency of the drive system [2,3,4].

In most popular electric drives, the three-phase induction motor (IM) holds a dominant position when compared to other ac machines [5]. This is primarily attributed to its simple and plain conception, and regular maintenance-free operation. This has promoted the development of different control strategies for speed control such as the Direct Torque Control (DTC) approach. The latter enables precise and accurate managing of the IM performances.

Based on the literature, the main typical improvement approaches for Direct Torque Control (DTC) can be classified into two categories: modifications of Space Vector Modulation (SVM)-based DTC (DTC-SVM) and modifications of switching table-based DTC (ST-DTC). For the first category, several studies have employed the SVM technique in controlling two-level voltage inverters to enhance DTC performance [6,7,8,9,10]. For instance, in [6], an SVM-based DTC scheme was proposed for a two-level inverter supplying a five-phase induction motor drive, aiming to reduce common-mode voltage through the introduction of two virtual vectors. Similarly, in [7], a simplified DTC-SVM scheme for a two-level three-phase inverter-fed induction motor was introduced, offering reduced dependence on motor parameters by employing a single PI controller. Other researchers have focused on multilevel inverters due to their well-known advantages, including lower output voltage distortion, reduced switching stress, lower per-switch voltage ratings, and the availability of additional voltage vectors [11,12,13]. These characteristics effectively address several limitations of DTC-controlled induction machines. Representative works have targeted different objectives such as improving the dynamic performance and current profile [8,9], eliminating the impact of the xy component on output voltage space vectors [10], and reducing torque and flux ripples.

For the second category, switching table-based DTC has been applied to both two-level and multilevel inverters. For example, in [14], a new virtual vector-based DTC strategy was proposed for two-level PMSM drives to improve steady-state performance and reduce CMV. In [15], a five-level hysteresis-based DTC for open-end winding PMSM was developed to suppress zero-sequence currents and minimize torque ripple. Furthermore, in [16], a novel DTC scheme was designed for matrix converter-fed PMSM drives, where a multidimensional switching table was employed to minimize common-mode voltage.

In the case of multilevel inverter-fed DTC, several contributions can be noted. In [17], a torque ripple reduction method was proposed for a three-level NPC inverter-fed induction machine using a modified five-level torque comparator. In [18], a twelve-sector DTC approach for a three-level inverter-fed induction motor drive was presented to simultaneously achieve torque ripple reduction, neutral-point voltage balancing, and CMV reduction. Likewise, in [19], torque ripple mitigation and flux-droop minimization were addressed for a DTC scheme of an induction motor fed by a three-level NPC inverter. In [20], a four-level hysteresis-based DTC for IPMSM was implemented to enhance torque capability across all speed regions and improve stator current quality. Other works include a modified DTC technique for a three-level NPC inverter-fed induction motor [21], as well as an approach addressing torque ripple and CMV reduction along with neutral-point capacitor voltage balancing in three-level inverter-fed IM drives [5].

Despite its simple structure, robustness to motor parameter variations, and fast dynamic response, classical DTC still suffers from two major challenges: significant torque ripples and current distortion, and high common-mode voltage (CMV) due to the use of zero voltage vectors. These issues can lead to motor damage and reduce system reliability. To date, CMV reduction has not been sufficiently investigated in DTC schemes incorporating simplified SVM for three-level NPC inverter-fed induction machines. Motivated by this gap, we propose an enhanced DTC-SVM strategy aimed at reducing CMV, while simultaneously minimizing current harmonics as well as torque and flux ripples. For a fair evaluation, Table 1 compares the most recent DTC methods reported in the literature and the proposed DTC-SVM. The main advantages of our proposal are:

-

Integration of CMV minimization into a closed-loop control scheme without the need for additional hardware components.

-

Simultaneous reduction in CMV, torque and flux ripples, as well as current harmonic content with a constant switching frequency.

-

Implementation of a simplified SVM strategy that lowers computational complexity and reduces processing load.

-

Use of a single virtual vector within the small hexagon, rather than multiple virtual vectors, to minimize switching complexity and losses.

Table 1. Performance comparison between the proposed DTC method and existing approaches.

Ref.	Method/Strategy	Inverter/Motor Type	CMV Reduction	Additional Features	Limitations
[6], 2022	DTC-SVM with virtual vectors	two-level/five-phase induction motor	Partial reduction	-Constant switching frequency	-High torque ripples at low speed
[7], 2023	Simplified DTC-SVM with the use of only one PI controller	two-level/three-phase induction motor	Not considered	-Simple and less dependent on motor parameters	-Limited precision and robustness of torque and flux control under rapid load changes
[8], 2021	DTC-SVM with 3-D Mamdani type-2 fuzzy controller	Five-level NPC/three-phase induction motor	Not considered	-Improved dynamic performance and current profile	-Increased computational complexity
[10], 2022	DTC-SVM with virtual vector concept	Three-to-five direct matrix converter/five-phase induction motor	Not considered	-xy component elimination	-Increased algorithmic complexity
[14], 2025	ST-DTC with virtual vectors	two-level/three-phase PMSM	Partial reduction	-Improved steady-state performance	-Variable switching frequency -Increased algorithmic complexity
[16], 2021	ST-DTC with multidimensional ST	Two-level matrix converter/three-phase PMSM	Near elimination	-Adequate dynamic performance	-High torque and current ripples -Variable switching frequency
[18], 2025	ST-DTC using twelve sectors	Three-level NPC/three-phase induction motor	Partial reduction	-Balancing of the dc-link neutral point	-High torque and current ripples at low speed -Variable switching frequency
[5], 2022	ST-DTC using specific voltage vectors	Three-level NPC/three-phase induction motor	Partial reduction	-Balancing of the dc-link neutral point	-High current ripple -Variable switching frequency -Restricted DC-bus utilization ratio
P-DTC-SVM	DTC-SVM with simplified SVM algorithm	Three-level NPC/three-phase induction motor	Partial reduction	-Reduced torque, flux, and current ripples across the entire speed -High DC-bus utilization ratio -Constant switching frequency -Simplified algorithm structure	-No consideration given to the DC-link neutral point balance

Table 1. Performance comparison between the proposed DTC method and existing approaches.

Ref.	Method/Strategy	Inverter/Motor Type	CMV Reduction	Additional Features	Limitations
[6], 2022	DTC-SVM with virtual vectors	two-level/five-phase induction motor	Partial reduction	-Constant switching frequency	-High torque ripples at low speed
[7], 2023	Simplified DTC-SVM with the use of only one PI controller	two-level/three-phase induction motor	Not considered	-Simple and less dependent on motor parameters	-Limited precision and robustness of torque and flux control under rapid load changes
[8], 2021	DTC-SVM with 3-D Mamdani type-2 fuzzy controller	Five-level NPC/three-phase induction motor	Not considered	-Improved dynamic performance and current profile	-Increased computational complexity
[10], 2022	DTC-SVM with virtual vector concept	Three-to-five direct matrix converter/five-phase induction motor	Not considered	-xy component elimination	-Increased algorithmic complexity
[14], 2025	ST-DTC with virtual vectors	two-level/three-phase PMSM	Partial reduction	-Improved steady-state performance	-Variable switching frequency -Increased algorithmic complexity
[16], 2021	ST-DTC with multidimensional ST	Two-level matrix converter/three-phase PMSM	Near elimination	-Adequate dynamic performance	-High torque and current ripples -Variable switching frequency
[18], 2025	ST-DTC using twelve sectors	Three-level NPC/three-phase induction motor	Partial reduction	-Balancing of the dc-link neutral point	-High torque and current ripples at low speed -Variable switching frequency
[5], 2022	ST-DTC using specific voltage vectors	Three-level NPC/three-phase induction motor	Partial reduction	-Balancing of the dc-link neutral point	-High current ripple -Variable switching frequency -Restricted DC-bus utilization ratio
P-DTC-SVM	DTC-SVM with simplified SVM algorithm	Three-level NPC/three-phase induction motor	Partial reduction	-Reduced torque, flux, and current ripples across the entire speed -High DC-bus utilization ratio -Constant switching frequency -Simplified algorithm structure	-No consideration given to the DC-link neutral point balance

The remainder of this paper is structured as follows. Section 2 presents the fundamental concepts of the DTC strategy based on a three-level NPC inverter. It also examines CMV issues in the three-level NPC inverter-fed IM drives and explains the basic principles of the conventional SVM technique along with its impact on CMV. Section 3 introduces the proposed SVM-based DTC approach aimed at reducing CMV. Section 4 presents simulation studies conducted to validate the effectiveness of the proposed approach. Section 5 describes the hardware implementation of the control system using FPGA technology. Finally, Section 6 summarizes the main conclusions and highlights the key contributions of the work.

2. Conventional DTC-SVM Design Based on Three Level Inverter and CMV Issues

2.1. Operating Principle of DTC-SVM

DTC-SVM is a control method renowned for its ability to achieve rapid flux and torque response while maintaining robustness against the machine electrical parameter variations. This strategy is characterized by directly determining the switching sequences of the voltage converter fed the IM, to simultaneously regulate the flux and torque, serving as a valuable asset in improving the efficiency and reliability of induction motor systems. DTC-SVM offers inherent decoupling between flux and torque in asynchronous machine control, resulting in excellent dynamic performance with limited sensitivity to machine parameters [13].

The dynamic behavior of the controlled IM is described in the stationary reference frame (α, β) using the state model, while neglecting iron losses and magnetic saturation, as follows: [8,22]:

$${\displaystyle \frac{d}{dt}}\left[\begin{array}{l}{i}_{s \alpha }\\ i_{s \beta }\\ {\mathrm{\phi }}_{s \alpha }\\ {\mathrm{\phi }}_{s \beta }\end{array}\right]=\left(\begin{array}{cccc}-({\displaystyle \frac{R_s}{\mathrm{\sigma }{R}_r}}+{\displaystyle \frac{R_r}{\mathrm{\sigma }{L}_r}})& -\omega & {\displaystyle \frac{Rr}{\mathrm{\sigma }{L}_s{L}_r}}& {\displaystyle \frac{\omega }{\mathrm{\sigma }{L}_s}}\\ \omega & -({\displaystyle \frac{R_s}{\mathrm{\sigma }{R}_r}}+{\displaystyle \frac{R_r}{\mathrm{\sigma }{L}_r}})& {\displaystyle \frac{\omega }{\mathrm{\sigma }{L}_s}}& {\displaystyle \frac{Rr}{\mathrm{\sigma }{L}_s{L}_r}}\\ -R_s& 0& 0& 0\\ 0& -R_s& 0& 0\end{array}\right)\ast \left[\begin{array}{l}{i}_{s \alpha }\\ i_{s \beta }\\ {\mathrm{\phi }}_{s \alpha }\\ {\mathrm{\phi }}_{s \beta }\end{array}\right]+\left[\begin{array}{cc}{\displaystyle \frac{1}{\mathrm{\sigma } L_s}}& 0\\ 0& {\displaystyle \frac{1}{\mathrm{\sigma } L_s}}\\ 1& 0\\ 0& 1\end{array}\right]\ast \left[\begin{array}{l}{V}_{s \alpha }\\ V_{s \beta }\end{array}\right]$$

(1)

where $V_s$, ${\mathrm{\phi }}_s$, $i_s$, $\omega$, $R_s$, $R_r$, $L_s$ and $L_r$ represent stator voltage, stator flux, stator currents, electric speed, stator resistance, rotor resistance, stator inductance, and rotor inductance respectively.

The parameter $\mathrm{\sigma }$ denotes the Blondel coefficient given as

$$\mathrm{\sigma }=1-{\displaystyle \frac{M_{sr}^2}{L_s{L}_r}}$$

(2)

with $M_{sr}$ is the mutual inductance.

The equation that defines the mechanical behavior of the IM is presented as follows:

$$J{\displaystyle \frac{d}{dt}}\Omega =T_{em}-f \Omega -T_l$$

(3)

where J, $\Omega$, $T_{em}$, f, $T_l$ represent respectively the inertia moment, the mechanical speed, the electromagnetic torque, the viscous friction coefficient and the load torque.

The global structure of the DTC-SVM consists of several subsystems including torque and flux estimators, torque and flux controllers, a modulation technique block, a three-level voltage source inverter, and a three-phase induction motor. The torque reference is obtained from the speed regulator, while the actual torque is estimated based on the stator voltages and currents.

The estimation block of stator flux linkage and the torque is based on the following equations:

$${\mathrm{\phi }}_{s\alpha }={\displaystyle \int \left(V_{s\alpha }-R_s*i_{s\alpha }\right)}dt$$

(4)

$${\mathrm{\phi }}_{s\beta }={\displaystyle \int \left(V_{s\beta }-R_s\ast i_{s\beta }\right)}dt$$

(5)

$$T_{em}={\displaystyle \frac{3}{2}}p({\mathit{\phi }}_{s\mathit{\alpha }}·i_{s\mathit{\beta }}-{\mathit{\phi }}_{s\mathit{\beta }}·i_{s\mathit{\alpha }})$$

(6)

where ${\mathrm{\phi }}_{s\alpha },{\mathrm{\phi }}_{s\beta }$ are the stator fluxes in reference frame (α, β), $i_{s\alpha },i_{s\beta }$ are the stator currents in the coordinate system (α, β), $V_{s\alpha },V_{s\beta }$ are the stator voltage, and p is the pole pairs number.

Once the stator flux is estimated, the magnitude of the stator flux linkage can be determined as stated below:

$$\left|{\mathit{\phi }}_s\right|=sqrt\left({\mathit{\phi }}_{s\mathit{\alpha }}^2+{\mathit{\phi }}_{s\mathit{\beta }}^2\right)$$

(7)

The error between the estimated torque $T_{em}$ and the reference one $T_{emref}$ as well as the difference between the estimated stator flux magnitude $\left|{\mathrm{\phi }}_s\right|$ and the reference stator flux are considered as the inputs to PI comparators. The outputs of both controllers can be considered as the desired reference stator voltage components in the d-q coordinate system. These DC voltage commands are subsequently transformed into the stationary frame (α-β) and fed into the Space Vector Modulation (SVM) block. Within the SVM block, the voltage commands are processed to produce gate drive pulses for controlling the three-level voltage source inverter (VSI) circuit.

For more comprehensive information, please refer to the paper [23], which provides an extensive and detailed explanation of the DTC-SVM control approach.

2.2. Modeling of Three Level NPC Inverter

Amongst the multilevel inverters, the three-level NPC inverter is widely employed in DTC drives due to its ability to reduce torque and flux ripples. This topology offers greater flexibility in selecting voltage vectors, enabling precise control of the stator flux for various speed operations. Hence, the DTC method proposed in this study employs a three-level three-phase inverter to drive the IM. This converter provides 27 voltage vectors (VVs) for generating the desired voltage. The fundamental structure of a three-level NPC inverter and its connected load are illustrated in Figure 1.

The configuration comprises a DC source and four IGBTs allocated to each leg or phase of the inverter and two clamping diodes. The DC bus voltage is equally divided into two potentials of ${\mathrm{V}}_{\mathrm{dc}}/2$ each. The midpoint of each leg is connected to the IM terminal. To safeguard against the risk of short-circuiting the DC source at the inverter input or causing disturbance to the AC load at the output, it is crucial to maintain the condition where the four switches on a single leg are not closed or opened simultaneously.

Figure 2 presents the space vector diagram and switching states of a three-level NPC inverter. It provides a representation of 19 voltage vectors. These voltage vectors correspond to 27 switching states, which signify how the stator is connected to the DC power supply. The connections are indicated by “−1”, “0”, “1”. These digits signify that the corresponding arm is connected to the negative (N), neutral (O), or positive (P) points of the DC link respectively.

Table 2. Switching state for three-level NPC inverter.

SAH1	SAH2	SAL1	SAL2	State	Output Voltage
1	1	0	0	P	$+V_{dc}/2$
0	1	1	0	O	0
0	0	1	1	N	$-V_{dc}/2$

provides the connection functions and their corresponding output voltages for the first leg of the inverter (leg A).

2.3. CMV Issues in Three-Level NPC Inverter-Fed IM

When an inverter drives an IM, high dv/dt (rate of voltage change) is generated due to switching actions. This rapid voltage transition, also known as CMV, leads to the circulation of substantial current, known as leakage current, through the motor bearing, as shown in Figure 3. This current will pass through the parasitic capacitance C_p and it can be determined as

$$i_L=i_a+i_b+i_c=C_P{\displaystyle \frac{d{V}_{CM}}{dt}}$$

(8)

If this circulating current persists for a prolonged period, it can result in bearing failure as presented in Figure 4. This figure illustrates the physical consequences of bearing damage in induction motors powered by inverters, where high-frequency CMV are present. The observed features like flaking, fretting and cracking are typical consequences of repeated discharge events across motor bearings. These discharges arise due to capacitive coupling between stator and rotor, allowing transient currents to pass through the bearing system when CMV is not adequately suppressed. The fretting phenomenon is due to micro-oscillatory motions between contact surfaces under load, leading to adhesion, and wear. The flacking behavior refers to a surface fatigue failure mechanism. It is characterized by the detachment of small pieces of material from the element surfaces, leading to surface irregularities. Concerning the cracking effect, it refers to the propagation of fractures in the motor bearings. To address the issues of CMV, it is necessary to reduce its magnitude. Thus, the proposed DTC method is designed while taking CMV into consideration. The CMV of the inverter can be effectively defined as the voltage difference between the load star point and the neutral point of the DC bus of the inverter. This relationship can be mathematically expressed using the following equation [24,25,26]:

$$V_{CM}=V_{NO}={\displaystyle \frac{V_{AO}+V_{BO}+V_{CO}}{3}}$$

(9)

where $V_{AO}$, $V_{BO}$, and $V_{CO}$ are the three-phase terminal voltages.

In three level NPC inverters, there are three possible voltage values for each pole: $-{\mathrm{V}}_{\mathrm{dc}}/2$, 0, and ${\mathrm{V}}_{\mathrm{dc}}/2$. These values represent the voltage amplitudes relative to the DC bus voltage. According to Equation (9), the CMV can have seven different amplitudes: 0, $\pm {\mathrm{V}}_{\mathrm{dc}}/6$, $\pm {\mathrm{V}}_{\mathrm{dc}}/3$, and $\pm {\mathrm{V}}_{\mathrm{dc}}/2$. The specific amplitude of the CMV depends on the type of space vector used in the inverter system.

Table 3. Correlation between space vector types and CMV amplitude.

Vector’s Type	Voltage Vector	CMV Level
Zero	NNN	$-V_{dc}/2$
	OOO	$0$
	PPP	$+V_{dc}/2$
Small	ONN, NON, NNO	$-V_{dc}/3$
	OON, NOO, ONO	$-V_{dc}/6$
	POO, OPO, OOP	$+V_{dc}/6$
	PPO, OPP, POP	$+V_{dc}/3$
Medium	PON, OPN, NPO, NOP, ONP, PNO	$0$
Large	PNN, NPN, NNP	$-V_{dc}/6$
	PPN, NPP, PNP	$+V_{dc}/6$

illustrates the relationship between the space vector type and the CMV amplitude. Medium vectors, when utilized in the inverter, always result in a constant CMV amplitude of zero. This means that when the inverter operates with a medium vector, the CMV will be completely suppressed or eliminated. On the other hand, large vectors provide two possible CMV values, which are $\pm {\mathrm{V}}_{\mathrm{dc}}/6$. Small vectors.

(${\overline{\mathrm{V}}}_1-{\overline{\mathrm{V}}}_6$) offer four different levels of CMV. These levels are $\pm {\mathrm{V}}_{\mathrm{dc}}/6$ and $\pm {\mathrm{V}}_{\mathrm{dc}}/3$. Finally, the zero vector (${\overline{\mathrm{V}}}_0$) results in a CMV of zero when the switching state is (OOO). However, when the switching states (NNN) or (PPP) are applied, the zero vector can generate the highest CMV amplitudes of $\pm {\mathrm{V}}_{\mathrm{dc}}/2$.

2.4. Two-Level Hexagon-Based Modulation Method

This approach divides the three-level space vector diagram into six regions that are covered by six two level hexagons, each treated as a two-level space vector diagram as shown in Figure 5.

Consequently, the first step of this method involves identifying the appropriate two-level hexagon that includes the reference voltage vector ${\overline{\mathrm{V}}}_{\mathrm{r}}$. Next, the origin of ${\overline{\mathrm{V}}}_{\mathrm{r}}$ is shifted to the center of the selected two-level hexagon, resulting in a new virtual reference vector. Hence, to implement this modulation method, three fundamental steps must be followed: (i) identification of the small hexagon, (ii) computation of duty cycles, and (iii) generation of switching sequences. So, after identifying the relevant small hexagon (H₁, H₂, … H₆), the next step is to determine the appropriate subsector within the chosen hexagon. To accomplish this, we introduce a new space vector ${\overline{\mathrm{V}}}_{\mathrm{k}}$, which is referenced to the center of the corresponding two-level diagram.

The vector ${\overline{\mathrm{V}}}_{\mathrm{k}}$ can be derived from the initial reference vector ${\overline{\mathrm{V}}}_{\mathrm{r}}$ using the equation provided below:

$${\overline{V}}_k=\overline{V}r-{\displaystyle \frac{V_{dc}}{3}}{e}^{j{\displaystyle \frac{(H-1)}{3}}\pi }$$

(10)

where H (1 … 6) is the number of the two-level hexagon.

To recapitulate, we simplify the three-level vector diagram into a two-level diagram. Then, we utilize the same methodology used for two-level voltage source inverters to synthesize the new reference voltage vector ${\overline{\mathrm{V}}}_{\mathrm{k}}$. To achieve this, we need to determine the subsector that encompasses the new reference vector ${\overline{\mathrm{V}}}_{\mathrm{k}}$ and identify the two suitable adjacent vectors from the small hexagon. Subsequently, we calculate their respective application times [12]. For further clarification, let us assume that ${\overline{\mathrm{V}}}_{\mathrm{k}}$ is located in the second subsector within the small hexagon H₁, as depicted in Figure 6. In this scenario, the small vector ${\overline{\mathrm{V}}}_2$ and the medium vector ${\overline{\mathrm{V}}}_8$ serve as the adjacent vectors to ${\overline{\mathrm{V}}}_{\mathrm{k}}$, while the small vector ${\overline{\mathrm{V}}}_1$ represents a virtual zero vector. These vectors are selected as the closest vectors to ${\overline{\mathrm{V}}}_{\mathrm{k}}$ in order to ensure a smooth trajectory.

To determine the duty cycles dx, dy, and d0, which are the relative application times of ${\overline{\mathrm{V}}}_8$, ${\overline{\mathrm{V}}}_2$ and ${\overline{\mathrm{V}}}_1$ respectively, the volt-second equation is used and it is written as follows:

$$\left\{\begin{array}{l} {\overline{V}}_k=d_x \times {\overline{V}}_8+d_y \times {\overline{V}}_2+d_0 \times {\overline{V}}_1\\ d_x+d_y+d_0=1\end{array}\right.$$

(11)

According to Equation (11) and the two-level space vector diagram of the small hexagon H1, we can write:

$$\left\{\begin{array}{l}\left|V_k\right|\cos \theta =d_x\left|V_8\right|\cos {60}^{°}+d_y\left|V_2\right|\cos {120}^{°}\\ \left|V_k\right|\sin \theta =d_x\left|V_8\right|\sin 60°+d_y\left|V_2\right|\sin {120}^{°}\\ d_x+d_y+d_0=1\end{array}\right.$$

(12)

By solving Equation (12) and extending this principle to all operating sub-sectors, the general expressions of the duty cycles are given as follows:

$$\begin{array}{l}{d}_x=2{\displaystyle \frac{\sqrt{3}\left|{\overline{V}}_k\right|\sin \left(S_s\frac{\pi }{3}-\theta \right)}{V_{dc}}}\\ d_y=2{\displaystyle \frac{\sqrt{3}\left|{\overline{V}}_k\right|\sin \left(\theta -\left(S_s-1\right)\frac{\pi }{3}\right)}{V_{dc}}}\\ d_0=1-\left(d_x+d_y\right)\end{array}$$

(13)

where “$\theta$” represents the phase angle of the newly introduced reference vector ${\overline{\mathrm{V}}}_k$ and “$S_s$” denotes the subsector number assigned to the small hexagon.

In the last stage, the appropriate switching states are determined for each sampling period. Figure 7 presents an illustrative example showcasing a conventional distribution of sequences along with the corresponding CMV, characterized by $S_s$ = 2 and H = 1.

3. The Proposed DTC-SVM with CMV Reduction for Three-Level NPC Inverter

The generalized structure of the proposed SVM-based DTC scheme for the induction motor drive is shown in Figure 8. It primarily consists of PI regulator modules for controlling motor speed, stator flux, and electromagnetic torque, with parameters determined using the pole compensation technique. In addition, it includes a coordinate transformation module, a flux and torque estimation block, and an SVM module based on a CMV reduction algorithm, which selects the appropriate voltage vector to achieve the desired control objectives. In the previously analyzed example, the five-level CMV is generated by specific vectors. The medium vector ${\overline{\mathrm{V}}}_8$ leads to a CMV of 0 V. The small vector ${\overline{\mathrm{V}}}_2$ produces a CMV with an amplitude of ${\mathrm{V}}_{\mathrm{dc}}/6$. The small vector ${\overline{\mathrm{V}}}_1$ is employed as a virtual zero vector, generating two different voltage levels. When ${\overline{\mathrm{V}}}_1$ is in the state (POO), it produces a voltage level of ${\mathrm{V}}_{\mathrm{dc}}/6$. On the other hand, when ${\overline{\mathrm{V}}}_1$ is in the state (ONN), it generates a voltage level of $-{\mathrm{V}}_{\mathrm{dc}}/3$.

In order to decrease the levels of the CMV, our proposal involves replacing the small vector ${\overline{\mathrm{V}}}_1$, which acts as a virtual zero vector, with a combination of two vectors providing the same CMV as ${\overline{\mathrm{V}}}_2$ (OON) and ${\overline{\mathrm{V}}}_8$ (PON). These vectors are ${\overline{\mathrm{V}}}_0$, the adjacent vector to ${\overline{\mathrm{V}}}_2$, with the switching state (OOO) and the large vector ${\overline{\mathrm{V}}}_7$, the adjacent vector to ${\overline{\mathrm{V}}}_8$, as presented in Figure 9. In fact, the zero vector ${\overline{\mathrm{V}}}_0$ (OOO) yields the same CMV as the medium vector ${\overline{\mathrm{V}}}_8$ (PON), which is equal to 0 V. Similarly, the large vector ${\overline{\mathrm{V}}}_7$ (PNN) produces the same CMV as the small vector ${\overline{\mathrm{V}}}_2$ (OON), which is equal to $-{\mathrm{V}}_{\mathrm{dc}}/6$.

In this way, the CMV levels are confined to the ranges [$-{\mathrm{V}}_{\mathrm{dc}}/6$, 0] or of [0, $+{\mathrm{V}}_{\mathrm{dc}}/6$], since within the selected small hexagon, the virtual zero vector is synthesized either by combining a zero vector with a small vector or a medium vector with a small vector. It should be noted that only the small vectors corresponding to states that yield a CMV of $\pm {\mathrm{V}}_{\mathrm{dc}}/6$ are utilized, while for the zero vector, only the (OOO) state is employed.

Accordingly, ${\overline{\mathrm{V}}}_0$ and ${\overline{\mathrm{V}}}_7$ are used to generate a virtual zero vector corresponding to the vector ${\overline{\mathrm{V}}}_1$ when ${\overline{\mathrm{V}}}_{\mathrm{k}}$ is located in the subsector 2 ($S_s=2$) of the first hexagon. The duration time of ${\overline{\mathrm{V}}}_0$ is denoted by $d_{02}$ and the duration time of ${\overline{\mathrm{V}}}_7$ is denoted by $d_{01}$. The switching sequences as well as the equivalent CMVs for this example are illustrated in Figure 10. As can be seen, the produced CMV involves only two levels ($-{\mathrm{V}}_{\mathrm{dc}}/6$ and 0). Compared with the CMV generated by the conventional method shown in Figure 7, the levels $\pm {\mathrm{V}}_{\mathrm{dc}}/3$ and $+{\mathrm{V}}_{\mathrm{dc}}/6$ are eliminated. With the proposed method, a simultaneous reduction in both the CMV amplitude and its periodic variations is achieved. Moreover, this approach does not compromise the DC-bus utilization ratio, as it employs the same active vectors to synthesize the reference vector ${\overline{\mathrm{V}}}_{\mathrm{k}}$. Extending this concept to all subsectors, the distribution sequences for the first small hexagon are depicted in

Table 4. Switching sequences distribution for the first small hexagon.

Subsector Ss	Switching Sequences Distribution
1	OON-PON-PNN-PNO-PNN-PON-OON
2	OOO-OON-PON-PNN-PON-OON-OOO
3	ONO-OOO-OON-PON-OON-OOO-ONO
4	PNO-ONO-OOO-OON-OOO-ONO-PNO
5	PNN-PNO-ONO-OOO-ONO-PNO-PNN
6	PON-PNN-PNO-ONO-PNO-PNN-PON

.

In the conventional SVM, the time intervals corresponding to the applied vectors are determined based on the volt-second balance principle. The main principle is also adopted in the proposed algorithm. To determine the duration times of the used vectors that virtualize the zero vector ${\overline{\mathrm{V}}}_1$, another example is presented for better understanding when ${\overline{\mathrm{V}}}_{\mathrm{k}}$ is situated in the third subsector of the first small hexagon, as illustrated in Figure 11. In this case, the small vector ${\overline{\mathrm{V}}}_1$ is virtualized using the medium vector ${\overline{\mathrm{V}}}_8$ and the small vector ${\overline{\mathrm{V}}}_6$ with the state (ONO). Based on the geometric construction of Figure 11, we can consider the two right triangles (ABC) and (DBC). The duration time $d_{01}$ is affected to ${\overline{\mathrm{V}}}_8$ and $d_{02}$ is affected to ${\overline{V}}_6$. The following relationship is derived, where $d_0$ represents the duration time for which the virtual zero vector ${\overline{\mathrm{V}}}_1$ is applied in the conventional SVM:

$$\left\{\begin{array}{l}\sin (\pi /6)={\displaystyle \frac{d_{02}\ast {\mathrm{V}}_6}{d_0\ast {\mathrm{V}}_1}}\\ \sin (\pi /3)={\displaystyle \frac{d_{01}\ast {\mathrm{V}}_8}{d_0\ast {\mathrm{V}}_1}}\end{array}\right.$$

(14)

Based on Equation (12), we can write

$$\left\{\begin{array}{l}{d}_0\ast {\mathrm{V}}_1= 2\ast d_{02}\ast {\mathrm{V}}_6\\ \sqrt{3}\ast d_0\ast {\mathrm{V}}_1= 2\ast d_{01}\ast {\mathrm{V}}_8\end{array}\right.$$

(15)

Given that ${\overline{\mathrm{V}}}_1$ and ${\overline{\mathrm{V}}}_6$ are small vectors, and ${\overline{\mathrm{V}}}_8$ is a medium vector, we can express $V_1=V_6$ and $V_8=\sqrt{3} V_1$. Substituting these expressions into Equation (13) gives

$$\left\{\begin{array}{l}{d}_{01}= d_0/2\\ d_{02}= d_0/2\end{array}\right.$$

(16)

Accordingly, we can define the new virtual zero vector ${\overline{\mathrm{V}}}_{\mathrm{ZV}}$ such that

$$d_0{\overline{V}}_{ZV}=d_{01}{\overline{V}}_x+d_{02}{\overline{V}}_y$$

(17)

where ${\overline{\mathrm{V}}}_x$ and ${\overline{\mathrm{V}}}_y$ represent the adjacent vectors nearest to those employed in the conventional SVM for synthesizing the reference vector ${\overline{\mathrm{V}}}_k$ with a reduced CMV.

The suggested method is therefore expanded in the following way: for each vector ${\overline{\mathrm{V}}}_{\mathrm{k}}$, two vectors are used in place of the conventional zero vector, employed in a two-level hexagon. For each active vector, we proceed to choose its adjacent vector. In instances where a zero vector or a small vector is chosen for synthesizing the virtual zero vector, we implement a specific switching state to ensure that its CMV matches that of its non-adjacent active vector. For further elucidations, the synthesis of the virtual zero vector ${\overline{\mathrm{V}}}_1$, when located within the first hexagon, is described as follows:

▪

If $S_s=1$, then ${\overline{\mathrm{V}}}_1$ is synthesized by ${\overline{\mathrm{V}}}_2$ (OON) and the medium vector ${\overline{\mathrm{V}}}_{18}$ (PNO).

▪

If $S_s=2$, then ${\overline{\mathrm{V}}}_1$ is synthesized by ${\overline{\mathrm{V}}}_0$ (OOO) and ${\overline{\mathrm{V}}}_7$ (PNN).

▪

If $S_s=3$, then ${\overline{\mathrm{V}}}_1$ is synthesized by ${\overline{\mathrm{V}}}_6$ (ONO) and ${\overline{\mathrm{V}}}_8$ (PON).

▪

If $S_s=4$, then ${\overline{\mathrm{V}}}_1$ is synthesized by ${\overline{\mathrm{V}}}_2$ (OON) and ${\overline{\mathrm{V}}}_{18}$ (PNO).

▪

If $S_s=5$, then ${\overline{\mathrm{V}}}_1$ is synthesized by ${\overline{\mathrm{V}}}_0$ (OOO) and ${\overline{\mathrm{V}}}_7$ (PNN).

▪

If $S_s=6$, then ${\overline{\mathrm{V}}}_1$ is synthesized by ${\overline{\mathrm{V}}}_0$ (ONO) and ${\overline{\mathrm{V}}}_8$ (PON).

4. Simulation Results

This section involves conducting numerical simulations to validate the effectiveness of the suggested DTC algorithm dedicated to a three-level inverter-fed IM drive based on CMV reduction. The simulations were carried out in MATLAB R2020a/Simulink environment. The model includes detailed representations of the three-level inverter, induction motor, and controllers, as shown in Figure 12. A comparative analysis of the proposed method with the conventional DTC-SVM approach is presented. The electrical system and control algorithm parameters are shown in

Table 5. Control system parameters.

Parameter Description	Value
DC-bus voltage	Vdc = 560 V
DC-bus capacitor	C1 = C2 = 470 μF
Switching frequency	Fc = 5 kHz
Sampling frequency	Fs = 10 kHz
Output frequency	fo = 50 Hz
Torque controller parameters	Kp = 1500; ki = 0.05
Flux controller parameters	Kp = 20.103; ki = 2
Speed controller parameters	Kp = 3.2; ki = 0.15

.

The provided Appendix A contains the nominal IM parameters used for both simulation and real-time implementation.

The dynamic performances of the IM operating at speeds of 382 r/min, 764 r/min, and 1435 r/min are presented in Figure 13, Figure 14 and Figure 15. The analysis focuses on the torque, flux, and stator current responses for both the conventional DTC-SVM and the proposed DTC method aimed at reducing CMV. At all three speeds, the proposed DTC exhibits significant improvements, particularly in terms of reduced flux and current oscillations. These improvements are noticeable in the detailed zoom-in view from 0.2 to 0.4 s, where the proposed method demonstrates smoother torque response and lower current ripples. To offer further insights, a comparative analysis of the ripple characteristics associated with the two control strategies is presented in

Table 6. Comparison between conventional DTC-SVM and proposed DTC.

Performance Index	Conventional DTC-SVM	Proposed DTC-SVM	Improvement (%)
Torque ripple (%)	29	27	6.9%
Flux ripple (%)	1.7	1.2	29.4%
Current ripple (%)	37	28	24.3%
Speed error (%)	2.55	2.40	5.9%

. The results clearly demonstrate that the proposed method outperforms the conventional method, indicating a significant improvement in performance characterized by reduced ripples and enhanced stability. These enhancements primarily originate from the effective suppression of disturbances caused by CMV. In conventional inverter control schemes, high CMV levels induce common-mode currents and switching transients that distort voltage waveforms, negatively impacting flux estimation accuracy and consequently causing oscillations in torque and current. By employing the proposed algorithm with minimized CMV, the inverter switching transitions become smoother, which decreases harmonic distortion and electromagnetic interference.

Figure 16 illustrates the harmonic spectra of the phase stator current at nominal speed under no-load conditions for both the proposed and conventional control methods. Analyzing the harmonic content reveals significant differences in performance between the two strategies. The THD for the proposed method is limited to 5.72% (Figure 16b), indicating a more favorable current waveform with reduced harmonic content. Meanwhile, the conventional approach exhibits a higher rate of 6.41% (Figure 16a), suggesting greater distortion in the stator current. This reduction in THD for the proposed method is crucial, as it not only enhances the efficiency of the motor but also minimizes potential overheating. In our opinion, this difference in THD is due to the fact that the conventional algorithm employs only three active vectors to synthesize the reference voltage vector, which limits the precision of the approximation, especially during transient states or low-speed operation. By introducing a fourth vector, the proposed algorithm enhances the flexibility and resolution of vector synthesis. This leads to a more accurate approximation of the desired reference voltage vector within a given sampling period, reducing voltage vector errors. The better tracking of the reference vector results in smoother stator flux trajectories. This, in turn, minimizes torque ripple, which is one of the main contributors to harmonic distortion in motor currents.

Figure 17 depicts the results obtained for CMV and leakage current using the conventional DTC and the proposed one. It is evident that the conventional DTC-SVM generates more significant fluctuations in CMV amplitude, reaching a peak value of V_dc/2, which is produced by the zero vector. Applying the proposed DTC, the amplitude of the CMV and its variation are considerably reduced. As predicted in the theoretical study, the positive and the negative peak values are equal to ±V_dc/6. Certainly, this is because of the remove of the zero vectors and the small vectors with high CMV. Moreover, the conventional DTC generates a significant leakage current, peaking at 2A, due to its substantial variation in CMV. In contrast, the proposed DTC algorithm demonstrates superior performance by achieving approximately a 50% reduction in leakage current amplitude compared to the conventional DTC. It is important to note that this difference arises from the variations in CMV across each sector, since the amplitude of the leakage current depends not only on the CMV magnitude but also on its fluctuations.

For further investigation, the frequency spectra of the acquired CMVs are illustrated in Figure 18. It is evident that the conventional DTC-SVM stands out as the most disruptive algorithm, generating the highest harmonic with an amplitude of 48.35 V at a frequency of 148 Hz. In comparison, the proposed DTC exhibits a noteworthy improvement, with its most significant harmonic having an amplitude of 43.03 V at the same frequency. The lower-frequency harmonics for the conventional DTC are measured at 10.75 V and 5.64 V, while for the proposed DTC, they are reduced to 16.94 V and 3.16 V, respectively.

Figure 19 shows the performance of the conventional DTC-SVM and the proposed one with regard to the RMS values of CMV and leakage current with respect to the speed variation. The obtained results prove that the proposed DTC exhibits enhanced performance in reducing both the CMV and, generally, the leakage current, which achieves the lowest RMS values for both the CMV and leakage current.

To evaluate the dynamic performance of both the proposed and conventional methods, simulations were performed under sudden load and unload conditions. The IM initially operated under no-load conditions, and at t = 0.35 s, a full load was applied. The obtained results are presented in Figure 20 and Figure 21. As shown, both methods exhibit similar dynamic behavior, with comparable response times to abrupt changes. The proposed method effectively regulates the torque, which closely tracks its reference values. The stator current exhibits low ripple and responds accurately to step changes in the torque reference. Furthermore, the CMV was maintained within ±Vdc/6, transitioning smoothly even during sudden torque. Moreover, no overshoot was observed during rapid load variations. These results indicate that the proposed DTC strategy enhances the motor’s operating conditions without compromising system dynamics, which represents a key advantage of the proposed algorithm.

To provide a quantitative assessment of tracking performance, the Integral of Absolute Error (IAE) is computed for torque, flux, and speed obtained with both methods. This performance index is defined as the integral of the absolute value of the error between the actual output and the reference over a given time period [27]. The obtained result is shown in Figure 22. It is evident that the proposed DTC-SVM consistently achieves lower IAE values compared to the conventional approach. For torque, the reduced IAETem highlights the ability of the proposed strategy to mitigate torque oscillations and ensure smoother dynamics. In the case of flux, the lower IAEφ demonstrates enhanced flux regulation and reduced steady-state error. The speed IAEΩ also confirms a superior dynamic response. Hence, the obtained results emphasize that the proposed method based on CMV mitigation improves both transient and steady-state accuracy.

5. FPGA Implementation

5.1. HIL Co-Simulation

Our goal is to provide a hardware-based architecture for an improved DTC strategy based on CMV reduction for a three-level NPC inverter in motor drive applications. FPGA has been selected over alternative hardware techniques due to its ability to combine the flexibility of DSPs with the high performance of ASICs. Hardware Description Languages (HDL) like Verilog and VHDL are used to program FPGAs [28]. These languages necessitate extensive knowledge of hardware design and can be a time-consuming process. In this instance, in our work, we have chosen a high-level programming tool based on graphic toolboxes that enables us to rapidly and simply create, simulate, and execute the compiled design in the MATLAB/Simulink environment at a high degree of abstraction. After the verification of the Xilinx System Generator (XSG)-based architecture in Simulink, it can be seamlessly mapped to hardware implementation using the Xilinx ISE Design Suite. The above technique is called Hardware-in-the-Loop (HIL) co-simulation [29]. To explain further, it serves as an intermediary step in system verification, positioned between software simulation and the actual implementation of the controller on the experimental system. The flowchart in Figure 23 illustrates the HIL testing process utilizing FPGA. Initially, the controller and VSI system undergo modeling in MATLAB/Simulink, and their performance is validated through simulations. Moreover, the controller is developed using the XSG digital platform, and its performance is evaluated based on the Simulink control model. Subsequently, the digital modeling of the controller is later validated through real-time HIL co-simulation. The controller system is validated through co-simulation using the Virtex-5 FPGA kit. To establish a physical connection between the FPGA kit and the computer, a USB cable is employed. This cable links the Joint Test Action Group (JTAG) port on the FPGA to a USB port on the computer, facilitating the execution of HIL real-time implementation [30].

The controller system is validated through co-simulation using the Virtex-5 FPGA kit. To establish a physical connection between the FPGA kit and the computer, a USB cable is employed. This cable links the Joint Test Action Group (JTAG) port on the FPGA to a USB port on the computer, facilitating the execution of HIL real-time implementation [29].

5.2. Real Time Implementation Using XSG Blockset

We present in this section the real time implementation achieved using the suggested architecture, which has been implemented with the XSG blockset. The system performance analysis is conducted using the same parameters as those employed in the simulation case. An illustration of the hardware implementation of the proposed DTC is shown in Figure 24. Figure 25 presents the proposed DTC design with XSG tools and presents some blocks’ configuration.

Figure 26 and Figure 27 illustrate the steady-state evolution of the motor parameters at nominal speed for both software and hardware implementation obtained with the conventional method and the proposed one, respectively. The obtained hardware signals were transferred to MATLAB/Simulink through the USB-JTAG communication link, which allows real-time monitoring and recording of these signals. The acquired data were then processed and analyzed in MATLAB for further validation. It can be seen that, for both methods, the conducted real-time implementation curves align well with simulation curves, affirming the excellent performance and accuracy of the hardware implementation.

Except for a slight difference observed between the software and hardware results, the overall behaviors remain consistent. These minor discrepancies are mainly attributed to non-ideal factors such as fixed-point arithmetic, switching device delays, and signal acquisition noise, which are not considered in the ideal simulation environment.

Using either method, the flux and torque are effectively controlled, ensuring accurate tracking of their respective references. In particular, the proposed DTC method produces nearly sinusoidal stator current with low ripple content, while maintaining a reduced CMV amplitude of Vdc/6, compared to Vdc/2 obtained with the conventional method. This leads to an approximate 50% reduction in leakage current. For further clarification, additional quantitative data have been included in

Table 7. Comparison between hardware results of the conventional DTC-SVM and the proposed DTC.

	Conventional DTC-SVM	Proposed DTC-SVM with CMV Reduction
Torque ripple (%)	34	31
Flux ripple (%)	1.9	1.5
Current ripple (%)	39	29
Speed error (%)	3.4	2.9
CMV peak values (V)	±Vdc/2	±Vdc/6
Leakage current peak values (A)	±2	±1
Execution time (µs)	0.82	0.74

to clearly highlight the performance differences in terms of torque and flux ripples, current THD, CMV and leakage current peak values, and execution time. The obtained comparison shows excellent agreement with the software comparison, demonstrating that the proposed method surpasses the conventional one, achieving a noticeable enhancement in performance through reduced ripple levels. As for the measured execution time, it is 0.82 µs for the conventional DTC-SVM and 0.74 µs for the proposed method. These results highlight the high processing speed of FPGA implementation, made possible by its inherent parallel processing capability. Compared to the conventional approach, the proposed DTC achieves a lower execution time. This improvement arises because, in the conventional DTC-SVM, identifying the region of the reference vector requires a complex algorithm, whereas in the proposed method, a subsector is determined simply by comparing the angle. The rapid computation time of the FPGA significantly enhances the performance of the IM, overcoming the typical constraints associated with sequential algorithms in DSP. These findings are noteworthy and provide motivation to develop more advanced control techniques and implement them on the FPGA board.

For extended comparison purposes, the hardware implementation of both the proposed and conventional DTC methods was carried out under sudden load and unload conditions. The corresponding results, presented in Figure 28 and Figure 29, exhibit waveforms similar to those obtained in the dynamic software simulations. For both control methods, the electromagnetic torque responds rapidly during the dynamic process without significant overshoot. Furthermore, the CMV peak value is maintained at V_dc/6, demonstrating the robustness of the proposed method against sudden load disturbances. These results confirm that the proposed DTC ensures satisfactory dynamic performance.

6. Conclusions

In this paper, an enhanced DTC strategy for induction motor drives fed by a three-level NPC inverter is presented. To address the main drawbacks of conventional DTC, namely torque ripple, current distortion, and variable switching frequency, the SVM technique is integrated into the proposed DTC framework. The key objective is to mitigate the CMV effects inherent to the traditional DTC-SVM scheme. By reformulating the three-level space vector diagram into an equivalent two-level representation, the proposed SVM-based approach simplifies the control structure while embedding CMV suppression directly into the modulation process through the use of a virtual zero vector synthesized from active states.

The results demonstrate significant improvements in current quality, torque and flux ripple reduction, and CMV mitigation, while maintaining the fast dynamic response characteristic of DTC. Furthermore, the proposed method retains a simple design and implementation. Real-time validation was carried out on a Virtex-5 FPGA platform using the XSG tool. The hardware results closely match the simulation outcomes, confirming the effectiveness of the proposed approach. The implementation benefits from the high degree of parallelism inherent to FPGA architectures, enabling short execution time. Compared with conventional DTC-SVM, this reduced execution latency decreases control loop delays, which in turn lowers current and torque harmonics and enhances the induction motor’s lifetime.

Despite the demonstrated improvements in torque and current performance, the proposed control strategy does not explicitly address the issue of DC-link neutral-point voltage balancing, a fundamental challenge in three-level NPC inverter topologies. Imbalanced neutral-point voltages can lead to unequal stress on power semiconductor devices and increased switching losses. Future investigations should focus on integrating an active neutral-point voltage balancing loop within the suggested control strategy to ensure DC-link voltage symmetry. This improvement would alleviate imbalance-related issues such as unequal device stress. Additionally, robustness assessments under parameter variations and inverter non-idealities are essential to validate the scheme’s reliability. Extending the approach to renewable energy and electric vehicle drives would further demonstrate its scalability, efficiency, and suitability for high-performance industrial applications.