Progress in Passive Silicon Photonic Devices: A Review

Abstract

Silicon photonics has emerged as a critical enabling technology for a diverse range of applications, from high-speed data communication and computing to advanced sensing and quantum information processing. This paper provides a comprehensive review of recent progress in the foundational passive devices that underpin this technological revolution. We survey the state of the art in fundamental building blocks, including strip, rib, and silicon nitride waveguides, with a focus on achieving ultra-low propagation loss. The review details essential components for light coupling and splitting, such as grating couplers, edge couplers, multimode interference couplers, and directional couplers, citing their typical performance metrics. Key wavelength filtering and routing components, including high-Q ring resonators, Mach–Zehnder interferometers, and arrayed waveguide gratings, are analyzed. Furthermore, we provide a comparative overview of the capabilities of major photonic foundries operating on a multi-project wafer model. The paper concludes by discussing persistent challenges in packaging and polarization management, and explores future trends driven by co-packaged optics, inverse design methodologies, and the expansion of silicon photonics into new application domains.

1. Introduction

1.1. The Imperative for Silicon Photonics in the AI and Zettabyte Era

The relentless expansion of the digital economy, propelled by the explosive growth of artificial intelligence (AI) [1], machine learning (ML) [2], cloud computing [3], and high-performance computing (HPC) [4], has created an unprecedented demand for data movement [5]. This surge in traffic, particularly within and between the massive data centers that form the backbone of modern computation, has pushed traditional copper-based electrical interconnects to their fundamental physical limits. As data rates climb, copper links face overwhelming challenges in bandwidth, power consumption, signal integrity, and physical density. This has created a critical bottleneck where data transfer, rather than data processing, becomes the primary constraint on system performance, especially for AI workloads that require massive, parallel data exchange between processors, memory, and storage.

Silicon photonics (SiPh) has emerged as a transformative technology to resolve this interconnect crisis. By using photons to carry information instead of electrons, SiPh leverages the intrinsic advantages of optical communication: much higher bandwidth, lower latency, significantly reduced power consumption per bit, and complete immunity to electromagnetic interference (EMI). In today’s “Zettabyte Era”, SiPh technology is more important than ever. The performance of AI systems, including the large language models behind generative AI, is directly held back by the hardware’s ability to handle data coming in and out. Indeed, over 90% of the inference operations in the neural networks foundational to these models are constrained by data transfer bottlenecks that silicon photonics is uniquely positioned to solve [6].

A pivotal factor accelerating the adoption of SiPh is its profound synergy with the mature Complementary Metal–Oxide–Semiconductor (CMOS) manufacturing ecosystem. This convergence allows for the fabrication of complex photonic integrated circuits (PICs) using the same high-volume, high-precision, and cost-effective processes developed over decades for the microelectronics industry. This manufacturability at scale is enabling a historic transition from discrete optical components to highly integrated systems on a chip, mirroring the evolutionary path of electronic integrated circuits [7]. As the technology matures, it is becoming the foundational platform not only for next-generation data centers and 5G/6G telecommunications but also for disruptive new applications in quantum computing, LiDAR for autonomous systems, and advanced biomedical and environmental sensing [8,9].

1.2. Passive vs. Active Devices in PICs

A photonic integrated circuit is a microchip that contains two or more photonic components to form a functioning circuit, manipulating light on a semiconductor substrate. These components can be broadly categorized into two classes: passive and active.

Passive optical components are devices that perform their function without requiring external power or active control. They are the fundamental pipes of a PIC, responsible for manipulating the flow of light through processes such as guiding, splitting, combining, filtering, and coupling. Examples include waveguides, which confine and direct light; couplers and splitters, which distribute optical power; and filters, which select specific wavelengths, as shown in Figure 1. These components are essential for managing and routing optical signals with minimal loss and interference, forming the foundational infrastructure upon which all other on-chip functionalities are built.

In contrast, active devices require an external power source to perform their function, which typically involves converting signals between the electrical and optical domains or actively modifying the properties of the light signal itself. This category includes modulators, which encode electrical data onto an optical carrier; photodetectors, which convert optical signals back into electrical ones; and light sources such as lasers and amplifiers.

This review will focus exclusively on the state of the art and recent progress in passive silicon photonic devices. While active components are critical for a complete system, the performance, efficiency, and scalability of any PIC are ultimately supported by the quality and sophistication of its passive device library.

1.3. Overview of the Review

This paper provides a comprehensive review of the recent progress in passive silicon photonic devices. Section 2 begins with the most fundamental building block, the optical waveguide, reviewing the primary architectures (strip, rib, SiN) and the advanced concept of sub-wavelength grating metamaterials. Section 3 examines the critical components for light coupling and splitting, detailing the performance of fiber-to-chip couplers and on-chip power splitters. Section 4 delves into devices for wavelength filtering and routing, including microring resonators, Mach–Zehnder interferometers, and arrayed waveguide gratings. Section 5 presents a comparative overview of the global fabrication landscape, introducing the multi-project wafer model and profiling the capabilities of major silicon photonics foundries. Section 6 discusses the persistent challenges facing the field, such as polarization management and packaging, and explores future trends including co-packaged optics, inverse design, and new applications in quantum and sensing. Finally, Section 7 provides a summary of the key findings and a concluding perspective on the field’s trajectory.

2. Fundamental Building Blocks: Waveguides for Light Confinement and Propagation

The optical waveguide is the most fundamental component in any photonic integrated circuit, serving as the channel for confining and propagating light across the chip. The performance of virtually all other passive and active devices is directly dependent on the properties of the underlying waveguide. The primary goal in waveguide design is to achieve low propagation loss while maintaining sufficient optical confinement to enable compact routing and device footprints. This section reviews the principal waveguide architectures that form the foundation of modern silicon photonics.

2.1. Conventional Silicon Waveguide Architectures on SOI

The silicon-on-insulator (SOI) platform is the most mature and widely used material system for silicon photonics. It consists of a thin crystalline silicon device layer on top of a thicker buried oxide (BOX) layer, which itself sits on a silicon handle wafer. The large refractive index contrast between the silicon core (n ≈ 3.47 at 1550 nm) and the silicon dioxide (SiO₂) cladding (n ≈ 1.45) enables strong light confinement [10].

2.2. Strip Waveguides

Strip waveguides, as shown in Figure 2a, are formed by fully etching through the silicon device layer to define a rectangular core, typically with sub-micron cross-sectional dimensions (e.g., 450–500 nm wide and 220 nm high for single-mode operation at 1550 nm) [11].

The primary advantage of this architecture is its extremely strong optical confinement. This high confinement allows for very tight bending radii, as small as a few micrometers, without significant radiation loss. This capability is critical for realizing highly compact devices, such as microring resonators with a large free spectral range (FSR), and for enabling dense integration of complex circuits on a single chip.

However, this strong confinement comes at a cost. The optical mode is tightly concentrated within the core, leading to significant interaction with the waveguide’s top, bottom, and sidewall interfaces. While the top and bottom surfaces are typically very smooth, the vertical sidewalls are defined by the etching process, which inevitably introduces roughness. This sidewall roughness is a major source of scattering, which is the dominant loss mechanism in strip waveguides. The scattering loss scales strongly with the refractive index contrast, making it particularly pronounced in the high-contrast SOI system.

Historically, propagation losses for strip waveguides were in the range of 1–3 dB/cm [12,13]. However, continuous improvements in lithography and etching processes have led to significant reductions. More recent work on standard 220 nm SOI platforms has demonstrated propagation losses for transverse-electric (TE) polarized light of 2.4 dB/cm [14]. Furthermore, research has shown that operating at longer wavelengths can reduce loss; a record-low propagation loss of approximately 0.2 dB/cm was achieved for a 700 nm wide single-mode strip waveguide operating in the 2 µm wavelength band. This improvement is attributed to the weaker optical field intensity at the waveguide sidewalls at longer wavelengths compared to the standard 1550 nm band [15].

2.3. Rib Waveguides

Rib waveguides are designed to directly address the challenge of sidewall scattering loss. In this architecture, the silicon device layer is only partially etched, leaving a thinner slab of silicon on either side of the central, thicker guiding region [16]. This geometry alters the mode profile, allowing the optical field to spread laterally into the un-etched slab regions [17]. Consequently, the mode’s overlap with the rough, vertically etched sidewalls is significantly reduced, leading to a dramatic decrease in propagation loss, as shown in Figure 2b.

The primary advantage of the rib waveguide is its potential for ultra-low loss. The trade-off for this reduced loss is weaker optical confinement compared to a strip waveguide. This weaker confinement necessitates much larger bending radii, typically in the range of tens of micrometers or even millimeters to prevent excessive radiation loss [18]. This limits the ultimate integration density achievable with rib waveguide-based circuits.

The performance of rib waveguides has seen remarkable progress, with reported losses moving from the dB/cm to the dB/m regime, a critical achievement for applications requiring long optical paths like delay lines, gyroscopes, and ultra-high-Q resonators. Early work on shallow-ridge waveguides on 250 nm SOI achieved an average propagation loss of 0.274 dB/cm using standard lithography and dry etching, a figure that was state-of-the-art at the time [11]. A key strategy for further loss reduction is to use thicker SOI wafers and a very shallow etch. By fabricating rib waveguides on a 500 nm thick SOI platform with a rib height of only ~10% of the total silicon thickness (a 56 nm etch), researchers have demonstrated propagation losses as low as 4 dB/m (0.04 dB/cm) [16]. An alternative fabrication approach involves using anisotropic wet etching with chemicals like tetramethylammonium hydroxide (TMAH). This process selectively etches crystal planes, resulting in waveguide sidewalls that are atomically smooth. This technique has been used to achieve propagation losses of 0.85 dB/cm for TE polarization and 1.08 dB/cm for TM polarization [10].

This evolution highlights a fundamental trade-off in waveguide design between optical confinement and propagation loss. While strip waveguides prioritize density and rib waveguides prioritize low loss, advanced fabrication techniques are continuously mitigating this trade-off, enabling complex, large-scale PICs that require both low loss and reasonable compactness.

2.4. The Silicon Nitride (SiN) Platform: A Key Alternative

While SOI is the dominant platform, silicon nitride (SiN) has emerged as a powerful and complementary material for passive photonic devices, as shown in Figure 2c. SiN is a dielectric material that is fully compatible with CMOS fabrication processes and offers a unique set of properties that make it highly attractive for specific application [19]. It has a moderate refractive index of approximately 2.0, which provides good confinement when cladded with SiO₂ while being less sensitive to fabrication imperfections than the higher-contrast silicon system [20].

The key advantages of the SiN platform are its ultra-low propagation loss, broad transparency window, and high-power handling. SiN waveguides are renowned for their exceptionally low propagation losses, which are now routinely in the dB/m range [21]. This is primarily due to the lower refractive index contrast, which reduces scattering from sidewall roughness, and the high quality of SiN films deposited via processes like Low-Pressure Chemical Vapor Deposition (LPCVD). Recent demonstrations have reported losses as low as 0.045 dB/m [22], 1.4 dB/m [23], and, after high-temperature annealing to drive out hydrogen impurities, an astonishing 0.06 dB/cm [24]. Foundries like AIM Photonics now target SiN waveguide losses of below 1 dB/cm in their standard processes [25,26].

Unlike silicon, which becomes opaque below ~1.1 µm, SiN is transparent over a very wide wavelength range, from the visible (~400 nm) to the mid-infrared. This makes it an ideal platform for applications outside the traditional telecom bands, such as visible-light photonics for quantum information and displays, or MIR sensing [27]. Furthermore, SiN exhibits negligible two-photon absorption at telecom wavelengths, a nonlinear effect that can be a limiting factor in silicon waveguides. This property allows SiN devices to handle much higher optical powers, making them the platform of choice for nonlinear applications like frequency comb generation and parametric amplification [19].

A significant challenge in SiN photonics has been the high intrinsic tensile stress of the films, particularly for the thick layers (≥600 nm) required for dispersion engineering in nonlinear applications. This stress can lead to film cracking and wafer bowing, especially on large 300 mm wafers. A breakthrough solution to this problem is the photonic Damascene process [28]. In this method, instead of depositing SiN and then etching it, trenches are first etched into the SiO₂ cladding. SiN is then deposited to fill these trenches, and the excess is removed via chemical mechanical planarization (CMP). This process effectively mitigates the stress issue, enabling the fabrication of ultra-low-loss, thick SiN waveguides on large-scale wafers. As shown in Figure 3, the photonic Damascene process has been demonstrated to enable the high-yield, wafer-scale fabrication of high-performance, dispersion-engineered SiN photonic circuits with ultra-low loss [29]. In conclusion,

Table 1. Waveguide performance on Si and SiN platform.

Ref	Loss (dB/cm)	Wavelength	Platform	Bend Loss (dB)	Core Thickness	Wafer Size (inch)	Polarization Handling
[24]	0.06	Cband	SIN	NA	730 nm	4	TE
[21]	0.34	Oband	SIN	0.018 for 50 μm	NA	NA	TE
[11]	0.274 ± 0.008	Cband	SOI	<10−4 for 100 μm	250 nm	6	TE
[28]	0.055	Cband	SIN	NA	870 nm	NA	TE/TM
[23]	0.014 @1.55 μm	Cband	SIN	NA	720 nm	4	TE
[12]	TE: 3.6 ± 0.1 @1.5 μm, TE: 6.8 ± 0.2 @1.3 μm, TM: 3.5 ± 0.1 @1.3 μm	1.2–1.7 μm	SOI	0.086 ± 0.005 for 1 μm, 0.013 ± 0.005 for 2 μm	220 nm	8	TE/TM
[19]	0.157 @1.55 μm, 0.06 @1.58 μm	1.49–1.58 μm	SIN	0.013 for 50 μm, 0.0095 for 80 μm	400 nm	8	TE/TM
[13]	2.01 ± 0.231	Cband	SOI	0.05 ± 0.005 for 30 μm	50 nm	6	TE
[22]	0.00045	1.58–1.61 μm	SIN	NA	50 nm	NA	TE
[16]	0.16	C + L band	SOI	NA	500 nm	NA	TE

provides a summary of the key performance metrics for each Si and SiN waveguide.

2.5. Advanced Waveguide Engineering: Sub-Wavelength Grating (SWG) Metamaterials

Sub-wavelength grating (SWG) waveguides represent a paradigm shift in device design, moving from using silicon as a simple wave-guiding medium to engineering its properties at a sub-wavelength scale to create an artificial optical material or metamaterial [30,31,32]. An SWG waveguide consists of a periodic arrangement of silicon segments interleaved with a low-index material (like the SiO₂ cladding), where the period of the grating, or pitch (Λ), is small enough to suppress diffraction effects. For light propagating along the grating, if the pitch is below the Bragg condition ($\mathsf{\Lambda }<{\displaystyle \frac{{\mathsf{\lambda }}_0}{2{\mathrm{n}}_{eff}}}$), the structure behaves not as a series of discrete scatterers but as a continuous, homogeneous waveguide with unique, engineered properties.

The key characteristic of SWGs is the ability to achieve index engineering. By intentionally designing the geometry of the sub-wavelength segments, the effective refractive index of the equivalent metamaterial can be precisely controlled. The periodic structure is inherently anisotropic, meaning its effective refractive index is different for electric fields oscillating parallel or perpendicular to the grating segments. This engineered anisotropy provides an extra degree of freedom unavailable in conventional solid-core waveguides.

This design flexibility has enabled breakthrough performance and novel functionalities across a wide range of passive devices. SWGs are used to create ultra-broadband and highly efficient fiber-to-chip couplers with low polarization dependence [33]. SWG-based MMI [34] and directional couplers [35] can also be made more compact and can operate over much wider bandwidths than their conventional counterparts. Furthermore, the engineered anisotropy of SWGs is ideal for creating compact and efficient polarization splitters and rotators [36]. SWGs also allow for precise control over the waveguide’s group velocity dispersion, a critical parameter for nonlinear optics and for compensating dispersion in communication links.

This approach marks a conceptual leap from geometric optics to metamaterial engineering on a chip. Instead of being constrained by the intrinsic properties of bulk silicon, designers can now synthesize a material with the exact optical properties required for a specific application. While introducing nanoscale features, these waveguides can maintain low propagation losses comparable to standard strip waveguides, with values around 3.7 dB/cm reported for metamaterial-clad structures designed to reduce crosstalk [37].

3. Light Coupling and Splitting: The Interface to and Within the Chip

Efficiently coupling light from an external source, typically a single-mode optical fiber, onto the photonic chip and subsequently distributing that light to various functional blocks are fundamental requirements for any PIC. The performance of these coupling and splitting components directly impacts the overall insertion loss and power budget of the entire system. This section reviews the state of the art in fiber-to-chip couplers and on-chip power splitters.

3.1. Fiber-to-Chip Couplers

A significant challenge in silicon photonics is bridging the immense size mismatch between the mode field diameter of a standard single-mode optical fiber (~9–10 µm) and that of a sub-micron silicon waveguide (~0.5 µm). Two primary strategies have been perfected to address this challenge: grating couplers and edge couplers.

3.1.1. Grating Couplers (GCs)

Grating couplers are periodic structures, such as etched lines in the silicon waveguide, that act as a diffraction grating. They are designed to scatter light out of the plane of the chip at a specific angle that matches the acceptance angle of an optical fiber positioned vertically above it [38]. A key advantage of this out-of-plane coupling scheme is that it allows for testing at any point on a wafer’s surface without requiring the wafer to be diced. This makes GCs ideal for high-throughput, wafer-scale characterization of devices during R&D and manufacturing [39].

The performance of GCs is defined by their coupling efficiency (CE) and optical bandwidth. Historically, the CE of simple GCs was limited to around 30–40% (−5 to −3 dB) due to two primary loss mechanisms: back-reflection into the waveguide and power leakage downwards into the silicon substrate. Modern GC design has largely overcome these limitations through sophisticated engineering. Techniques include adding a bottom reflector (e.g., a metal layer or a distributed Bragg reflector) to redirect substrate-bound light upwards, and apodizing the grating (varying the etch depth or duty cycle along its length) to shape the diffracted beam into a more Gaussian-like profile that better matches the fiber mode. More recently, inverse design methods have been used to create non-periodic “meta-gratings” that achieve unprecedented performance. State-of-the-art designs have demonstrated experimental CEs of 78% (1.08 dB) [40] and 81.57% (1.76 dB) [41]. For polarization-diverse applications, two-dimensional (2D) GCs have been developed, with a recent foundry-compatible design achieving a measured CE of 2.54 dB (56%) [42].

Standard uniform GCs are inherently wavelength-sensitive, typically having a 1 dB bandwidth of 30–40 nm. However, advanced designs that engineer the grating’s dispersion can significantly broaden this operational window. Bandwidths of 80–90 nm (1 dB) [39] and 92 nm (3 dB) [41] are now achievable. While most GCs are on SOI, SiN platforms are also used. The lower index contrast of SiN results in weaker grating strength and typically lower CE. However, hybrid platforms that use an amorphous silicon or polysilicon overlay on top of the SiN waveguide can enhance the grating strength, enabling CEs approaching 1 dB [43].

3.1.2. Edge Couplers (ECs)

Edge couplers facilitate in-plane coupling, where the optical fiber is brought to the polished facet of the chip. The core component of an EC is a mode-size converter, most commonly an inverted taper. This is a section of the waveguide that gradually narrows towards the chip facet. As the waveguide width decreases, the optical mode becomes less confined and expands in size, allowing for a much better mode-field overlap with the larger mode of the optical fiber [44].

Edge couplers are renowned for their superior performance in terms of efficiency and bandwidth. ECs can achieve near-unity coupling efficiency. By using multiple stacked tapers or multi-tip structures to precisely shape the output mode in both the horizontal and vertical dimensions, losses can be minimized, as shown in Figure 4. Recent demonstrations on the SiN platform have achieved simulated CEs of over 90% across a 1000 nm wavelength range (1000–2000 nm) and a record-high measured CE of 97.1% (−0.13 dB) [45]. On other platforms like thin-film lithium niobate (TFLN), CEs of −1.52 dB (70%) are reported [46]. Furthermore, a major advantage of ECs is their inherently ultra-broad bandwidth and low polarization dependence compared to GCs [45]. A 1 dB bandwidth of over 270 nm has been demonstrated [47], and polarization-dependent loss (PDL)—the difference in coupling loss between TE and TM polarizations—can be as low as < 0.17 dB [48]. Moreover, power handling that can be as high as 520 mW with <0.6/0.8 dB TE/TM insertion loss has been demonstrated recently [49].

The historical trade-off between the wafer-scale testing convenience of GCs and the superior performance of ECs is rapidly diminishing. As both architectures converge towards high efficiencies, the choice of coupler is becoming less about a performance compromise and more about a system-level design choice dictated by packaging and testing strategy, as shown in

Table 2. Optical I/O: the edge coupler and grating coupler performance.

Ref	Type	Coupling Eff. per Facet (dB)	Wavelength	Platform	Mode
[46]	Bident EC	1.52 @1.55 μm	Cband	TFLN	TE/TM
[42]	2D GC	2.54	1510–1560 nm	SOI	TE
[45]	Double-tip EC	0.12/0.9 for TE/TM	1070–1830 nm	SIN	TE/TM
[47]	3D multi-tip EC	0.0682/0.0958 for TE/TM @1.55 μm	Cband	TFLN	TE/TM
[38]	GC	0.97/1.05 for TE/TM	Cband	TFLN	TE/TM
[48]	3D EC	0.29/0.24 for TE/TM	1490–1670 nm	TFLN	TE/TM
[41]	Vertical metal GC	2.77/2.55 for TE/TM	Cband	SOI	TE/TM
[44]	Double-tip EC	1.52/2 for TE/TM	Oband	SOI	TE/TM
[49]	EC	0.6/0.8 for TE/TM	Oband	SIN	TE/TM

. This convergence is a hallmark of a maturing technology platform.

3.2. On-Chip Power Splitters and Routers

Once light is on the chip, it must be divided and routed to different functional units. The primary components for this task are Y-branches, multimode interference couplers, and directional couplers.

3.2.1. Y-Branch Splitters

The Y-branch is the simplest and one of the most robust power splitters, consisting of a single input waveguide that symmetrically bifurcates into two output waveguides [51]. While conventional Y-branches with a sharp, wide-angle split suffer from significant optical radiation loss, modern designs have largely mitigated this issue. By using a very gradual, adiabatic split or by inserting a specially designed mode-evolution region at the junction, excess loss (the loss beyond the ideal 3 dB split) can be made negligible.

An optimized silica-on-silicon Y-branch using a tapered multimode section reported an excess loss of just 0.12 dB [52]. A design on SiN, optimized for low-loss quantum applications, achieved a loss of <0.1 dB [53]. Additionally, a power splitter based on adiabatically tapered rib waveguides, which functions as a mode evolution Y-branch, demonstrated an exceptionally low excess loss of 0.06 dB [54].

3.2.2. Multimode Interference (MMI) Couplers

MMI couplers are based on the self-imaging principle. Light from one or more input waveguides enters a much wider multimode waveguide section. Within this section, the various excited modes propagate at different phase velocities, interfering with each other. At specific lengths along the MMI section, the interference pattern reproduces one or more images of the input field at the output waveguides [55]. MMI devices are prized for their compact size, broad optical bandwidth, and high tolerance to fabrication variations. As shown in Figure 5, a Si-based 4 × 4 MMI was demonstrated with 100G channel width, high channel uniformity with less than 1 dB excess loss, and 12.7 dB crosstalk in [56].

Recent low-loss 2 × 2 MMI couplers fabricated on a SiN platform achieved a measured insertion loss of only 0.07 dB at 1310 nm, with loss remaining below 0.25 dB across the entire O-band [57]. A 1 × 4 MMI splitter on SiN reported a similarly low insertion loss of 0.13 dB [55].

3.2.3. Directional Couplers (DCs)

A directional coupler consists of two parallel waveguides placed in close proximity. Their evanescent fields overlap, allowing power to be gradually transferred from one waveguide to the other. The amount of power transferred (the coupling ratio) depends sensitively on the interaction length, the gap between the waveguides, and the wavelength [54].

While this wavelength sensitivity can be a drawback, it can also be exploited for wavelength-division multiplexing. Moreover, recent advanced designs have focused on overcoming this limitation to create broadband splitters with tailorable coupling ratios. By using bent directional couplers, where the waveguides are curved instead of straight in the coupling region, the wavelength dependence can be significantly flattened. A bent DC on a SiN platform demonstrated a 1 dB bandwidth of 80 nm [20]. Similarly, a broadband directional coupler with an optimized arc-shaped waveguide demonstrated a low excess loss of 0.272 dB. This design maintained a tapping ratio deviation of only 1.433% from the 1550 nm value across the 1470 nm to 1630 nm wavelength range [54], as shown in Figure 6. Furthermore, by using SWG waveguides to form the coupler, the dispersion properties can be engineered to achieve an extremely flat spectral response. A recent SWG-based DC showed an average excess loss of less than 0.24 dB and a coupling ratio variation of less than ±1 dB over an unprecedented 170 nm bandwidth, completely covering the C, L, and U telecommunication bands [58].

This evolution in splitter design, from simple geometries to more physically sophisticated structures using mode evolution and metamaterial engineering, reflects a deeper understanding of the underlying wave optics. Designers are no longer simply accepting the limitations of basic shapes but are actively manipulating light propagation to achieve the robust, broadband, and fabrication-tolerant performance required for complex, next-generation PICs, as shown in

Table 3. Couplers: Y-brand, MMI, and DC performance.

Ref	Type	Coupling Efficiency per Facet (dB)	Wavelength	Platform	Mode
[20]	DC	0.25	1510–1590 nm	SIN	TE
[55]	1 × 4 MMI	0.13	Oband	SIN	TE
[58]	DC	0.24	C + L + Uband	SOI	TE
[57]	2 × 2 MMI	0.07 @1.31 μm	Oband	SIN	TE
[54]	DC	0.272 @1.55 μm	S + C + Lband	SOI	TE
[36]	DC	0.42/0.28 for TE/TM	C + Lband	SOI	TE/TM
[53]	Y-BRANCH	0.1 @808 nm	760–860 nm	SIN	TE
[52]	Y-BRANCH	0.06 @1.55 μm	1400–1565 nm	SOI	TE/TM
[34]	2 × 2 MMI	0.08 @1.55 μm	Cband	SOI	TE
[35]	DC	0.1 @2 μm	1.95–2.02 μm	SOI	TE

.

4. Wavelength Filtering and Routing: Manipulating the Spectrum

Beyond guiding and splitting light, a critical function of passive photonics is to manipulate the spectral content of the optical signal. Wavelength-selective components are the building blocks for wavelength-division multiplexing (WDM) systems, which dramatically increase the data capacity of a single optical fiber by transmitting multiple data channels on different colors of light. These components are also fundamental to on-chip spectroscopy for sensing and are used to build tunable lasers and other advanced devices.

4.1. Resonant Structures: Microring Resonators (MRRs)

Microring resonators are one of the most versatile and widely used components in silicon photonics. An MRR consists of a closed-loop waveguide, often in the shape of a ring or a “racetrack” with straight sections, that is placed in close proximity to one or two straight “bus” waveguides [59,60,61]. Light from an input bus waveguide couples evanescently into the ring. It then circulates within the resonator, and resonance occurs when the round-trip path length of the ring is an integer multiple of the wavelength of the light. At these specific resonance wavelengths, light builds up within the cavity, leading to a sharp drop in transmission at the through-port and a corresponding peak at the drop-port (in an add-drop filter configuration).

The performance of an MRR is defined by two key metrics: Quality Factor (Q-factor) and Free Spectral Range (FSR). The Q-factor is a measure of the sharpness of the resonance peak, defined as the ratio of the resonance wavelength to its full width at half-maximum (FWHM) linewidth (Q = λres/ΔλFWHM). A high Q-factor signifies low loss within the cavity and a long photon lifetime, which is essential for creating narrow-band filters, highly sensitive sensors, and low-threshold nonlinear devices. The intrinsic Q-factor is fundamentally limited by the propagation loss of the waveguide forming the ring. On standard SOI platforms, fabrication techniques like local oxidation of silicon (LOCOS), which avoids plasma etching of the waveguide, have enabled intrinsic Q-factors of ~2 million [62]. On the ultra-low-loss SiN platform, Q-factors have reached even more extraordinary levels, with demonstrations of 17 million [63] and a record 45.7 million being reported [64]. A significant recent advancement in integrated photonics is an all-waveguide Si₃N₄ resonator with a record-high intrinsic Q-factor of 422 million at 1570 nm, as shown in Figure 7. This performance is achieved by carefully reducing scattering and absorption losses, resulting in a corresponding linear loss of just 0.060 dB/m—the lowest reported to date for this type of device [65]. This ultra-high-Q capability is also being extended to other wavelength bands; for mid-infrared (MIR) applications, SiGe-on-silicon ring resonators have recently achieved Q-factors of 1 million [66].

The FSR is the wavelength spacing between adjacent resonance peaks. It is inversely proportional to the total optical path length of the ring, given by the equation $FSR={\displaystyle \frac{n_{g}L}{{\lambda }^2}}$, where L is the physical length of the ring and ng is the group index of the waveguide mode. A large FSR is often desirable to ensure that only one resonance peak falls within the communication band of interest, avoiding ambiguity. The FSR is primarily controlled by the ring’s radius. To achieve a large FSR for applications like coarse WDM, very small rings are required. For example, a compact ring on a TFLN platform with an equivalent radius of just 15 µm achieved a large FSR of 10.36 nm [67]. Conversely, for applications requiring very fine channel spacing, large rings are used. As designers seek to balance these competing requirements, a variety of trade-offs emerge between key metrics such as Q-factor, loss, and FSR. These trade-offs, and how different research efforts have addressed them, are summarized in

Table 4. Filters: mircroring resonator performance.

Ref	Q	Loss (dB/cm)	FWHM	Radius	FSR	Wavelength	Platform	Mode
[65]	422 M	0.0006	906 kHz	11.787 mm	2.713 GHz	1.55–1.65 μm	SIN	TE
[62]	2 M	0.3	1.8 pm	50 μm	2 nm	Cband	SOI	TE
[64]	45.7 M	0.018	0.1 pm (12.5 MHz)	* 100 μm–4 mm	0.52 nm	Cband	SIN	TE/TM
[15]	2 M	0.25	1.76 pm	** 39 μm	0.6 nm	2–2.4 μm	SOI	TE
[63]	17 M	0.021	0.28 pm (35 MHz)	100 μm	25 GHz	1.52–1.6 μm	SIN	TE/TM
[66]	1.01 M	0.15	0.5–1.5 MHz	250 μm	NA	3.5–4.6 μm	SIGE	TE
[67]	48 K	8.5	0.07 nm (8.8 GHz)	15 μm	10.36 nm	1.5–1.6 μm	LNOI	TE

* Euler bends gradual width change. ** Effective Euler bends radius.

. A key innovation for improving device yield is the design of FSRs that are insensitive to fabrication variations. This can be achieved by constructing the ring from two sections of waveguide with different widths, engineered such that their group index sensitivities to width variations cancel each other out [68].

4.2. Interferometric Devices: Mach–Zehnder Interferometers (MZIs)

The Mach–Zehnder interferometer is another fundamental building block for spectral filtering. A basic MZI splits an input optical signal into two separate arms, introduces a path length difference between them, and then recombines them [69]. The phase difference accumulated due to the path length difference causes wavelength-dependent constructive and destructive interference at the output, resulting in a sinusoidal transmission spectrum. MZIs are widely used as optical filters and (de)multiplexers. They also form the basis of most thermo-optic switches and high-speed electro-optic modulators, where the phase in one or both arms is actively controlled.

The Extinction Ratio (ER) is a key performance metric for filtering applications, as it measures the ratio of maximum to minimum transmission and is critical for rejecting unwanted signals. While a single MZI has a sinusoidal response, more complex, box-like filter shapes with high ER can be achieved by cascading multiple MZIs or by coupling MRRs to the MZI arms. A recent demonstration of four cascaded MZI-coupled resonators on a SiN platform achieved an experimental extinction ratio of 35 dB [70].

A major challenge for silicon-based interferometric devices is their high sensitivity to temperature, a consequence of silicon’s large thermo-optic coefficient (~1.86 × 10⁻⁴/K). A temperature change will alter the refractive index and thus the phase in the MZI arms, causing the filter spectrum to drift. A breakthrough solution to this problem is the athermal MZI [71]. In this design, one arm of the interferometer is made from a silicon waveguide, while the other arm is made from a SiN waveguide. Since SiN has a much smaller and positive thermo-optic coefficient, the lengths of the two arms can be chosen to precisely balance out the phase shifts induced by temperature changes. This approach has been shown to reduce the thermal wavelength drift by a factor of 24 compared to an equivalent all-silicon MZI, making the device robust to environmental temperature fluctuations. This shift in focus from achieving peak performance to ensuring robust performance is a sign of the technology’s maturation towards commercial deployment.

4.3. Channel Demultiplexing: Arrayed Waveguide Gratings (AWGs)

For applications requiring the separation of many closely spaced wavelength channels, such as in dense WDM (DWDM) systems, the arrayed waveguide grating is the device of choice [72]. An AWG functions like an on-chip prism. It consists of two free-propagation regions (also called star couplers) connected by an array of channel waveguides. Each waveguide in the array has a slightly different length, with a constant length increment between adjacent waveguides.

Light from a single input waveguide enters the first free-propagation region and is distributed among all the arrayed waveguides. As the light propagates through the array, the length difference introduces a wavelength-dependent phase shift. At the second free-propagation region, these phase-shifted beams interfere and focus at different spatial positions depending on their wavelength. A set of output waveguides is placed at the focal plane to collect the separated wavelength channels.

AWGs are capable of high performance, with key metrics being insertion loss, crosstalk, and channel uniformity. State-of-the-art AWGs demonstrate very low loss and excellent channel isolation. A SiN AWG operating in the visible spectrum (760 nm) achieved an insertion loss of less than 0.5 dB and crosstalk below −23 dB [73]. In the 2 µm band, silicon AWGs have been demonstrated with an on-chip loss of 0.5 dB and crosstalk of −30.2 dB [74]. Even very high-channel-count devices, such as a 64-channel AWG with 50 GHz spacing, have been realized with a total on-chip loss of ~5 dB [75].

A persistent challenge in AWG design is the channel non-uniformity, where the outer channels inherently have higher loss than the central channels due to the diffraction envelope of the star coupler. This can be a significant issue in systems where all channels must have similar power levels. A recent innovation to address this is the use of passive silicon nanowires placed in the gaps between the arrayed waveguides at the input to the free-propagation region. These nanowires modify the field distribution, flattening the diffraction envelope and dramatically improving uniformity. This technique was shown to improve the non-uniformity of a 16-channel AWG from 1.6 dB down to 0.63 dB without introducing any additional insertion loss [72]. In addition,

Table 5. Filters: array waveguide gratings (AWG) performance.

Ref	# of Channels	Loss (dB)	Channel Spacing	Crosstalk	Wavelength	Platform	Mode
[72]	8&16	8 CHs: 6.26, 16 CHs: 10.1	200 GHz	NA	Cband	SOI	TE
[56]	4	0.66	100 GHz	9.6	Oband	SOI	TE
[74]	8	0.5	1.85 nm	30.2	1.88–2.02 μm	SOI	TE
[73]	8	0.5	0.5 nm	23	centered@ 760 μm	SIN	TE
[75]	64	5	0.7 nm	10	1.967–2.012 μm	SOI	TE

provides a summary of the key performance metrics for each design.

5. Foundry Comparison for Fabrication

The remarkable progress in silicon photonic device performance and complexity has been enabled by a corresponding maturation of the manufacturing ecosystem. The high capital cost of a semiconductor fabrication facility makes it prohibitive for most research groups and startup companies to own their own fab. The solution to this has been the adoption of the foundry model, which has democratized access to state-of-the-art fabrication and has been a critical catalyst for innovation.

5.1. The Multi-Project Wafer (MPW) Model

The shift to larger wafer sizes, from 200 mm to 300 mm, is a critical step for manufacturability and cost reduction. Larger wafers allow for a greater number of chips to be fabricated in a single run, which directly lowers the cost per chip, a crucial factor for moving from a research-and-development environment to high-volume manufacturing. While some foundries still operate on 200 mm wafers, the industry trend is moving toward 300 mm, a standard widely adopted by the microelectronics industry. The availability of multiple foundries and the compatibility of their platforms are also key to market growth. While each foundry has its own unique process design kit (PDK), which defines the available components and design rules, standardization efforts are underway to enable greater interoperability and a more robust supply chain. This is vital for ensuring that a design can be easily ported between different fabrication facilities, reducing reliance on a single source.

The Multi-Project Wafer (MPW) service is the cornerstone of the fabless silicon photonics ecosystem [76]. In an MPW run, multiple users—from university research groups to small- and medium-sized enterprises—can purchase a portion of the area on a single wafer. These different projects share the significant costs of the photomask set and the wafer processing, dramatically reducing the financial barrier to entry for prototyping and low-volume production [25,76,77].

This model, as shown in Figure 8, has been instrumental in transforming silicon photonics from a specialized research field into a broadly accessible technology with a clear path to commercialization. By providing regular, scheduled access to a standardized and well-characterized process flow, the MPW model allows designers to fabricate and test their ideas quickly and affordably. Organizations such as ePIXfab in Europe and CMC Microsystems in North America, in partnership with research institutes and foundries, coordinate these shuttle runs, providing a vital service to the community.

5.2. Comparative Overview of Major Foundries

A number of research institutes and commercial semiconductor foundries now offer silicon photonics MPW and dedicated wafer services. Each has a unique platform with distinct capabilities, process flows, and device libraries, catering to different applications and markets. The following provides a comparative overview of several leading foundries.

AIM Photonics: Positioned as a U.S.-based national hub for integrated photonics, AIM Photonics operates an open-access R&D and manufacturing facility focused on 300 mm wafers. Its key strength lies in providing a comprehensive and flexible MPW platform that accelerates the lab-to-fab transition [25]. The platform includes five distinct process technologies: Active, Passive, Low-Loss Active, Sensor, and the specialized Quantum Flex (QFlex) for quantum applications. A unique feature is the offering of “bite-size custom” process modifications, allowing designers to make minor changes to the standard flow for an additional fee, a level of flexibility not typically available at high-volume commercial foundries. The platform integrates silicon, silicon nitride (including thick films >700 nm via a Damascene process for nonlinear optics), and germanium for detectors, targeting applications from datacom and LiDAR to sensing and quantum computing [27].

IMEC: A world-leading research and innovation hub in nanoelectronics based in Belgium, imec offers one of the most advanced and comprehensive silicon photonics platforms, known as iSiPP. Services are available on both 200 mm and 300 mm wafers and include prototyping via MPW runs and volume production partnerships [78,79,80]. The platform is offered in several flavors, including the simplified iSiPP50G for transceivers operating at 50 Gb/s and beyond, and the full-featured iSiPP200.75. Key process features include a 220 nm SOI starting substrate, multi-level silicon and polysilicon patterning, germanium epitaxy for high-speed photodetectors, and two levels of copper metallization. A major recent upgrade is the co-integration of high-quality, low-loss SiN waveguides without degrading the performance of active devices. Furthermore, imec offers advanced heterogeneous integration capabilities, including the flip-chip bonding of III-V lasers and micro-transfer printing of materials like lithium niobate (LNO) [81].

TSMC (Taiwan Semiconductor Manufacturing Company): As the world’s largest semiconductor foundry, TSMC’s entry into silicon photonics signifies the technology’s industrial maturity. TSMC offers a high-volume SiPh platform on 300 mm wafers, built upon its mature 65 nm CMOS process technology [82,83,84]. The company’s focus is on large-scale production and advanced packaging solutions to meet the demands of the HPC and AI markets. A key offering is the Compact Universal Photonic Engine (COUPE™), a technology that enables the 3D stacking of photonic ICs (PICs) with electronic ICs (EICs), which is essential for co-packaged optics. Their platform includes low-loss SiN waveguides fabricated with a low-temperature (<400 °C) PECVD process, making them compatible with back-end-of-line (BEOL) integration with the CMOS electronics.

GlobalFoundries (GF): GF provides a highly differentiated platform, GF Fotonix™, which monolithically integrates silicon photonics with its RF-CMOS process technology (e.g., 45SPCLO based on 45 nm SOI) [7,85,86]. This allows for the fabrication of both photonic devices and high-performance radio frequency electronics on the same chip. The platform is highly flexible, offering a photonics-only flow as an alternative to the full RF-photonic integration. The second generation of GF Fotonix supports data rates of 200 G per wavelength and includes upgrades to all active devices. GF is also investing heavily in full turnkey solutions, including onshore advanced packaging and testing, to provide customers with a secure and complete supply chain from chip fabrication to the final packaged product. The platform includes SiN for power handling and through-silicon vias (TSVs) for 3D stacking.

Tower Semiconductor: Tower offers its PH18 silicon photonics platform, which is promoted as an “open” foundry service available to all customers for prototyping and volume production on 200 mm wafers [87,88]. This platform is designed to complement Tower’s strong offerings in specialty analog processes like SiGe BiCMOS, providing a combined electronic–photonic solution for customers. The PH18 platform features low-loss silicon and silicon nitride waveguides, integrated germanium photodiodes (PIN and avalanche), and efficient heaters for thermal tuning. A key strength is its comprehensive design enablement, with process design kits (PDKs) supported by all major electronic design automation (EDA) vendors, including Ansys, Cadence, and Synopsys. The platform primarily targets the O-band and C-band data center interconnect market, as well as telecom and sensing applications. The summary table is shown in

Table 6. Summary of representative SiPh foundry platforms.

Foundry	Platform Highlights	Key Materials	Process Node(s)/Wafer Size
AIM Photonics	US-based open-access R&D hub; Comprehensive MPW platform (Active, Passive, Low-Loss, Sensor, QFlex); “Bite-size” process customization.	Si, SiN (incl. thick film), Ge	90 nm/45 nm base on 300 mm
IMEC	iSiPP platforms (iSiPP50G, iSiPP200); Advanced co-integration of SiN; Heterogeneous III-V/LNO integration via flip-chip/micro-transfer printing.	Si, poly-Si, SiN, Ge, III-V (InP), LNO	130 nm base on 200 mm, 300 mm
TSMC	High-volume 65 nm SiPh process; COUPE™ advanced packaging for 3D stacking; Fully automated wafer-level testing (EWAT/OWAT).	Si, SiN (low-temp PECVD)	65 nm on 300 mm
GlobalFoundries	GF Fotonix™ platform; Monolithic RF-CMOS integration; Turnkey solutions including advanced packaging; 200 G/λ capable.	Si, SiN, Ge	90 nm, 45 nm on 200 mm/300 mm
Tower Semiconductor	PH18 “open” foundry platform on 200 mm; Complements SiGe BiCMOS processes; Strong PDK support from major EDA vendors.	Si, SiN, Ge	180 nm base on 200 mm

This table provides a general overview of silicon photonics foundry capabilities and should be used for reference only. Please note that the specifications and offerings are subject to change. For the most up-to-date and representative information, it is essential to consult the official process design kits (PDKs) and documentation from each foundry, as their state-of-the-art technologies are constantly evolving.

.

5.3. Integration with Active Devices: Approaches for System-Level Functionality

While this review focuses on the foundational passive components that form the backbone of a photonic integrated circuit, a complete system requires the integration of active devices that can modulate, detect, and generate light. The integration of these active components—such as modulators, photodetectors, lasers, and amplifiers—onto the passive silicon platform is a major challenge and a critical area of ongoing research. Three primary approaches are used to achieve this system-level functionality: monolithic, heterogeneous, and hybrid integration.

5.3.1. Monolithic Integration

Monolithic integration involves fabricating both the electronic and photonic devices on a single silicon substrate using a single, unified process flow. This approach is highly compatible with the mature CMOS manufacturing ecosystem [85]. It is particularly well-suited for high-speed modulators [89] and photodetectors [90], which can be formed using doped silicon and germanium. For example, silicon’s Pockels effect is weak, but its high plasma dispersion effect allows for the creation of efficient modulators. Germanium, with its high absorption at telecom wavelengths, can be epitaxially grown on silicon to create high-speed photodetectors. This method offers the potential for very low power consumption and high-density integration because the electrical interconnects between the electronic and photonic components are kept extremely short. This approach also simplifies packaging, as there are no separate chips to align. A key challenge remains in the lack of a native silicon-based laser source, as silicon is an inefficient light emitter due to its indirect bandgap. However, efficient laser-to-SiPh-circuit butt-coupling with optical power up to 20 mW was demonstrated through wafer- and module-level characterizations [91].

5.3.2. Heterogeneous Integration

To overcome the light source limitation, heterogeneous integration allows for the bonding of III-V semiconductor materials (such as InP and GaAs, which are efficient light emitters) directly onto SOI wafer [92]. The III-V material is typically grown on its native substrate and then transferred and bonded to the passive silicon waveguide layer using a process like wafer bonding. The transferred material is then patterned to create active devices like lasers, semiconductor optical amplifiers (SOAs), and modulators. This technique leverages the best of both worlds: the high-performance light-emitting capabilities of III-V materials and the low-loss, cost-effective passive routing of the silicon platform [93]. This is the most common approach for creating integrated laser sources on silicon. A significant advantage is that it allows for the parallel processing of both the silicon and III-V wafers, which can improve manufacturing yield.

5.3.3. Hybrid Integration

Hybrid integration involves placing separate, pre-fabricated III-V and silicon photonic chips side-by-side or on a common substrate and then connecting them [94,95]. This can be performed via techniques such as flip-chip bonding. While this method can lead to higher insertion loss and a larger footprint than heterogeneous or monolithic integration, it offers the highest level of flexibility and yield. It allows designers to select best-in-class components from different processes (e.g., a high-power III-V laser from one vendor and a low-loss silicon PIC from another) and then assemble them at the package level. This approach is particularly relevant for advanced systems like co-packaged optics (CPO), which integrate both the electronic IC (EIC) and the photonic IC (PIC) onto a single package, minimizing the length of high-speed electrical traces.

Therefore, the choice of integration approach is a key consideration in system design, trading off between manufacturability, performance, and cost. While monolithic integration offers the highest level of integration density, heterogeneous and hybrid methods are vital for incorporating high-performance III-V devices, such as laser sources, that are essential for a complete and functional silicon photonic system.

6. Challenges and Future Outlook

Despite the tremendous progress in the performance and manufacturing of passive silicon photonic devices, several significant challenges remain. Overcoming these hurdles is essential for the technology to realize its full potential. Concurrently, a number of exciting trends are emerging that promise to redefine the capabilities and application scope of silicon photonics, pushing the field into new and uncharted territories.

6.1. Persistent Technical Hurdles

6.1.1. Polarization Management

One of the most persistent challenges in silicon photonics stems from the material and geometric properties of the waveguides themselves. The high refractive index contrast of the SOI platform and the typically rectangular cross-section of the waveguides lead to a very large birefringence [96]. This means that the effective refractive index experienced by the light is significantly different for the TE mode and the TM mode. As a result, the performance of most photonic devices—from couplers to filters—is highly polarization-dependent. This poses a major problem because the polarization state of light arriving from a standard optical fiber is generally arbitrary and can fluctuate over time.

To address this, on-chip polarization management is required [97,98,99]. This is typically achieved through a polarization diversity approach, where the incoming light is split into its TE and TM components by a polarization beam splitter (PBS). The TM polarization is then converted to TE polarization using a polarization rotator (PR), and both TE signals are processed in parallel on identical circuits. Recent advancements in these crucial components include the creation of ultra-compact polarization beam rotator-splitters (PBRS) have been created using inverse design, combining both functions into a single, high-performance device [100]. Sub-wavelength gratings can also be engineered to be highly anisotropic, allowing for the design of efficient TM-pass polarizers and broadband PBSs [96,101]. Additionally, tunable polarization management is being explored using micro-electromechanical systems (MEMS). By mechanically perturbing a waveguide or changing the gap in a directional coupler, MEMS structures can enable tunable polarization splitting and rotation, offering reconfigurability that is not possible with static devices [102].

6.1.2. Packaging and Integration

While device fabrication has benefited enormously from leveraging CMOS infrastructure, photonic packaging remains a major bottleneck and a significant contributor to the final cost of a photonic-enabled system [5,8,103]. The challenges are multifaceted, encompassing optical I/O, electrical integration, heterogeneous integration, and thermal management [104].

Achieving robust, low-loss, and high-throughput alignment of optical fibers (or fiber arrays) to the chip’s couplers is a critical and often time-consuming step. While passive alignment schemes are being developed, active alignment, where the device is powered on and the fiber position is optimized for maximum coupling, is still common but expensive and slow. High-speed electrical signals must be routed to and from the PIC to drive active components like modulators. This requires careful RF design and integration to avoid signal degradation and crosstalk.

Furthermore, most silicon photonic systems require an external laser source because silicon is an inefficient light emitter. Heterogeneous integration, whether through flip-chip bonding or wafer-level techniques, is a complex assembly process to integrate these III-V semiconductor lasers with the silicon PIC. Lastly, thermal management is crucial for stable operation, as PICs, especially those with densely integrated electronics and active photonic components, can generate significant heat. Silicon photonic devices are highly sensitive to temperature, so thermal crosstalk between components must be carefully modeled and mitigated.

Solutions are being pursued through the development of standardized packaging design rules (PDRs) and the holistic, system-level approach of co-packaged optics.

6.2. Emerging Trends and Future Directions

6.2.1. Co-Packaged Optics (CPO)

Co-packaged optics represents a fundamental shift in how optical interconnects are integrated into high-performance computing systems. The concept involves moving the optical I/O functionality from front-panel pluggable modules directly onto the same package or substrate as the main electronic IC, such as a network switch ASIC or a GPU, as shown in Figure 9. By co-integrating the photonic and electronic chiplets, the electrical distance that high-speed signals must travel is reduced from tens of centimeters across a PCB to mere millimeters or microns on the package substrate [105,106,107].

This architectural change is driven primarily by the immense power consumption of modern data centers. In a traditional pluggable architecture, a significant portion of the system power (~15 pJ/bit) is consumed by the SerDes (Serializer/Deserializer) circuits needed to drive the long, lossy copper traces to the front panel. CPO promises to slash this interconnect power to <5 pJ/bit, a critical step for enabling the terabit-per-second switches and AI accelerators of the future. However, this approach introduces significant new challenges in thermal management (as the hot ASIC is now next to the temperature-sensitive PIC), manufacturing yield, testing, and field serviceability.

6.2.2. Inverse Design and Artificial Intelligence (AI)

The increasing complexity of photonic devices is driving a revolution in design methodology. The traditional approach, which relies on human intuition and parameter sweeps of known structures, is often too slow and suboptimal for creating the novel components required for next-generation systems. Inverse design is a new paradigm that flips this process on its head [108,109]. Instead of starting with a structure, the designer specifies a desired optical function (a figure of merit), and an optimization algorithm explores a vast design space to generate a device topology that best achieves that function [110].

These algorithms, such as topology optimization (TO) or genetic algorithms (GA), often produce non-intuitive, free-form, or “pixelated” structures that can significantly outperform their conventional counterparts, as shown in Figure 10. This has led to breakthroughs in creating ultra-compact and highly efficient devices like splitters and grating couplers [111].

Complementing inverse design, artificial intelligence and machine learning models are being used to accelerate the design cycle even further [112]. Deep neural networks (DNNs) can be trained on simulation data to act as ultra-fast surrogates for computationally expensive electromagnetic solvers. This allows for the rapid prediction of a device’s performance, enabling vast optimizations that would otherwise be intractable. A key challenge that remains is the “black-box” nature of these methods; understanding the underlying physics of the novel structures they produce is an active area of research.

6.2.3. New Frontiers: Quantum and Sensing

The maturation of the silicon photonics platform is enabling its application in entirely new domains beyond communications. Quantum technologies represent a significant frontier, with silicon photonics emerging as a leading platform for building photonic quantum computers. The ability to fabricate large-scale, complex interferometric circuits with high stability and low loss on a chip is ideal for manipulating photonic qubits [113,114]. Photons are robust qubits, resilient to decoherence, and can be operated at room temperature. The scalability and manufacturability offered by CMOS foundries are a major advantage for constructing the future’s million-qubit, fault-tolerant systems.

Another key area is advanced sensing, where the high sensitivity of photonic devices to their environment is being leveraged for a new generation of miniaturized, low-cost, and high-performance sensors [115]. Applications include biosensing [116], where high-Q microring resonators are used as highly sensitive label-free biosensors to detect the presence of proteins, viruses, or DNA by measuring minute changes in the refractive index of their surroundings. Spectroscopy is also enabled on-chip through miniaturized Fourier-transform spectrometers (FTS) or AWGs, used for chemical analysis and gas sensing, particularly in the mid-infrared range [117]. Furthermore, LiDAR systems for autonomous vehicles and robotics are being developed using PICs to build solid-state systems that steer laser beams without any moving parts [118].

These emerging trends are not developing in isolation but are part of a virtuous cycle. The demand for more computational power for AI is a primary driver for CPO. The complexity of CPO systems necessitates the use of AI-driven inverse design tools. The resulting ability to design and fabricate highly complex, integrated systems then opens the door to revolutionary applications like large-scale quantum processors and multi-analyte sensor arrays, which in turn create new demands, further accelerating the entire field.

7. Conclusions

7.1. Synthesis of Key Advancements

The field of passive silicon photonics has undergone a period of transformative growth, evolving from a promising academic research area into a mature, industrialized technology. This review has charted the remarkable progress across its foundational components. We have witnessed the propagation loss of optical waveguides plummet from the dB/cm to the dB/m regime, a thousand-fold improvement driven by advances in rib waveguide architectures, ultra-pure silicon nitride films, and novel fabrication techniques like the Damascene process. This ultra-low loss has been the direct enabler for resonant devices, such as microring resonators, to achieve extraordinary quality factors in the tens of millions, unlocking new possibilities in filtering, sensing, and nonlinear optics.

Simultaneously, the critical interfaces to and within the chip have been perfected. Both grating couplers and edge couplers have converged on near-unity coupling efficiencies, effectively erasing a long-standing performance trade-off and giving system architects greater flexibility in packaging and testing strategies. On-chip splitters and routers, once limited by the simple geometries of Y-branches and directional couplers, are now sophisticated components engineered for broadband, low-loss, and fabrication-tolerant operation through the use of mode evolution principles and sub-wavelength grating metamaterials.

Underpinning all these device-level advancements is the maturation of the global fabrication ecosystem. The multi-project wafer (MPW) model has successfully democratized access to state-of-the-art manufacturing, fostering a vibrant community of innovation among universities and fabless design houses. Major commercial and research foundries now offer robust, well-characterized process design kits (PDKs) that include not only silicon but also co-integrated materials like silicon nitride and germanium, alongside advanced packaging solutions, providing a clear and reliable path from concept to high-volume production.

7.2. Concluding Perspective on the Field’s Trajectory

Looking at the trajectory of the field, it is clear that silicon photonics is successfully navigating the transition from a focus on optimizing individual component performance to a focus on system-level integration, manufacturability, and robustness. The central questions are evolving from “Can we build a high-performance device?” to “Can we integrate, package, test, and scale these complex systems reliably and cost-effectively?” This shift is indicative of a technology reaching industrial maturity.

The convergence of several powerful trends—the insatiable demand for bandwidth from AI, the architectural shift towards co-packaged optics, the paradigm change in design methodology brought by AI-driven tools, and the expansion into new application frontiers like quantum computing and advanced sensing—creates a powerful, self-reinforcing cycle of innovation. As these elements co-evolve, they accelerate the capabilities of the platform at an exponential rate. Silicon photonics is therefore not merely an incremental improvement over copper interconnects; it is a foundational enabling technology poised to follow a similar trajectory of impact and integration as the electronic integrated circuit industry. It is cementing its role as the essential hardware backbone for the data-intensive, intelligent, and quantum-aware world of the 21st century.