Charger/Discharger with a Limited Current Derivative and Regulated Bus Voltage: A Simultaneous Converter-Controller Design

Abstract

This paper proposes a co-design methodology for the power and control stages of a bidirectional battery charger/discharger based on a boost converter topology. The approach ensures safe operation by limiting the battery current derivative, preventing abrupt transients that could degrade battery lifespan. The control strategy combines a cascade structure with an inner sliding mode current controller (for robustness and fast response) and an outer adaptive PI voltage loop (to regulate the DC-link voltage under varying load conditions). Additionally, the design constrains the switching frequency to reduce power losses. Experimental validation on a prototype converter demonstrates the effectiveness of the co-design framework, showing precise current/voltage regulation, adherence to switching frequency limits, and compliance with battery charging/discharging requirements. The results highlight the methodology’s potential to enhance efficiency and reliability in energy storage systems. The dynamic restrictions, overshoot lower than 5%, settling time shorter than 5 ms, and a battery current limitation less than 50 A/ms were always met with SMC and, in some cases, with the PI controller, but the results with SMC were always better: lower overshoot, shorter settling time, and greater restriction on the derivative of the battery current. In addition, the SMC system was 2.5–5.0% more efficient than the PI controller.

1. Introduction

Electrochemical energy storage has emerged as a fundamental pillar for the transition to a more sustainable energy paradigm, with critical applications ranging from the electrification of transportation to the integration of intermittent renewable energy sources [1,2,3,4,5,6]. At the heart of these systems are charging and discharging processes, essential mechanisms that enable the controlled accumulation and release of energy. The proper management of these cycles is not merely a matter of operational functionality, but a scientific and technical challenge of the first order, given their direct influence on the useful life, safety, and profitability of battery systems.

Chargers and discharge management systems (integrated into a Battery Management System, or BMS [7]) are responsible for regulating these processes. Their importance lies in their ability to dictate current and voltage profiles, thereby controlling internal electrochemical reactions. Optimal management maximizes round-trip efficiency and preserves battery health, while inadequate strategies irreversibly accelerate degradation. The advantages of precise control include maximizing range, ensuring operational safety, and enabling high-reliability applications. However, the main disadvantage lies in the inherent complexity of these systems, which must cope with the intrinsic degradation mechanisms triggered by each cycle.

These aging mechanisms are well documented in the scientific literature [8,9,10,11,12,13,14,15,16], and among them, those caused by thermal effects are the most significant. The rise in battery temperature is primarily driven by irreversible heat (ohmic and polarization heat) and reversible heat (entropic heat) generated during operations at high charge and discharge rates [17,18]. External factors, such as overcharging, the permissible ${\displaystyle \frac{di}{dt}}$ limits at the terminals, and mechanical compression, exacerbate this increase by inducing internal short circuits and a chain of exothermic chemical reactions [19,20,21]. Notable among these reactions are the decomposition of the passivation layer (SEI—Solid Electrolyte Interphase) and the electrolyte, as well as the structural collapse of the cathode, which releases massive amounts of heat and flammable gases [17,18,22].

This thermal rise and high-rate cycling cause severe structural degradation, manifested in the pulverization and fragmentation of electrode particles [19,22]. This fragmentation increases the reactive surface area, reducing the activation energy and accelerating the onset of thermal runaway. Chemical degradation includes interface reconstruction and phase evolution that compromise service life. Furthermore, there is an exponential relationship between capacity fade and an increase in internal resistance [19]. Moreover, in the internal resistance, a high RMS current becomes important, since ohmic heat (part of the irreversible heat) is calculated as $I^2·R_{int}$ (where I is the current and $R_{int}$ is the internal resistance), leading to significantly higher heat generation that accelerates thermal degradation [18]. A charging/discharging current with a steep slope contributes significantly to this, as it contains multiple harmonics that increase the current’s RMS value and, consequently, accelerate battery degradation. However, the critical factor—considered the primary driver of battery degradation—is high charge/discharge current rates (C-rate), which can lead to structural degradation, chemical instability, and failure of the separator [19,22].

This challenge takes on a particularly critical dimension in the emerging context of second-life batteries. After serving in demanding applications such as electric vehicles, these batteries are reused in less stressful stationary applications [23,24,25]. However, their prior cycling history makes them more susceptible to accelerated degradation under poorly managed charge-and-discharge profiles, quickly compromising the economic and technical viability of their reuse [26,27]. Therefore, mitigating these effects requires approaches that transcend conventional design.

Existing battery chargers/dischargers vary widely, classified by converter topology, control strategy, and switching strategy [28,29,30,31,32,33]. While prior literature addresses the design of charger/discharger power and control stages, most approaches lack full integration between these components.

The difficulty lies in the fact that non-integrated methodologies consist of a sequential design process or one that is independent of the power and control stages. In other words, the control is designed only once the converter topology and component values have been established. The design of the power stage does not consider the implications of the actual control, it only sizes the passive components (inductors and capacitors), semiconductors (MOSFETs and diodes), and the converter topology, based on criteria such as voltage/current ranges, efficiency, voltage/current ripple, maximum voltage/current values supported by the devices, cost, and availability of components, among others.

Critical parameters such as the permissible physical limit of di/dt at the battery terminals (for safety and service life) are often imposed retrospectively as an operational restriction on the controller (e.g., through reference saturation) without influencing the calculation of the inductor, which is directly affected, since $di/dt=V/L$. The above leads to suboptimal solutions: an inductor that is too small allows excessive $di/dt$, which generates thermal/mechanical stress on batteries; an inductor that is too large is bulky and expensive, and may have performance limitations in high-frequency dynamics.

Furthermore, the desired settling time, overshoot, or disturbance rejection cannot be guaranteed if the converter was not designed to offer a “favorable plant” (e.g., with well-separated poles or no dominant nonlinearities). In this way, the controller becomes a “band-aid” to compensate for structural deficiencies in the hardware. Therefore, the control is forced to “adapt” to an already fixed plant, which can be challenging to stabilize or lead to undesirable dynamics (such as non-minimum-phase zeros, resonances, etc.). If control proves unstable or too slow, ad hoc redesigns are required—changing inductors, adjusting the switching frequency, adding filters—all of which involve trial-and-error cycles, repeated prototyping, and wasted time and resources.

In short: a non-integrated methodology artificially separates two subsystems that are physically and dynamically coupled, treating the converter as a “static black box” and the controller as an “external module,” when in reality both form a single closed dynamic system.

Literature Review and Contributions

The literature review was conducted using descriptors related to the design of switched converters for battery chargers/dischargers and the limitation on the battery current derivative as a design constraint. The analysis reveals that most research focuses exclusively on the power stage or controller design. Although some studies address both dimensions, they do so in a decoupled manner, ignoring dynamic interdependencies. On the other hand, the limitation on the battery’s $di/dt$ is rarely used as a performance criterion for the converter controller.

For instance, Ref. [34] analyzes a boost converter with PI control for integrating PEMFC fuel cells into local energy systems. On the other hand, Ref. [35] proposes a voltage regulation strategy based on Lyapunov control functions (LCFs) for boost converters, ensuring overall stability. In microgrid applications, Ref. [36] describes a four-port boost converter for integrating renewable sources and lithium storage, with P&O maximum power-point tracking (MPPT), and Refs. [37,38] control a synchronous boost converter and a buck-boost converter, respectively, to charge and discharge batteries using sliding modes. Ref. [39] proposes a design methodology based on polynomial relations of the gain for step-up converters; this approach allows systematic design but does not optimize component selection. The design of the control stage is not included. Ref. [34] presents the design processes for the power and control stages, but decoupled: the values of L and C are determined solely to mitigate steady-state ripple and are not constrained by the controller. Ref. [35] focuses primarily on the mathematical rigor of control stability, assuming pre-existing or simplified physical parameters. In [36], control focuses on the battery charge state and does not condition the converter design. Ref. [37] does not integrate the designs of the power and control stages, while Ref. [38] conditions the selection of the inductor and capacitor on the system’s transient dynamic performance and stability, but in no case does it protect the battery from values of $di/dt$ that exceed its nominal value.

In [40], for a buck converter, an adaptive controller based on observers (model reference adaptive control plus high-gain observer, MRAC + HGO) is designed to power constant-power loads (CPLs) in DC microgrids. Ref. [41] presents a configurable buck converter that can be used as a current or voltage source, designed solely to charge batteries in small-scale non-conventional renewable energy systems. In low-power applications for electric vehicles, Ref. [42] compares designs based on inductors, switched capacitors, and linear regulators (LVRs) in terms of response time, ripple, and efficiency, static characteristics unrelated to the application controller. On the other hand, Ref. [43] analyzes multiphase buck converters from the point of view of their conduction and switching losses and characterizes them in terms of ripple and efficiency as a function of the number of branches in low-voltage, high-current applications. Of these last four references, only Ref. [40] presents the controller design process, but it is not integrated with the power stage design process. In the other three cases, there is no controller to design.

The work of [44] proposes a battery charger/discharger based on flyback topology with adaptive sliding mode control (SMC). Ref. [45] employs a holistic and unified design to integrate an active rectifier with a four-phase interleaved buck-boost converter optimized using the artificial bee colony (ABC) algorithm for fast charging of batteries in electric vehicles. In [46], a design method based on a time-domain model of a three-phase LLC converter acting exclusively as a charger is proposed. In [47], a methodological design process is defined for the power stage of a CLLC resonant converter for a battery charger/discharger, but in this process, $di/dt$ is not limited, nor is it combined with the controller design. Ref. [48] determines the operating mode of a battery charger based on an initial design of a DAB converter. If the design does not meet the requirements, the resonant tank’s frequencies (i.e., inductors and capacitors) must be modified iteratively. The methodology imposes no restrictions on the converter’s passive elements; instead, it adjusts them through trial and error. Refs. [49,50] uses slew-rate control to limit battery current transients on the low-voltage side of a DAB converter, indirectly sizing the high-side AC/DC inductor; however, this approach does not extend to other power/control-stage parameters. In [51], the design processes for the power stage, the SEPIC/Zeta converter for a battery charger/discharger, and control, and LQG adaptive control are presented, but they are not unified within the same methodology. The control stability characteristics of the flyback converter presented in [44] condition the DC bus capacitance, showing coupling between the power and control stage design methodologies, but no restrictions are imposed on the battery current. Ref. [45] implements a hierarchical cascade control structure that includes internal current loops and external voltage loops, all PI. Several passive elements are selected based on the system’s dynamic behavior: the DC link capacitor, the LCL filter, and the phase inductors. However, $di/dt$ is not explicitly specified as a design criterion for the power-stage elements. The design approach for battery protection focuses primarily on minimizing current ripple to extend cell life. Ref. [46] also integrates the power and control stages into the design, but within an optimization process to maximize efficiency without including the derivative of the battery current.

This review highlights a significant gap in the literature: the scarcity of methodologies that integrate both stages into a unified co-design process that optimizes overall system performance, and the lack of attention that designers of charger/discharger control systems pay to strong variations in battery current, a crucial aspect in the degradation of both new batteries and, above all, second-use batteries.

This article argues that a joint design methodology for power stages and control algorithms is indispensable. Such systemic integration is key to ensuring stability across the entire operating range, simplifying controller design, and, most importantly, ensuring system integrity. This performance is achieved by implementing two constraints: limiting charging and discharging rates to minimize battery stress, and regulating the DC bus voltage.

A preliminary version of this solution was presented in [52], which disregards converter losses and considers a simple proportional voltage controller that does not account for the impact of bus capacitance on the system’s global stability. Instead, this paper considers the main converter losses, requiring an additional proportional-integral controller to ensure the desired bus regulation. Additionally, a comparison was made in simulation and experimentation against a classic PI controller.

Table 1. Comparison of the contributions of this work with respect to the references reviewed. Ref., references; I. M., integrated methodology; $di/dt$, battery $di/dt$ limitation; L. A., loss analysis; C., controller; C. T., converter topology; C. C., comparison against another controller; E. V., experimental validation.

Ref.	Contributions of This Work
	I. M.	di/dt	L. A	C.	C. T.	C. C.	E. V.
[34]	×	×	×	PI	Boost	×	✓
[35]	×	×	×	CLF-based	Boost	✓	✓
[36]	×	×	×	ON-OFF	Boost	×	×
[37]	×	×	×	SMC	Boost	×	✓
[38]	✓	×	×	SMC	Buck-Boost	×	✓
[39]	×	×	×	-	Boost	×	✓
[40]	×	×	×	MRAC + HGO	Buck	✓	×
[41]	×	×	×	-	Buck	×	✓
[42]	×	×	×	-	Buck	×	×
[43]	×	×	✓	-	Buck	×	×
[44]	✓	×	×	SMC	Flyback	✓	×
[45]	✓	×	×	PI	Buck-Boost	×	×
[46]	✓	×	×	Optimizer	3$\varphi$ LLC	✓	✓
[47]	×	×	×	CC − CV	CLLC resonant	×	✓
[48]	×	×	✓	PI	DAB	×	✓
[49]	×	×	×	PI	DAB	×	✓
[50]	×	×	×	DCSR	ZVS three-level	✓	✓
[51]	×	×	×	LQG	SEPIC/Zeta	✓	✓
[52]	✓	✓	×	SMC + P	Boost	×	×

summarizes the contributions of this work in comparison with the literature reviewed throughout this subsection. The care with which the system was designed, and the thoroughness of the considerations to ensure the safe operation of both new and second-hand batteries in operating points that minimize degradation due to electrical stress, are clearly evident.

In short, this paper presents a co-design framework for the power and control stages of a boost converter-based battery charger/discharger, accounting for losses in the battery, inductor, and MOSFETs. The system combines a sliding-mode current controller and an adaptive PI voltage controller, ensuring overall stability, second-order dynamic behavior in the output voltage, and limitation of the battery current derivative to operate within safe margins. In addition, it limits the converter’s switching frequency by introducing a hysteresis band into the sliding surface of the current controller. Simulations and experimental tests validate the proposed methodology, while the conclusions highlight the main contributions and results obtained.

2. Power Stage and Mathematical Model

The electrical scheme of the power stage is depicted in Figure 1, which corresponds to a bidirectional buck-boost converter interfacing a battery with a DC bus: boost topology in discharge mode, buck topology in charge mode.

Table 2. Nomenclature.

Description	Symbol	Description	Symbol
Battery voltage	$v_b$	DC Bus voltage	$v_{dc}$
Reference bus voltage	$v_r$	DC Bus current	$i_{dc}$
Battery resistance	$R_b$	MOSFET ON-resistance	$R_{ON}$
Converter inductance	L	Inductor parasitic resistance	$R_L$
DC bus capacitance	$C_{dc}$	Input resistance	$R_i$
Inductor current	$i_L$	Battery current	$i_b$
MOSFET control signal	u	Complementary control signal	$\overline{u}$
Converter duty cycle	d	Complementary duty cycle	$d^{\prime }$
Switching frequency	$F_{sw}$	Switching period	$T_{sw}$
Inductor current ripple	$\delta i_L$	Bus voltage ripple	$\delta v_{dc}$
Switching function (SMC)	$S_x$	Sliding surface (SMC)	$Q_x$
Reference current (SMC)	$i_r$	Hysteresis width (SMC)	$\delta S_x$
Adaptive proportional gain	$k_p$	Adaptive integral gain	$k_i$
Normalized proportional gain	$k_{pa}$	Normalized integral gain	$k_{ia}$
Bus perturbation amplitude	$\Delta i_{dc}$	Maximum overshoot	$MO$
Settling time	$t_s$	Settling time band	$ϵ$
Conduction losses	$P_{Loss,\Omega }$	Switching losses	$P_{Loss,sw}$
MOSFET turn-ON energy	$E_{on}$	MOSFET turn-OFF energy	$E_{off}$

summarizes the nomenclature of this power stage and the control system. The main objectives of this charger/discharger are to regulate the DC bus voltage ($v_{dc}$) and to avoid high current derivatives in the battery. The DC bus is represented by the bus capacitance $C_{dc}$ and the current source $i_{dc}$, which models the current exchanged with the charger/discharger. The converter is formed by two MOSFETs $Q_1$ and $Q_2$ with ON-resistances $R_{ON}$, and an input inductor L with a parasitic resistance $R_L$.

In the design and control of DC/DC converters interacting with batteries, the converter’s model often considers the battery as a constant voltage source. This approach is used in [45] to model the boost battery charger/discharger in a grid-connected fast-charging system for vehicles; similarly, in [53] the battery is considered as an ideal voltage source in the modeling of a non-inverting step-down/up converter for battery voltage regulation. Such a battery modeling approach is used because the State-of-Charge (SoC) changes with the integral of the battery current, thus producing an effective change in the battery voltage over seconds or minutes of operation. Instead, the converter’s current changes very fast, usually in microseconds. However, when the battery voltage is small and the battery current is significant, the internal resistance (ESR) of the battery could produce fast power and voltage changes; hence, some authors use a more realistic model to account for this battery-current effect. The authors of [54] consider a Thevenin model to represent the battery, where the voltage source $v_b$ is associated with the SoC, and the series resistance $R_b$ represents the battery’s internal resistance. In [54] that model is used to analyze the dynamic behavior and control of a buck-boost converter interfacing the battery and an ultracapacitor. Similarly, in [6] the same Thevenin model is used to represent the battery in the modeling of a buck-boost charger/discharger for control design and energy management. In this last case, the $v_b$ voltage is modified at intervals of seconds to represent changes in SoC, while the converter operates at microseconds. Following the previous approach, in this work, the battery is represented by the Thevenin ($v_b$-$R_b$) model, where the voltage $v_b$ can be perturbed to test the system behavior on different SoC conditions.

Figure 1 also describes the control system proposed for this solution, which must be co-designed with the power stage to ensure global stability. The control system includes an inner current controller based on sliding-mode control (SMC), which regulates the inductor current $i_L$ and produces the activation signals of the MOSFETs (u and $\overline{u}=1-u$). The stability of such an SMC depends on the reference current $i_r$, which is produced by a cascade adaptive controller focused on regulating the DC bus voltage. Since the charger/discharger must support battery discharge ($i_L=i_b>0$ and $i_{dc}>0$), stand-by ($i_L=i_b=0$ and $i_{dc}=0$), and charge ($i_L=i_b<0$ and $i_{dc}<0$) conditions, the adaptive controller parameters must be changed to provide a consistent performance in all operation conditions, ensuring the desired bus voltage $v_{dc}=v_r$.

The switched model of the power stage is given in (1), where the differential equations for the inductor current and the bus voltage are modulated by the MOSFETs’ control signals. This model considers the internal resistance of the battery ($R_b$), the MOSFETs’ ON resistances ($R_{ON}$), and the inductor’s parasitic resistance ($R_L$) lumped into an input resistance $R_i$.

$$\begin{array}{c}\hfill {\displaystyle \frac{d{i}_L}{dt}}={\displaystyle \frac{v_b-i_L·R_i-v_{dc}·\overline{u}}{L}},{\displaystyle \frac{d{v}_{dc}}{dt}}={\displaystyle \frac{i_L·\overline{u}-i_{dc}}{C_{dc}}}\end{array}$$

(1)

The average value of the MOSFETs’ control signal (u), within the switching period $T_{sw}$, is equal to the duty cycle $d={\displaystyle \frac{1}{T_{sw}}}·{\int }_0^{T_{sw}}udt$. Then, averaging the switched-mode over the switching period results in the averaged model given in (2), where $d^{\prime }=1-d$ is the complementary duty cycle.

$$\begin{array}{c}\hfill {\displaystyle \frac{d{i}_L}{dt}}={\displaystyle \frac{v_b-i_L·R_i-v_{dc}·d^{\prime }}{L}},{\displaystyle \frac{d{v}_{dc}}{dt}}={\displaystyle \frac{i_L·d^{\prime }-i_{dc}}{C_{dc}}}\end{array}$$

(2)

The average values (low frequency) of the inductor current and complementary duty cycle are calculated by solving the differential equations equal to zero as given in (3). Moreover, the average current by MOSFET $Q_2$ is equal to $i_L·d^{\prime }$.

$$\begin{array}{c}\hfill i_L={\displaystyle \frac{i_{dc}}{d^{\prime }}},d^{\prime }={\displaystyle \frac{v_b+\sqrt{v_b^2-4·v_{dc}·R_i·i_{dc}}}{2·v_{dc}}}\end{array}$$

(3)

Finally, the switching ripples in the inductor current $\delta i_L$ and bus voltage $\delta v_{dc}$ are given in (4), where $F_{sw}={\displaystyle \frac{1}{T_{sw}}}$ is the switching frequency.

$$\begin{array}{c}\hfill \delta i_L={\displaystyle \frac{\left(v_b-i_L·R_i\right)·d}{2·L·F_{sw}}},\delta v_{dc}={\displaystyle \frac{i_{dc}·d}{2·C_{dc}·F_{sw}}}\end{array}$$

(4)

3. Sliding-Mode Controller

The inner sliding-mode controller (SMC) is designed to regulate the inductor current [55], which also defines the battery current. Therefore, the switching function $S_x$ and the sliding-surface $Q_x$ are defined in (5) to impose the desired dynamic behavior on $i_L$ using the reference signal $i_r$. Then, the time derivative of $S_x$ is calculated from (1) and reported in (6).

$$\begin{array}{c}\hfill S_x=i_L-i_r,Q_x=\left\{S_x=0\right\}\end{array}$$

(5)

$$\begin{array}{c}\hfill {\displaystyle \frac{d{S}_x}{dt}}={\displaystyle \frac{d{i}_L}{dt}}-{\displaystyle \frac{d{i}_r}{dt}}={\displaystyle \frac{v_b-i_L·R_i-v_{dc}·\overline{u}}{L}}-{\displaystyle \frac{d{i}_r}{dt}}\end{array}$$

(6)

Sira-Ramirez demonstrates in [56] that, to guarantee global stability of an SMC for switching converters, only two of the three classical conditions (transversality, reachability, and equivalent control) are necessary. The following subsections explain and apply those tests to the SMC based on (5).

3.1. Transversality Condition

This test evaluates the capability of the SMC to define system behavior, which is done by verifying the presence of the control signal u in the switching function derivative, i.e., ${\displaystyle \frac{d}{du}}\left({\displaystyle \frac{d{S}_x}{dt}}\right)\ne 0$. This is tested in (7) by using the $S_x$ derivative (6), resulting in a positive value, thus fulfilling the transversality condition. Moreover, since ${\displaystyle \frac{d}{du}}\left({\displaystyle \frac{d{S}_x}{dt}}\right)>0$, it means that a positive change in u produces a positive $S_x$ derivative, and a negative change in u produces a negative $S_x$ derivative; this information is needed for the reachability test.

$$\begin{array}{c}\hfill {\displaystyle \frac{d}{du}}\left({\displaystyle \frac{d{S}_x}{dt}}\right)={\displaystyle \frac{v_b-i_L·R_i+v_{dc}}{L}}>0\end{array}$$

(7)

3.2. Reachability Conditions

This test evaluates the capability of the SMC to reach the desired sliding surface $Q_x$. Therefore, when $S_x<0$, its derivative must be positive $\left({\displaystyle \frac{d{S}_x}{dt}}>0\right)$ to reach $S_x=0$, and for $S_x>0$, its derivative must be negative $\left({\displaystyle \frac{d{S}_x}{dt}}<0\right)$. These conditions are formalized as follows:

$$\begin{array}{c}\hfill \underset{S_x\to 0^{-}}{lim}{\left.{\displaystyle \frac{S_x}{dt}}\right|}_{u=1}={\displaystyle \frac{v_b-i_L·R_i}{L}}-{\displaystyle \frac{d{i}_r}{dt}}>0\end{array}$$

(8)

$$\begin{array}{c}\hfill \underset{S_x\to 0^{+}}{lim}{\left.{\displaystyle \frac{S_x}{dt}}\right|}_{u=0}={\displaystyle \frac{v_b-i_L·R_i-v_{dc}}{L}}-{\displaystyle \frac{d{i}_r}{dt}}<0\end{array}$$

(9)

Then, combining both (8) and (9) leads to the dynamic restrictions in the reference current $i_r$ needed for stability:

$$\begin{array}{c}\hfill -{\displaystyle \frac{v_{dc}-v_b+i_L·R_i}{L}}<{\displaystyle \frac{d{i}_r}{dt}}<{\displaystyle \frac{v_b-i_L·R_i}{L}}\end{array}$$

(10)

4. Adaptive Controller and Power Stage

From the electrical scheme of Figure 1 it is observed that the average current in the MOSFET $Q_2$ is equal to $d^{\prime }·i_L$. Then, taking into account that the SMC ensures $i_L=i_r$, the SMC, inductor, and $Q_2$ can be represented by a current source $i_r·d^{\prime }$, as depicted in Figure 2. Such an equivalent closed-loop system also describes the internal structure of the adaptive controller, which generates the parameters $k_p$ and $k_i$ of the PI voltage controller using an adaptive law. Finally, the adaptive controller produces the reference $i_r$ for the SMC.

The block diagram of the equivalent closed-loop system is reported at the bottom of Figure 2, which describes the contributions of the reference and load currents into the DC bus voltage. From the equivalent block diagram, two transfer functions are calculated: $G_{v_{dc},i_{dc}}$, which describes the response of the bus voltage $v_{dc}$ to perturbations on the bus current $i_{dc}$; and $G_{i_r,i_{dc}}$, which describes the response of the reference current $i_r$ to the same perturbations ($i_{dc}$). Those transfer functions are first calculated in terms of the PI parameters $k_p$ and $k_i$, but the denominators are in terms of the duty cycle; thus, the poles change with the operation conditions. Therefore, $k_p$ and $k_i$ must be adapted to ensure the same behavior in all the operation conditions. This is addressed by normalizing those parameters with respect to the duty cycle, producing the constant control parameters $k_{pa}=k_p·d^{\prime }$ and $k_{ia}=k_i·d^{\prime }$; thus, the adaptive law that must be processed in real-time is given in (13). Finally, the second forms of $G_{v_{dc},i_{dc}}$ and $G_{i_r,i_{dc}}$ have constant poles:

$$\begin{array}{c}\hfill G_{v_{dc},i_{dc}}={\displaystyle \frac{\frac{-s}{C_{dc}}}{s^2+\frac{k_p·d^{\prime }}{C_{dc}}·s+\frac{k_i·d^{\prime }}{C_{dc}}}}={\displaystyle \frac{\frac{-s}{C_{dc}}}{s^2+\frac{k_{pa}}{C_{dc}}·s+\frac{k_{ia}}{C_{dc}}}}\end{array}$$

(11)

$$\begin{array}{c}\hfill G_{i_r,i_{dc}}={\displaystyle \frac{\frac{k_p·d^{\prime }}{C_{dc}}·s+\frac{k_i·d^{\prime }}{C_{dc}}}{s^2+\frac{k_p·d^{\prime }}{C_{dc}}·s+\frac{k_i·d^{\prime }}{C_{dc}}}}={\displaystyle \frac{\frac{1}{d^{\prime }}·\left(\frac{k_{pa}}{C_{dc}}·s+\frac{k_{ia}}{C_{dc}}\right)}{s^2+\frac{k_{pa}}{C_{dc}}·s+\frac{k_{ia}}{C_{dc}}}}\end{array}$$

(12)

$$\begin{array}{c}\hfill k_p={\displaystyle \frac{k_{pa}}{d^{\prime }}},k_i={\displaystyle \frac{k_{ia}}{d^{\prime }}}\end{array}$$

(13)

Comparing the denominator of the previous transfer functions with the canonical characteristic equation $s^2+2·\rho ·{\omega }_n·s+{\omega }_n^2$ leads to the natural frequency expression ${\omega }_n=\sqrt{{\displaystyle \frac{K_{ia}}{C_{dc}}}}$ and damping ratio expression $\rho ={\displaystyle \frac{k_{pa}}{2·\sqrt{k_{ia}·C_{dc}}}}$. The damping ratio is defined as $\rho =1$ to ensure a voltage response without oscillations, which requires the following $k_{ia}$ value:

$$\begin{array}{c}\hfill k_{ia}={\displaystyle \frac{k_{pa}^2}{4·C_{dc}}}\end{array}$$

(14)

Moreover, the worst-case scenario corresponds to a step-current perturbation in the DC bus $i_{dc}={\displaystyle \frac{\Delta i_{dc}}{s}}$, where $\Delta i_{dc}$ is the step amplitude. Then, calculating the inverse Laplace transformation of $v_{dc}=G_{v_{dc},i_{dc}}·{\displaystyle \frac{\Delta i_{dc}}{s}}$ produces the time-domain expression given in (15), and its time derivative is given in (16):

$$\begin{array}{c}{v}_{dc}=-{\displaystyle \frac{\Delta i_{dc}}{C_{dc}}}·t·e^{-{\displaystyle \frac{k_{pa}·t}{2·C_{dc}}}}\end{array}$$

(15)

$$\begin{array}{c}{\displaystyle \frac{d{v}_{dc}}{dt}}=-{\displaystyle \frac{\Delta i_{dc}}{C_{dc}}}·\left(1-{\displaystyle \frac{k_{pa}·t}{2·C_{dc}}}\right)·e^{-{\displaystyle \frac{k_{pa}·t}{2·C_{dc}}}}\end{array}$$

(16)

The maximum deviation (overshoot, $MO$) in the DC bus voltage occurs when the derivative (16) is equal to zero, which occurs at $t_{MO}={\displaystyle \frac{2·C_{dc}}{k_{pa}}}$. Replacing such a time into (15) leads to the following $k_{pa}$ value, which ensures the desired $MO$:

$$\begin{array}{c}\hfill k_{pa}={\displaystyle \frac{2·\Delta i_{dc}·e^{-1}}{MO}}\end{array}$$

(17)

The settling time for a $ϵ$ band is calculated in (18) by solving (15) for $v_{dc}=v_r-ϵ·MO$ and $t=t_s$, where $W_{-1}\left(·\right)$ is the lower branch of the Lambert-W function.

$$\begin{array}{c}\hfill t_s=-{\displaystyle \frac{2·C_{dc}·W_{-1}\left(\frac{ϵ·MO·k_{pa}}{2·\Delta i_{dc}}\right)}{k_{pa}}}\end{array}$$

(18)

Finally, during the operation of this adaptive controller, the adaptive parameters $k_p$ and $k_i$ must be calculated in real-time using (13), thus requiring $i_{dc}$ to calculate the complementary duty cycle $d^{\prime }$ using (3). Therefore, this adaptive law requires the measurement of the DC-bus current $i_{dc}$, as illustrated in both the circuit scheme of Figure 1 and block diagram of Figure 2.

4.1. C_dc Value for Global Stability

The SMC requires fulfilling the dynamic restrictions (10) to ensure global stability; thus, the dynamic behavior of $i_r$ must be analyzed. Calculating the inverse Laplace transformation of $i_r=G_{i_r,i_{dc}}·{\displaystyle \frac{\Delta i_{dc}}{s}}$ produces the time-domain expression given in (19), and its time derivative is given in (20):

$$\begin{array}{c}\hfill i_r={\displaystyle \frac{\Delta i_{dc}}{d^{\prime }}}·\left(1-e^{-{\displaystyle \frac{k_{pa}·t}{2·C_{dc}}}}+{\displaystyle \frac{k_{pa}·t}{2·C_{dc}}}·e^{-{\displaystyle \frac{k_{pa}·t}{2·C_{dc}}}}\right)\end{array}$$

(19)

$$\begin{array}{c}\hfill {\displaystyle \frac{d{i}_r}{dt}}={\displaystyle \frac{\Delta i_{dc}·k_{pa}}{d^{\prime }·C_{dc}}}·\left(1-{\displaystyle \frac{k_{pa}·t}{4·C_{dc}}}\right)·e^{-{\displaystyle \frac{k_{pa}·t}{2·C_{dc}}}}\end{array}$$

(20)

The maximum value of ${\displaystyle \frac{d{i}_r}{dt}}$ occurs at $t_{ir}=0$, producing $\max \left({\displaystyle \frac{d{i}_r}{dt}}\right)={\displaystyle \frac{\Delta i_{dc}·k_{pa}}{d^{\prime }·C_{dc}}}$. Then, replacing such a maximum value into restrictions (10) leads to the following $C_{dc}$ range to ensure global stability, which considers charge and discharge states:

$$\begin{array}{c}\hfill C_{dc}>\max \left({\displaystyle \frac{\left|\Delta i_{dc}\right|·k_{pa}·L}{\left(v_{dc}-v_b\right)·d^{\prime }-\left|i_{dc}\right|·R_i}},{\displaystyle \frac{\left|\Delta i_{dc}\right|·k_{pa}·L}{v_b·d^{\prime }-\left|i_{dc}\right|·R_i}}\right)\end{array}$$

(21)

4.2. L Value to Limit the Battery Current Derivative

The previous $C_{dc}$ range ensures that the dynamic restrictions (10) are always fulfilled, thus the reference current for the SMC ($i_r$) is always limited by the instantaneous inductor current derivatives defined in the switched model (1).

However, since the battery current is imposed by the inductor current ($i_b=i_L$), the instantaneous maximum derivative in the battery current ${\displaystyle \frac{d{i}_b}{dt}}$ is defined by the maximum inductor current derivatives described in (1) for $u=1$ and $u=0$ conditions. Then, the maximum battery current derivative is limited by calculating the inductance L from (1) taking into account the charge balance principle ($i_{dc}=i_L·d^{\prime }$): any L value higher than (22) ensures that the battery current derivative, in any condition, is always lower than the maximum limit max $\left({\displaystyle \frac{d{i}_b}{dt}}\right)$ used in (22) to calculate L, i.e., ${\displaystyle \frac{d{i}_b}{dt}}={\displaystyle \frac{d{i}_L}{dt}}<\max \left({\displaystyle \frac{d{i}_b}{dt}}\right)$.

$$\begin{array}{c}\hfill L>{\displaystyle \frac{\max \left(v_b+\frac{\left|i_{dc}\right|}{d^{\prime }}·R_i,v_{dc}-v_b+\frac{\left|i_{dc}\right|}{d^{\prime }}·R_i\right)}{\max \left(\frac{d{i}_b}{dt}\right)}}\end{array}$$

(22)

Therefore, selecting L using (22) limits the battery current derivative at the power stage level. Hence, this limitation is applied despite the control system adopted, i.e., the adaptive SMC proposed in this work, or any other control strategy like traditional PID.

4.3. Switching Frequency Limitation and SMC Control Law

The theoretical SMC could reach infinite switching frequency near the steady-state condition $S_x=0$, hence a common solution is to introduce a hysteresis band $\left\{-\delta S_x,+\delta S_x\right\}$ using a hysteresis comparator, where $\delta S_x$ is the hysteresis width. Such a hysteresis band changes the sliding-surface to $Q_x=\left\{-\delta S_x<S_x<+\delta S_x\right\}$, producing the following SMC control law:

$$\begin{array}{c}\hfill u=\left\{\begin{array}{ccc}0\hfill & \mathrm{if}\hfill & S_x\ge +\delta S_x\hfill \\ 1\hfill & \mathrm{if}\hfill & S_x\le -\delta S_x\hfill \end{array}\right.\end{array}$$

(23)

Therefore, the switching frequency is defined by the hysteresis ripple $\delta S_x$ of the switching function (5), which is equal to the subtraction of the ripples in $i_L$ and $i_r$ because the SMC ensures that the average value of $S_x$ is zero. The ripple in $i_L$ and $v_{dc}$ were calculated in (4) as $\delta i_L$ and $\delta v_{dc}$. Then, the ripple in $i_r$ is produced by the PI controller processing $\delta v_{dc}$, resulting in $k_{pa}·\delta v_{dc}$ since the integral of $\delta v_{dc}$ is equal to zero due to the charge balance principle. Therefore, $\delta S_x=\delta i_L-k_{pa}·\delta v_{dc}$, and using the ripple values in (4) leads to Equation (24), where the discharge state is the worst-case scenario.

$$\begin{array}{c}\hfill \delta S_x={\displaystyle \frac{d}{2·\max \left(F_{sw}\right)}}\left({\displaystyle \frac{v_b+\frac{\left|i_{dc}\right|}{d^{\prime }}·R_i}{L}}+{\displaystyle \frac{k_{pa}·\left|i_{dc}\right|}{C_{dc}}}\right)\end{array}$$

(24)

Then, the switching frequency imposed by the SMC changes depending on the operating conditions, and it is calculated from (24) as follows:

$$\begin{array}{c}\hfill F_{sw}={\displaystyle \frac{d}{2·\delta S_x}}\left({\displaystyle \frac{v_b-\frac{i_{dc}}{d^{\prime }}·R_i}{L}}-{\displaystyle \frac{k_{pa}·i_{dc}}{C_{dc}}}\right)\end{array}$$

(25)

Finally, the minimum switching frequency is obtained from (25), as reported in Equation (26), which must be evaluated in the worst-case scenario: minimum duty cycle and maximum load current.

$$\begin{array}{c}\hfill \min \left(F_{sw}\right)={\displaystyle \frac{\min \left(d\right)}{2·\delta S_x}}\left({\displaystyle \frac{v_b-\frac{\max \left(i_{dc}\right)}{1-\min \left(d\right)}·R_i}{L}}-{\displaystyle \frac{k_{pa}·\max \left(i_{dc}\right)}{C_{dc}}}\right)\end{array}$$

(26)

4.4. Synthesis of the Design Procedure

The design process starts by calculating the duty cycle d using (3), then a commercial inductance L is selected from (22). The next step is to calculate $k_{pa}$ using (17), and subsequently select a commercial capacitance $C_{dc}$ following (21). The settling time $t_s$ is calculated from (18). If such a value does not fulfill the application requirements (design limit), then $MO$ must be reduced, which increases $k_{pa}$ to reduce $t_s$. Then, $k_{ia}$ is calculated from (14), and the hysteresis band $\delta S_x$ is calculated from (24).

The minimum switching frequency will not produce discontinuous conduction mode because the charger/discharger of Figure 1 is a synchronous converter, and the inductor current ripple is imposed by the SMC. However, low switching frequencies increase the voltage ripple $\delta v_{dc}$ in the DC bus, as given in (4); therefore, Equations (4) and (26) must be used to verify that the maximum voltage ripple in the DC bus is acceptable (design limit). In addition, switching frequencies below 20 kHz produce audible noise; thus, Equation (26) must be used to verify that the selected value of L produces $F_{sw}\ge$ 20 kHz. In this way, the design procedure considers reducing L if the minimum switching frequency is not acceptable. Moreover, if the voltage ripple $\delta v_{dc}$ in the DC bus is not acceptable (higher than a design limit), L could be reduced to increase the switching frequency, or $C_{dc}$ could be increased as reported in (4).

Finally, Figure 3 summarizes the proposed co-design procedure for the power stage and control system of the battery charger/discharger.

5. Design Example and Experimental Validation

The proposed solution has been validated using a $24V_{DC}$ bus with a nominal current of $1\mathrm{A}$ and dynamic variations of $100\%$ of the load current. The choice of this application environment was guided by a combination of criteria: technological relevance, experimental feasibility, and the scalability of the prototype system, in line with the capabilities of the Electronics and Renewable Energy Laboratory of the Instituto Tecnológico Metropolitano, where the proof of concept was carried out.

The $24V_{DC}$ level is a well-established standard in multiple distributed energy and stand-alone system applications, superior to the typical $12\mathrm{V}$ in terms of transmission efficiency and compatibility with modern loads, but still accessible for academic prototyping. Its most relevant uses include: small-scale hybrid photovoltaic systems (100–500 W), backup systems and rural telecommunications microgrids, which operate at $24\mathrm{V}$ to power radio equipment, sensors, and remote stations, light electric vehicles and mobile platforms using dual-voltage architectures ($12\mathrm{V}$ for control electronics and $24\mathrm{V}$ for small actuators/motors), and emerging industry standards for DC microgrids in buildings, where $24\mathrm{V}$ and $48\mathrm{V}$ are levels recommended by the Emerge Alliance and IEC 60364-7-710 [57] for safe power supply to low-power loads (less than 250 W) in non-specialized environments. With a nominal current of $1\mathrm{A}$ at $24\mathrm{V}$, the DC power is 24 W, while transients of $\pm 1\mathrm{A}$ allow the dynamic response of the converter, the stability of the control loop, and the management of demand peaks to be evaluated—common scenarios, for example, when connecting/disconnecting loads such as DC fans, small pumps, or communication modules with impulse start-up. This range is sufficiently demanding to validate control strategies without requiring high-power devices or extreme safety measures.

To facilitate validation testing, the laboratory has Taraz’s SPM-FB evaluation platform based on SiC MOSFETs. This rapid prototyping solution can be reconfigured to produce different topologies of typical power converters. The module features integrated current and voltage sensors, and drivers for SiC MOSFETs with configurable dead time, short-circuit protection, per-channel low-voltage lockout, and active Miller clamping to prevent false triggering during fast switching. The above dramatically reduces gate control circuit design time, minimizes critical layout, and improves prototype reliability—aspects that are especially relevant when the focus is on the control algorithm, not low-level power electronics. One disadvantage of the platform is that its transistors (G3R75MT12D) are designed for high-current, high-voltage applications, which means their turn-on and turn-off energies are high, significantly increasing switching losses.

Accordingly, the proposed system was validated using an FL1223GS battery with a nominal voltage of $12\mathrm{V}$. The reference voltage is $v_r=24\mathrm{V}$, the maximum load current is $i_{dc}=1\mathrm{A}$, the maximum load perturbation is $\Delta i_{dc}=1\mathrm{A}$, the maximum DC voltage deviation is set to 5% ($MO=1.2\mathrm{V}$), and the settling time (2% band) must be lower than 5 ms. The ON-resistance of the MOSFETs is $75\mathrm{m}\Omega$, the parasitic resistance of the inductor is $67\mathrm{m}\Omega$, and the series resistance of the battery is $90\mathrm{m}\Omega$, which results in $R_i=232\mathrm{m}\Omega$. Moreover, since a second-life battery is considered, the battery current derivative must be limited to $\max \left({\displaystyle \frac{d{i}_b}{dt}}\right)$ = 50 A/ms. Finally, the maximum switching frequency is set to $\max \left(F_{sw}\right)$ = 75 kHz.

Applying the design procedure reported in Section 4.4 results in an average duty cycle $〈d〉=0.52$ and a minimum inductance of $249.67\mathsf{\mu }\mathrm{H}$, selecting the commercial inductance 2318-V-RC1720 with $L=330\mathsf{\mu }\mathrm{H}$. Then, $k_{pa}=0.6454$ A/V is calculated. The minimum capacitance of $46.25\mathsf{\mu }\mathrm{F}$ is obtained by selecting $C_{dc}=253\mathsf{\mu }\mathrm{F}$, which yields a settling time $t_s$ = 4.5 ms, thus fulfilling the design requirement. Finally, $k_{ia}$ = 411.61 A/(V·s) and $\delta S_x=0.145\mathrm{A}$ are calculated.

This power stage serves as a scalable validation platform where modulation strategies, control, and protections tested at 24 V/1 A can be directly replicated in 24 V/5 A or 48 V/10 A systems by resizing passive and semiconductor components, without modifying the control logic or system architecture. This reinforces the transferability of results from the laboratory to other practical applications. Appendix A reports additional design examples validated with detailed circuital simulations, which consider high current and a wide range of voltage conversion ratios.

5.1. Circuital Simulations

The power system of Figure 1 was implemented in the electronics simulator PSIM, including the designed SMC and adaptive controllers. Figure 4 reports the detailed simulation of the circuit and control systems, where the load profile considers discharge ($i_{dc}>0$), charge ($i_{dc}<0$), and stand-by ($i_{dc}=0$) conditions. The perturbations in the DC bus current have step-like waveforms with $1\mathrm{A}$ amplitudes, thus producing deviations in the DC bus voltage. However, the cooperative action of the SMC and adaptive controllers imposes the desired behavior on the DC bus: the voltage is regulated at $24\mathrm{V}$ with maximum deviation $MO\le 1.2\mathrm{V}$ and settling time $t_s$ < 5 ms. In addition, the correct operation of the SMC is observed, which also constrains the battery current derivative to the desired value ${\displaystyle \frac{d{i}_b}{dt}}$ < 50 A/ms. The switching frequency is also limited to the desired range $F_{sw}$ < 75 kHz, and the switching function is always trapped inside the practical surface $\left\{-\delta S_x,+\delta S_x\right\}$, which ensures the global stability. Moreover, the additional design examples presented in Appendix A confirm the correct results provided by the co-design procedure in a wide range of voltage conversion ratios and load currents.

It is worth noting that the circuital simulation of Figure 4 starts with the DC-bus capacitor already pre-charged at nominal voltage ($24\mathrm{V}$). This is a common practice since battery chargers/discharges based on boost converters use well-known pre-charge circuits to avoid high inrush currents that could damage the battery and the power converter [58,59]. Appendix B discusses a classical start-up solution for DC-buses based on boost converters.

5.1.1. Performance Under Parametric Variations

Six additional simulations were conducted to evaluate the robustness of the adaptive controller, which consider changes in the bus capacitance ($C_{dc}$) and inductor (L). Those circuital simulations assume modifications of ±2% in both elements to be in agreement with maximum tolerances on commercial elements. Figure 5a shows that changes on $C_{dc}$ do not affect the DC bus voltage performance, fulfilling both $MO$ and $t_s$ requirements. Similarly, the inductor current profiles are almost the same in the three cases. Both the correct bus voltage and the battery (inductor) current are produced by the adaptive capability of the proposed control system. The switching frequency imposed in the three cases of Figure 5a is very similar, where increments in $C_{dc}$ reduce the effect of $i_{dc}$ on $F_{sw}$ as it is observed in (25). The conduction losses $P_{Loss,\Omega }$, which include the losses on the ON-resistance of the MOSFETs, the parasitic resistance of the inductor, and the series resistance of the battery, are calculated as given in (27). In addition, the switching losses are calculated from the switching frequency $F_{sw}$, the MOSFETs’ turn-ON switching energy $E_{on}$, and the MOSFETs’ turn-OFF switching energy $E_{off}$ using the classical expression (28) reported in [60]. Finally, the total power losses $P_{Loss}$ are given in (29). Given that the manufacturer of the G3R75MT12D transistors [61], considered in both simulations and experiments, reports an $E_{on}=217\mathsf{\mu }\mathrm{J}$ and $E_{off}=52\mathsf{\mu }\mathrm{J}$ under conditions of $800\mathrm{V}/20\mathrm{A}$, scaling to the operating point of this application, $24\mathrm{V}/2\mathrm{A}$ (inductor current), the turn-on and turn-off energies considered to calculate the switching losses are $21.7\mathsf{\mu }\mathrm{J}$ and $5.2\mathsf{\mu }\mathrm{J}$, respectively. The bottom traces of Figure 5a show the power losses produced by the Adaptive SMC for the three $C_{dc}$ values. Those results show that the consistent $F_{sw}$ behavior also produces a consistent loss condition:

$$\begin{array}{c}\hfill P_{Loss,\Omega }=i_L^2·R_i\end{array}$$

(27)

$$\begin{array}{c}\hfill P_{Loss,sw}=F_{sw}·\left(E_{on}+E_{off}\right)\end{array}$$

(28)

$$\begin{array}{c}\hfill P_{Loss}=P_{Loss,\Omega }+P_{Loss,sw}\end{array}$$

(29)

Figure 5b shows the performance of the Adaptive SMC to changes on L, where no effect on the DC bus voltage performance is present, thus fulfilling both $MO$ and $t_s$ requirements. The same behavior is observed in the inductor (battery) current for all the values of L. Such consistent performance is achieved by the correct operation of the sliding-mode controller, which absorbs those changes in L into the switching frequency. In fact, the switching frequencies reported in Figure 5b increase with reductions on L, which is in agreement with expression (25). Since the switching power losses (28) are proportional to the switching frequency, the total power losses (29) are increased when L is decreased. Finally, it is evident that higher inductor values could improve the converter’s efficiency but at the expense of higher size and cost.

In conclusion, the simulations reported in Figure 5 confirm the correct DC bus voltage regulation even for 20% changes on both $C_{dc}$ and L. However, it must be noted that reductions in L increase the maximum switching frequency; thus, the solution design must include a safe margin for L to account for construction tolerances. Finally, the selected value $L=330\mathsf{\mu }\mathrm{H}$ ensures a minimum switching frequency of 52 kHz with a voltage ripple of 20 mV, and even with a tolerance of 20%, the minimum switching frequency is 42 kHz with a voltage ripple of 24 mV. Both minimum switching frequencies are acceptable for this example since those values are out of the audible range, and both DC voltage ripples are lower than or equal to 0.1%, which is very small.

5.1.2. Comparison with a Classical Solution

A classical solution based on PI structures is designed to provide an additional evaluation of the proposed approach. In this way, a small-signal model $\dot{X}=A_m·X+B_m·U$ is obtained using the state X and input U vectors reported in (30), which leads to the system matrices given in (31).

$$X=\left[\begin{array}{c}{i}_L\\ v_{dc}\end{array}\right]U=\left[\begin{array}{c}d\\ v_b\\ i_{dc}\end{array}\right]$$

(30)

$$A_m=\left[\begin{array}{cc}{\displaystyle \frac{-R_i}{L}}& {\displaystyle \frac{-d^{\prime }}{L}}\\ {\displaystyle \frac{d^{\prime }}{C_{dc}}}& 0\end{array}\right]B_m=\left[\begin{array}{ccc}{\displaystyle \frac{v_{dc}}{L}}& {\displaystyle \frac{1}{L}}& 0\\ {\displaystyle \frac{-i_L}{C_{dc}}}& 0& {\displaystyle \frac{-1}{C_{dc}}}\end{array}\right]$$

(31)

The state-space system is completed with the output equation $Y=C_m·X+D_m·U$. The first option is to design a direct PI controller, which requires a transfer function of the bus voltage $v_{dc}$ with respect to the duty cycle d; such a transfer function is obtained using the matrices $C_m=\left[01\right]$ and $D_m=\left[000\right]$ as given in (32), which has a right half-plane (RHP) zero that makes difficult a direct control with a PI structure.

$$\begin{array}{c}\hfill {\displaystyle \frac{v_{dc\left(s\right)}}{d_{\left(s\right)}}}={\displaystyle \frac{-8237·(s-1.604\times {10}^4)}{s^2+703·s+2.758\times {10}^6}}\end{array}$$

(32)

The classical approach for this kind of converter with RHP zeros is to control another state to produce a reduced-order model. Then, the transfer function of the inductor current $i_L$ with respect to the duty cycle d is obtained using the matrices $C_m=\left[10\right]$ and $D_m=\left[000\right]$ as given in (33), which can be directly controlled with a PI structure (no RHP zero present). The PI current controller $G_{ci}$, given in (34), was designed from the transfer function (33) to provide the same performance of the proposed Adaptive SMC, i.e., a unitary damping ratio ($\rho =1$) and the fastest response possible. To provide a fair comparison with the Adaptive SMC, the PI control system includes a pulse-width modulator (PWM) with a switching frequency equal to $\max \left(F_{sw}\right)$ = 75 kHz to ensure a comparable dynamic response. Finally, the controller $G_{ci}$ was designed with a closed-loop bandwidth equal to 1/10 of the switching frequency (7.5 kHz), which is a classical approach used to ensure stability [62]. Figure 6 shows the block diagram of the complete cascade control system based on PI controllers, where the orange blocks represent the power converter and PWM circuit; that model includes $G_{i,d}$ transfer function (33) between $i_L$ and d, and $G_{v,i}$ transfer function (35) between $v_{dc}$ and $i_L$. Moreover, Figure 6 describes the current control loop (blue blocks) corresponding to the $G_{ci}$ PI controller (34), which regulates $i_L$ according to the reference $i_r$. It is observed that $G_{ci}$ produces the duty cycle d for the PWM circuit.

$$\begin{array}{c}\hfill G_{i,d}={\displaystyle \frac{i_{L\left(s\right)}}{d_{\left(s\right)}}}={\displaystyle \frac{72727·(s+164.7)}{s^2+703·s+2.758\times {10}^6}}\end{array}$$

(33)

$$\begin{array}{c}\hfill G_{ci}={\displaystyle \frac{0.53138·(s+9863)}{s}}\end{array}$$

(34)

Then, the average current of the $Q_2$ MOSFET (within a switching period) in the power converter of Figure 1 is $i_L·d^{\prime }$, thus the reduced-order transfer function $G_{v,i}$ between the bus voltage and inductor current is given in (35). Finally, the cascade voltage controller $G_{cv}$, given in (36), was designed using $G_{v,i}$ to avoid oscillations in the DC bus (unitary damping ratio, $\rho =1$) with the fastest response possible; in this case, the safe bandwidth is equal to 1/10 of the inner (current) controller bandwidth as reported in [63], i.e., 0.75 kHz. Figure 6 describes this cascade voltage control loop (red blocks) corresponding to the $G_{cv}$ PI controller (36), which regulates $v_{dc}$ according to the reference $v_r$. It is observed that $G_{cv}$ produces the reference $i_r$ for the current control loop.

$$\begin{array}{c}\hfill G_{v,i}={\displaystyle \frac{v_{dc\left(s\right)}}{i_{L\left(s\right)}}}={\displaystyle \frac{d^{\prime }}{C_{dc}·s}}\end{array}$$

(35)

$$\begin{array}{c}\hfill G_{cv}={\displaystyle \frac{1.3503·(s+640.2)}{s}}\end{array}$$

(36)

Figure 7a shows the performance of both Adaptive SMC (blue waveforms) and cascade PI controller (red waveforms) at the nominal battery voltage ($v_b=12\mathrm{V}$) used to design both approaches. These results demonstrate the correct design of the classical approach formed by $G_{ci}$ and $G_{cv}$ cascade controllers, where the PI solution achieves the same bus voltage and inductor current performance in comparison with the Adaptive SMC; i.e., both $MO$ and $t_s$ are fulfilled. However, the cascade PI solution exhibits a constant switching frequency imposed by the PWM (75 kHz), thus the calculated power losses are higher than in the Adaptive SMC case.

The operation of any charger/discharger produces changes in the battery SoC, which affects the battery voltage ($v_b$). Therefore, Figure 7b reports the circuital simulations of both solutions under a 25% reduction on $v_b$ to test the robustness of the controllers to changes in SoC. Those results show that the Adaptive SMC correctly regulates the bus voltage, fulfilling $MO$ and $t_s$ to ensure a safe operation of the DC bus. This is achieved by the adaptive law of this solution (13), which modifies the controller to ensure the desired performance under any duty cycle condition, thus adjusting the controller to changes in the battery voltage. Instead, the circuital simulations of Figure 7b shows that the classical PI solution is unable to ensure the desired performance ($MO$) of the DC bus voltage under changes of the battery voltage, which puts at risk any source or load connected to the bus. This is a result of operating far from the condition used to design the PI controllers (nominal $v_b$), thus demonstrating the lack of robustness of this classical solution to changes in real operation conditions. In addition, similar to the operation at nominal $v_b$, the switching frequency of the cascade PI is constant (75 kHz), and the power losses are higher than in the Adaptive SMC.

In conclusion, a classical solution based on PI structures can be designed to provide the same performance as the Adaptive SMC at some operation point, but changes in the operation conditions are not compensated by the PI controllers due to the lack of robustness, which leads to unsafe bus voltage performances that could damage the devices connected to the bus. Instead, the proposed Adaptive SMC provides the same desired performance under any operating condition, thus ensuring the safe operation of the bus and all connected devices. In addition, the Adaptive SMC ensures a maximum switching frequency imposed by (25) and a minimum switching frequency reported in (26), which, in this example, produces lower power losses in comparison with the classical solution.

5.1.3. Response to Current Pulses

The design of the capacitor $C_{dc}$ previously described in Section 4.4 considers step changes in the bus current $i_{dc}$, which corresponds to a non-linear load because the impedance $Z_L$ changes when the bus voltage $v_{dc}$ has dynamic transients, i.e., $Z_L=v_{dc}/i_{dc}$ is not constant. However, some loads may exhibit high-current pulses, which the proposed system can regulate based on pulse characteristics.

A load current pulse can be described by two parameters: the pulse duration $T_p$ and amplitude $I_p$. Since the pulse is usually very fast, all the pulse current is provided by the $C_{dc}$ capacitor; thus, the charge $Q_p$ extracted from $C_{dc}$ during the current pulse is $Q_p=T_p·I_p$. Such a charge extraction from $C_{dc}$ produces a voltage reduction $V_p=Q_p/C_{dc}$. On the other hand, when the bus voltage is reduced to the maximum deviation defined by $MO$, the capacitor $C_{dc}$ loses a charge $Q_{MO}=C_{dc}·MO$. Then, any current pulse with $Q_p\le Q_{MO}$ will be compensated by the proposed system. Inequality (37) formalizes the acceptable relation between $I_p$ and $T_p$ for a load current pulse; if such a relation is not fulfilled, then $C_{dc}$ must be increased, otherwise the pulse will not be correctly compensated.

$$\begin{array}{c}\hfill T_p·I_p\le C_{dc}·MO\end{array}$$

(37)

In the design example of this section $Q_{MO}=C_{dc}·MO=253\mathsf{\mu }\mathrm{F}·1.2\mathrm{V}=303.6\mathsf{\mu }\mathrm{C}$. A load current pulse with 500% amplitude with respect to the nominal value of $1\mathrm{A}$ ($I_p=5\mathrm{A}$) and a duration of $T_p=60\mathsf{\mu }\mathrm{s}$ will impose a charge extraction of $300\mathsf{\mu }\mathrm{C}$, thus fulfilling restriction (37). Therefore, such a load current pulse with 500% amplitude will be correctly regulated. This is tested in the circuital simulation reported in Figure 8, which considers the 500% current pulse ($5\mathrm{A}$) with $60\mathsf{\mu }\mathrm{s}$ duration.

Figure 8a shows the application of the $5\mathrm{A}$ current pulse in $i_{dc}$ at 3 ms, where the DC bus voltage is correctly constrained to $MO\le 1.2\mathrm{V}$, i.e., $v_{dc}\ge 22.8\mathrm{V}$. Similarly, since the battery current is imposed by the inductor current ($i_L=i_b$), the derivative of the battery current is limited following (22), which in this design example must fulfill ${\displaystyle \frac{d{i}_b}{dt}}$ < 50 A/ms. Finally, it is observed that the desired settling time is achieved, i.e., $t_s$ < 5 ms. Figure 8b shows a zoom between 2.95 ms and 3.15 ms, where the detail of the load current pulse in $i_{dc}$ is observed. Moreover, the zoom in Figure 8b shows the detail of the bus voltage $v_{dc}$ waveform, where the voltage drop produced by the charge $Q_p$ extraction is evident. Since $Q_p<Q_{MO}$, then the bus voltage deviation is lower than the design limit, i.e., $MO\le 1.2\mathrm{V}$. Finally, the bottom traces of Figure 8b confirm that ${\displaystyle \frac{d{i}_b}{dt}}$ < 50 A/ms even under a very large (500%) load current pulse.

In conclusion, any current pulse produced by the load that fulfills restriction (37) is correctly compensated. However, the $C_{dc}$ capacitor must have sufficient current rating; otherwise, it will be damaged.

5.2. Experimental Results

The proof-of-concept of the proposed solution was implemented in a laboratory environment, as shown in Figure 9. The bidirectional buck-boost converter was developed with a branch of Taraz’s SPM-FB full bridge using G3R75MT12D transistors (Global Power Synergies, Lake Forest, USA) and the series connection of two 43ML5M capacitors (Rubycon Corporation, Ina, Japan) making $C_{dc}=253\mathsf{\mu }\mathrm{F}$, the LC filter consists of the inductor $L=330\mathsf{\mu }\mathrm{H}$ and a capacitor $22\mathsf{\mu }\mathrm{F}$ connected in parallel with the battery. For safety reasons, a manual switch allows the battery to be disconnected. The Kepco BOP-5020GL ( Kepco Inc., New York City, USA) four-quadrant source/load was used to emulate DC bus operation, enabling programming of current changes on the DC bus. The control strategy was implemented using the TI LAUNCHXL-F28379D development board (Texas Instruments, Dallas, USA), which produces the switching functions for the Taraz GDC-2A4S1 drivers (Taraz Technologies, Islamabad, Pakistan), with dead time configured to $0.64\mathsf{\mu }\mathrm{s}$ because its adjustable range is $0.39579\mathsf{\mu }\mathrm{s}$ to $8.3\mathsf{\mu }\mathrm{s}$. Voltage dividers with the OPA484 in follower mode enable the sensing of DC bus and battery voltages. The AD8210 sensor (Analog Devices, Wilmington, USA) included in the LC Filter card measures the inductor current, and the ACS712 sensor (Allegro MicroSystems Inc., Manchester, USA) measures the $i_{dc}$ current. A Tektronix MDO3024 oscilloscope, TPP0500 voltage probes, and TCP0020 current probes (Tektronix Inc., Beaverton, USA) were used to verify the system’s operation. Finally, in the experimental set-up the Kepco BOP-5020GL four-quadrant source/load was used to pre-charge the DC-bus capacitor at nominal voltage ($24\mathrm{V}$), which protects the battery from high start-up currents and avoids the construction of classical start-up circuits like the solution discussed in Appendix B.

Figure 10 shows the experimental results for discharge, stand-by, and charge modes; the magenta line is the bus voltage, which remains at 24 V for all the operating conditions; the blue line is $i_L$, and the light blue line is $i_{dc}$. For discharge mode, $i_{dc}$ = 1 A produces $i_L\cong$ 2.1 A, which is consistent with the boost converter operation because battery voltage is 12.8 V. In charging mode, $i_{dc}$ = −1 A produces $i_L\cong$−1.6 A with a 13.2 V battery voltage; these results show that the battery voltage varies with operating mode. In discharge mode, the battery voltage is lower than its nominal value, resulting in higher gain voltage and current, i.e., a higher inductor current than in charge and stand-by modes. As the figure shows, after a step-like DC bus current change, inductor current changes with a slope of 0.75 A/ms, fulfilling the design restrictions, and the DC bus voltage shows a transient behavior with $MO\le$ 1.2 V and $t_s\le$ 5 ms, which is in agreement with the design procedure and simulation results.

To evaluate the robustness of the adaptive controller, adding a $220\mathsf{\mu }\mathrm{F}$ capacitor in parallel with the DC bus capacitance ($C_{dc}$) allows emulating changes in the charger/discharger parameters. Figure 11 shows results for discharge, stand-by, and charge modes with the additional $220\mathsf{\mu }\mathrm{F}$ capacitor; the bus voltage remains at 24 V across all operating conditions, with less oscillation in steady-state operation. For discharge mode, $i_{dc}$ = 1 A and $i_L\cong$ 2.1 A for $v_b$ = 12.8 V; in charging mode, $i_{dc}$ = −1 A and $i_L\cong$−1.6 A with a 13.2 V battery voltage. The transient behavior is similar to the results in Figure 10, i.e., $MO\le$ 1.2 V and $t_s\le$ 5 ms, fulfilling the design criteria and in agreement with simulation results in the Section 5.1.1. It is important to note that reducing $C_{dc}$ or changing the inductor value requires desoldering and soldering new components, which can affect the integrity of the Taraz bridge and the LC filter; therefore, no additional parametric changes were considered in the experimental case.

Another experimental test based on the classical cascade PI control strategy, designed in Section 5.1.2, provides an additional evaluation of the proposed approach. Figure 12 shows results for discharge, stand-by, and charge modes. For the discharging mode, the design criteria are fulfilled because $MO\le$ 1.2 V and $t_s\le$ 5 ms, but the transition from discharging to stand-by shows a settling time higher than 5 ms. Also, from stand-by to charging mode $MO$ > 1.2 V, these results show a proper regulation of the DC bus voltage at 24 V for the three operation modes. However, the transient behavior does not always meet the design criteria because the PI control is designed based on a small-signal model around the discharge operating point. Otherwise, the adaptive controller proposed in this work meets the design criteria at all operating points, as shown in Figure 10 and Figure 11.

The adaptive SMC control strategy exhibits proper transient behavior at all operating points, whereas the PI control strategy does not, due to the linearization required for PI design. Additionally, power losses and efficiency highlight the advantage of the adaptive SMC strategy over the PI control. Figure 13 shows the battery power $\left(P_{Bat}\right)$ in black line and the power at the DC bus $\left(P_{dc}\right)$ in red line, while regulating $v_{dc}$ at 24 V in discharging and charging modes for the adaptive SMC control (Figure 13a,c) and PI control (Figure 13b,d). In discharging mode, the battery acts as a power source and the DC bus as a power load. Figure 13a shows $2.7$ W power losses yielding 90% efficiency, while Figure 13b shows $4.22$ W power losses yielding $85.1\%$ efficiency. In charging mode, the battery acts as a power load, and the DC bus as a power source; due to the change in the energy flow, the power measures show a negative sign. Figure 13c shows $3.09$ W power losses yielding $87.6\%$ efficiency, while Figure 13d shows $3.59$ W power losses yielding $85\%$ efficiency. Efficiency results demonstrate that the proposed adaptive SMC controller is a better option than the PI control strategy due to lower power losses. It is important to note that the dead time between switching signals was not accounted for in the efficiency analysis, as a fixed value of $0.64\mathsf{\mu }\mathrm{s}$ was set in accordance with the driver manufacturer’s recommendations and maintained throughout all tests; besides that dead time introduces a delay lower than $5.1\%$ for switching signals with frequency lower than 80 kHz, thus its effect is negligible.

Power losses in power converters increase with higher switching frequency; in this sense, Figure 14 shows the steady-state inductor current in blue line and the switching signal in green line for charging (Figure 14a), stand-by (Figure 14b), and discharging (Figure 14c) modes concerning the adaptive SMC controller. Figure 14d shows the same variables in discharge mode for the PI controller; only discharge mode is shown because this strategy operates at a fixed frequency across all operating modes. Figure 14 highlights that inductor current ripple is between 290 mA and 340 mA for both control strategies and for all operating points, due to the hysteresis band in the adaptive SMC controller, and to the 80 kHz fixed frequency in the PI controller (see Figure 14d). The small variation in the inductor current ripple measured by the oscilloscope is caused by the current ringing occurring in the MOSFETs, but such a variation does not affect the system operation since the SMC is globally stable. For the adaptive SMC controller, the switching frequency is higher in discharge mode (68.49 kHz) than in charging (52.91 kHz) or stand-by (54.95 kHz) modes, because the battery voltage drops while battery discharge, causing an increase in the voltage and current gain, yielding an increase in the inductor current and switching frequency. Nevertheless, the switching frequency is lower with the adaptive SMC controller than with the PI controller for the same inductor current ripple, which explains the better efficiency of the control strategy proposed in this work.

To demonstrate the flexibility of the charger/discharger system, Figure 15 shows an additional experiment with higher load power; thus, 1 A step changes in $i_{dc}$ allow evaluation of the system behavior. This test is limited to $i_L\le$ 5 A because that is the maximum average current supported by the commercial inductor 2318-V-RC172. In the charging scenario, $i_L$ reaches −5 A when $i_{dc}$ = −3 A showing 72 W of power on the DC bus due to $v_{dc}$ = 24 V, and 66 W of power on the battery due to $v_b$ = 13.2 V; for this operating point, the system reaches $91.6\%$ of efficiency. For discharging scenario, $i_L$ reaches 5 A when $i_{dc}$ = 2 A showing 48 W of power on the DC bus due to the regulated DC bus voltage, i.e., $v_{dc}$ = 24 V; also the system shows 63 W of battery power due to $v_b$ = 12.6 V; for this operating point, the system reaches an efficiency of $76.2\%$. It is important to highlight that for all current step changes, the DC Bus voltage reaches the reference value ($v_{dc}$ = 24 V) with a settling time lower than 5 ms and a $MO$ lower than 1.2 V. These results confirm the adaptability of the charger/discharger platform to a higher load power while fulfilling the design criteria.

The system response to a high current pulse in the DC bus is reported in Figure 16, which shows the experiment with a temporal overload of $300\%$, i.e., $i_{dc}$ = 3 A. It is important to highlight that the Kepco source/load used to program the current changes on the DC bus does not allow current pulses shorter than $100\mathsf{\mu }\mathrm{s}$ because of its rise time limit; therefore, the $i_{dc}$ pulse in Figure 16 is not a square pulse but reaches the desired peak amplitude. For the test, the system operates in a stand-by mode when the action of the $i_{dc}$ pulse causes $v_{dc}$ to decrease during $112\mathsf{\mu }\mathrm{s}$ without exceeding the expected 1.2 V voltage drop, i.e., $MO$ = 1.2 V. In addition, the $i_{dc}$ pulse cause an increment in $i_L$ to compensate the voltage drop in $v_{dc}$, therefore, the inductor current shows an slope of ${\displaystyle \frac{d{i}_b}{dt}}\cong$ 17.8 A/ms fulfilling the design criteria. After $i_{dc}$ returns to 0 A, inductor current shows the ripple caused by the switching operation required to regulate the DC bus voltage, and therefore $v_{dc}$ increases, showing a voltage ripple and causing a current ripple in $i_{dc}$. These results agree with the analysis in Section 5.1.3 and with Equation (37), showing that even under critical current overload, the design criteria are fulfilled.

The experimental results demonstrate the feasibility of the proposed solution for charging and discharging second-life batteries, including its operating restrictions on the converter-controller design.

6. Conclusions and Future Works

A charger/discharger system based on a bidirectional boost converter with cascade control was proposed: Internal current control based on sliding modes and external voltage control based on an adaptive PI. The design of the power stage elements, inductor, and capacitor limits the derivative of the battery current and ensures the overall stability of the system. The system was validated through PSIM simulations and experimental tests for a 12 V battery and a 24 V DC bus in charge mode (−1 A), discharge mode (+1 A), and standby mode (0 A). The system strictly complies with performance constraints: A settling time of less than 5 ms and a maximum overshoot of 5%. In addition, the maximum switching frequency and the maximum rate of change of battery current derivative are limited, reducing degradation of second-life batteries. The results confirm the feasibility and effectiveness of the proposed approach, and a synthesized design procedure is presented that coherently integrates the control and power stages, facilitating its practical implementation in other types of battery chargers/dischargers.

Limiting the current derivative ($di/dt$) in batteries is essential to preserve their electrochemical integrity and extend their service life. In new batteries, this limitation protects the solid–electrolyte interface (SEI) and prevents the formation of inactive metallic lithium, reducing capacity from the first cycle. In second-use batteries, whose internal resistance increases and capacity decreases, strict control of $di/dt$ is critical to avoid deep voltage drops, overheating, and cell imbalances. This limitation must be implemented in both the converter design (using inductive filters) and the controller, with the controller dynamically adjusting the limits based on the battery’s state of health.

Although the use of high-capacity SiC devices in very low-power applications results in significant efficiency losses, especially at high switching frequencies, the Taraz SPM-FB platform is highly suitable for proof-of-concept testing to validate functionality, stability, and control strategies. In fact, the proof-of-concept prototype developed in this paper achieved an efficiency of 90%. Nevertheless, future work will focus on designing a new prototype with components optimized for the precise current and voltage levels required by both the battery and the DC bus, thereby improving overall efficiency and reducing system cost.

This work also shows an interesting comparison between fixed and variable switching frequency in power converters. Control systems with variable switching frequency introduces some disadvantages with respect to fixed-frequency control techniques: (i) the passive elements of the converter must be designed for the lowest frequency to avoid high switching ripples; (ii) in variable frequency systems the switching losses could become very high if the switching frequency is not limited; and (iii) the variable frequency produces electromagnetic interference (EMI) in a wider frequency spectrum, while fixed-frequency techniques concentrate the EMI at the constant switching frequency; hence, it is easier to filter. However, this paper has adopted several techniques to mitigate (not avoid) those problems in the co-design of both the power stage and adaptive sliding-mode controller: (i) the co-design process considers an iterative design of the hysteresis band (23) and inductor (22) to impose the desired minimum switching frequency, thus avoiding very large passive elements. Moreover, (ii) the hysteresis width of the SMC (24) is calculated to limit the maximum switching frequency, also limiting the switching losses. This aspect was experimentally verified with the results reported in Figure 13, where the proposed adaptive SMC solution exhibits higher efficiency in comparison with a traditional PWM-based PI controller operating at fixed frequency. In addition, (iii) the combined limitation of both the minimum and maximum switching frequencies defines a predictable operational EMI frequency spectrum. This reduces the peak power of the EMI noise observed at the fixed frequency of traditional PWM solutions but requires wider (or adaptive) EMI filters. The design of those EMI filters is under investigation.

Other interesting aspects of SMC include its improved transient response, as the controller keeps the switching period active until the controlled variable reaches the desired value; however, this results in a variable switching frequency. In addition, the SMC could provide global stability and robustness to changes in converter parameters, but its design is much more complex than that of a classical PID controller. Moreover, despite the SMC having a very simple control law (23), its implementation requires precise analog comparators and custom circuits, whereas classical fixed-frequency controllers can be implemented with readily available integrated circuits. Those last two characteristics make the PID alternative much more common in industrial applications. Finally, this paper is aimed at simplifying the design of adaptive SMC approaches by providing an easy-to-follow co-design procedure for both the power stage and control system.

Considering the contributions of this work: integration of power and control stage design, current derivative limitation, robustness, and precise regulation, it is possible to propose future work addressing current challenges in energy storage, smart power electronics, and transport decarbonization.

A first task is to extend the integrated design methodology to hybrid storage systems (battery + supercapacitor), with a focus on dynamic power management and peak current mitigation. This work would explore the adaptation of the simultaneous converter-controller approach for hybrid systems, leveraging supercapacitors’ ability to absorb current transients while batteries operate in slow-current-change. The impact on the overall system lifetime and energy efficiency under real load profiles, such as those found in urban microgrids or electric transportation, would be evaluated.

Another possible task is the design of a smart converter with self-reconfiguration capabilities based on the battery’s state of health (SoH) and grid conditions. Building on the robustness and stability of the current system, it proposes incorporating online diagnostic algorithms and adaptive control strategies that dynamically adjust the $di/dt$ limits and the control loop dynamics in response to storage degradation. The above would preserve the quality of the DC bus and further extend the system’s operability in the face of aging or incipient failures.

The use of other control techniques in the integrated methodology is another possible area for future work. The overall methodology presented is based on regulating the inductor current to ensure global stability, using the sliding-mode technique. In addition, the power stage co-design is performed to ensure global stability across all operating conditions and safe DC-bus characteristics. This same approach can be applied to other control techniques, such as passivity-based current control. However, the equations for co-designing the power-stage parameters must be modified to reflect the new stability conditions. Therefore, it can be used to extend the co-design process by accounting for other globally stable control techniques more suited to particular applications, such as motor control or renewable generation systems.

Finally, this work could be extended to the implementation and experimental validation of the methodology in a bidirectional charger for electric vehicles, with integration into the smart grid (V2G/G2V) and compliance with harmonic injection and flicker regulations. This work would transfer the solution proposed in this article to the field of electric mobility, evaluating its performance under fast-charging, power injection into the grid, and supply-voltage fluctuations. It would focus on ensuring compliance with standards such as IEEE 1547 [64] and IEC 61000-3-12 [65] and on validating not only DC bus stability but also power quality at the common coupling point.