Model-Based Control Assessment of PFC Systems with High-Conversion-Ratio DC–DC Converters

Abstract

This paper presents a model-based control strategy for a power factor correction system that employs a high conversion-ratio DC–DC converter. The proposed system consists of two stages. In the first stage, a full-bridge diode rectifier is connected to the grid through a passive filter to improve the quality of the injected current. Two passive AC input filters, namely L and $LCL$ configurations, are evaluated to analyze their impact on grid current quality and overall system performance. The second stage is a high-step-up DC–DC converter based on the switched-inductor technique, which provides a high voltage conversion ratio. A model-based approach is employed to derive the control design from the averaged system model. The resulting control structure consists of a current tracking loop and a voltage regulation loop. A proportional-resonant controller is used to ensure current tracking and achieve a near-unity power factor, while a proportional-integral controller regulates the output voltage. Experimental validation is carried out using a low-power laboratory-scale prototype to assess the effectiveness of the proposed approach. The results demonstrate adequate current tracking and satisfactory dynamic performance within the tested operating conditions.

1. Introduction

Internal combustion engine vehicles are still widely used. However, significant drawbacks are presented, including greenhouse gas emissions and dependence on fossil fuels. Therefore, the transition to cleaner alternatives has been driven by the adoption of electric vehicles (EVs) and plug-in hybrid electric vehicles (PHEVs), which have been identified as a promising solution. As a result, the growth in EV and PHEV sales has spurred the development of new technologies, particularly in battery charging systems. According to the Society of Automotive Engineers (SAE), these charging systems are classified as on-board chargers and off-board chargers [1]. On-board chargers (OBCs) are typically operated at Level 1, with power levels below 3 kW, or at Level 2, with power levels up to approximately 7–22 kW. These chargers are considered semi-fast and are supplied by single-phase or two-phase power sources. In contrast, Level 3 chargers, commonly referred to as fast chargers and generally implemented as off-board systems, are supplied by three-phase power sources and enable significantly higher power levels [2]. In particular, a structure similar to that shown in Figure 1 is commonly employed in Level 1 and Level 2 chargers.

A greater impact on the electrical grid is observed as the adoption of electric vehicles increases, leading to power quality issues, voltage instability, higher peak demand, increased losses, and transformer overload. Furthermore, harmonic distortion can be introduced into the grid current by the massive and uncoordinated connection of chargers, resulting in power factor degradation and affecting the performance of other equipment connected to the same point of common coupling. Therefore, high-performance power factor correction (PFC) is required in EV chargers to ensure a sinusoidal input current, reduce harmonic content, and improve overall system efficiency [3,4,5].

As shown in Figure 1, Level 1 and Level 2 EV chargers typically incorporate a dedicated stage to ensure power factor correction. This stage generally consists of a rectification unit followed by a DC–DC conversion stage. For this type of application, a wide variety of DC–DC converters can be employed; however, the selection of the appropriate topology depends on the specific requirements of the application, particularly the input and output voltage levels, power rating, and performance constraints. For instance, boost converters are commonly adopted in PFC applications due to their suitability for systems requiring voltage step-up capability [6,7], while Buck converters are preferred in low-voltage regulation applications [8,9]. Buck–Boost converters provide both step-up and step-down capabilities, making them suitable for systems with wide input voltage variations [10,11]. On the other hand, isolated topologies such as Flyback converters are typically employed in low- to medium-power applications requiring galvanic isolation, including battery chargers and auxiliary power supplies [12,13]. Therefore, selecting an appropriate topology is a critical design decision that directly influences the efficiency, cost, and performance of the overall system.

As previously mentioned, the conventional boost converter is widely used in PFC applications due to its simple structure, continuous input current, straightforward control scheme, and ability to achieve a high power factor [2,14]. However, despite these advantages, several drawbacks are identified, mainly related to the high electrical stress imposed on the output diode and the full-bridge rectifier. As a result, additional power losses are introduced due to the diode reverse-recovery phenomenon, which leads to a noticeable reduction in overall system efficiency [15,16]. To overcome these limitations, several PFC topologies derived from the conventional boost structure have been reported in the literature [14,16,17,18,19]. Among these alternatives, bridgeless configurations have received significant attention. In such structures, the conventional uncontrolled diode bridge is replaced by a controlled rectification stage, which reduces conduction losses and enhances the overall conversion efficiency [20,21].

For instance, in [22,23,24], several converters derived from the totem-pole topology are introduced. This configuration has been extensively adopted in PFC applications due to its high power quality, reduced component count, and compact structure, by which higher power density and improved thermal behavior are achieved [25,26]. Although the totem-pole approach has proven to be effective, with a power factor above 0.95 and an input current total harmonic distortion below 5% being ensured, certain limitations remain. Under high-power conditions, considerable stress is produced in both semiconductor devices and inductors due to elevated current levels. While this issue can be alleviated by interleaved topologies, additional complexity, cost, and a higher number of components are introduced [27,28]. Moreover, the same voltage gain as that of the conventional boost converter is provided by the totem-pole structure. Consequently, in applications such as electric vehicle chargers, where high DC bus voltages (typically around 400 V) are required, a wide step-up conversion ratio must be ensured. This condition generally results in operation at high duty cycles, by which power losses may be increased and efficiency may be negatively affected [29,30].

In this regard, the boost converter with voltage doubler has been widely adopted in PFC applications, as a higher voltage gain can be achieved without a significant increase in the duty cycle [31]. However, several disadvantages are introduced by this approach, including increased circuit complexity, the requirement for additional switching devices, higher power dissipation, and potential reliability issues, particularly under high-power conditions. In some cases, high current stresses are generated. To address the issues associated with high current stresses, multiphase converters have been proposed, by which current stresses in the semiconductor devices are reduced and system efficiency is improved, while a high voltage gain is ensured.

For instance, in [32], a two-inductor interleaved PFC boost converter is presented, in which voltage doubler operation is achieved for duty cycles greater than 0.5, making it suitable for universal input voltage ranges (90–264 Vrms). In [33], a high-gain, multilevel, interleaved, single-phase PFC boost converter based on the switched-capacitor concept is proposed. In this configuration, interphase transformers and switched-capacitor cells are incorporated to enable current sharing between branches and to significantly enhance the voltage gain. In [34], a family of hybrid SEPIC rectifiers with PFC based on switched capacitors is presented, in which semiconductor stress reduction and voltage gain enhancement are achieved through the inclusion of additional cells. Similarly, in [35], a family of three-level unidirectional PFC rectifiers based on switched capacitors is introduced, where high voltage gain and reduced semiconductor stress are obtained. However, although these topologies allow a high DC–DC conversion ratio to be ensured, together with a near-unity power factor and low total harmonic distortion, a drawback is presented due to the high number of components, by which system complexity and cost are increased.

For this reason, the switched-inductor technique has emerged as an attractive solution for achieving high conversion ratios. However, its application has been mainly limited to high-gain DC–DC converters [36,37]. Another challenge associated with boost converters in PFC applications is the injection of high-frequency harmonics into the mains current. This issue arises from the switching operation of the DC–DC stage, which introduces harmonic distortion into the input current. Therefore, an input filter is typically required to mitigate these disturbances and prevent their propagation to the power grid [38,39,40]. Moreover, conventional boost-based PFC converters rely on control strategies that simultaneously regulate the DC bus voltage and ensure power factor correction [41,42]. Although classical control methods are widely adopted, their application to high-gain converters remains limited due to increased system order and complexity. Motivated by these challenges, this work proposes a PFC system based on a high-gain DC–DC converter using the switched-inductor technique. Two passive filtering configurations, namely L-type and LCL-type, are considered to improve input current quality. In addition, a mathematical model and a model-based control strategy are developed to ensure output voltage regulation and a sinusoidal input current in phase with the grid voltage. Therefore, the leading contributions of the present work are presented as follows.

• A model-based control strategy for a PFC system employing a high conversion ratio DC–DC converter based on the switched-inductor technique is presented.
• An input filtering stage is incorporated between the grid and the rectifier, and a comparative evaluation between L and LCL filter configurations is carried out to assess their impact on grid current quality.
• A control strategy derived from the averaged model is proposed, including a proportional-resonant controller for current tracking and a proportional-integral controller for output voltage regulation.
• Experimental validation under steady-state and transient conditions is provided to demonstrate the effectiveness and performance of the proposed model-based control strategy.

The remainder of this paper is organized as follows. Section 2 introduces the description and modeling of the proposed SISUC-PFC system, including its operating principles and key analytical expressions. Section 3 presents the design methodology of the proposed control scheme, detailing both the inner current loop and the outer voltage loop. Section 4 discusses the prototype design considerations and provides experimental results to validate the performance of the proposed system under different operating conditions. Finally, Section 5 concludes the paper by summarizing the main findings and outlining directions for future work.

2. System Description and Modeling

The Switched-Inductor Step-Up Converter as a PFC (SISUC-PFC) is illustrated in Figure 2. This topology is composed of two main stages, described as follows. The first stage corresponds to a full-bridge diode rectifier (FBDR) connected to the electrical grid through a passive filter. Its purpose is to improve the quality of the current injected into the grid and to supply the DC voltage required by the second stage. In this work, two passive AC input filters, an L filter and an $LCL$ filter, interconnected to the grid, as shown in Figure 2, are evaluated to determine their impact on grid-current quality and overall system performance. The second stage is an SISUC DC–DC converter that provides a regulated output voltage $v_0$. In this converter, the switched-inductor technique is employed to achieve a significantly higher voltage conversion ratio than the conventional step-up converter. The grid source is modeled through its equivalent impedance, where $L_S$ and $R_S$ represent the grid-side inductance and its associated parasitic resistance, respectively. Furthermore, $v_{Si}$ denotes the grid voltage, and $v_S$ denotes the voltage at the point of common coupling (PCC) with the grid.

2.1. Model of the DC–DC Stage

The system model of the SISUC-PFC converter is obtained by analyzing its two main stages separately. The first part focuses on the DC–DC conversion stage. In this analysis, the DC–DC stage is assumed to operate in continuous conduction mode (CCM), and all components are considered ideal. Additionally, all inductors in the DC–DC structure are assumed to have the same inductance values. Under these assumptions, two distinct operating modes can be identified, determined by the switching states of switches $M_1$ and $M_2$. The first operating mode occurs when switches $M_1$ and $M_2$ are turned on, allowing the input voltage $v_{DCi}$ to energize the inductors $L_i$, in which energy is stored. During this interval, diode D remains reverse-biased, and the output capacitor $C_0$ provides energy to the load $R_0$. Conversely, in the second operating mode, switches $M_1$ and $M_2$ are turned off, thereby forward-biased diode D. In this mode, the energy previously stored in the inductors $L_i$ is released and transferred to both the output capacitor $C_0$ and the load $R_0$. The averaged model of the DC–DC stage is derived by applying Kirchhoff’s current and voltage laws to the circuits described by the operation modes, yielding in

$$\begin{array}{ccc}\hfill L_i{\displaystyle \frac{d{i}_{Li}}{dt}}& =& -{\displaystyle \frac{u_{\mathbf{c}}{v}_0}{2}}+{\displaystyle \frac{v_{DCi}}{2}}(2-u_{\mathbf{c}}),\hfill \end{array}$$

(1)

$$\begin{array}{ccc}\hfill C_0{\displaystyle \frac{d{v}_0}{dt}}& =& u_{\mathbf{c}}{i}_{Li}-{\displaystyle \frac{v_0}{R_0}},\hfill \end{array}$$

(2)

where $u_{\mathbf{c}}\triangleq (1-d_{\mathbf{c}})$ represents the control signal; $d_{\mathbf{c}}$ denotes the continuous PWM modulating signal (duty cycle), which takes values in the range $(0,1)$; $v_{DCi}$ represents the voltage at the output of the rectification stage; $i_{Li}$ denotes the current flowing through the inductors $L_i$ of the DC–DC stage; and $v_0$ represents the output voltage. By considering (1) and (2), the steady-state conversion ratio of the DC–DC converter topology is derived as

$$v_0={\displaystyle \frac{1+d}{1-d}}{v}_{DCi}.$$

(3)

It can be observed that the proposed converter exhibits a higher conversion ratio than the conventional DC–DC boost converter. The inductor current ripple and capacitor voltage ripple of the DC–DC stage can be calculated as follows:

$$\begin{array}{ccc}\hfill \Delta i_{L_i}& =& {\displaystyle \frac{V_{D{C}_i}D}{L_i{f}_{sw}}},\hfill \end{array}$$

(4)

$$\begin{array}{ccc}\hfill \Delta v_{C_0}& =& {\displaystyle \frac{I_{out}D}{C_0{f}_{sw}}}.\hfill \end{array}$$

(5)

The critical inductor and capacitor values required to ensure continuous conduction mode (CCM) operation are given by:

$$\begin{array}{ccc}\hfill L_i& >& {\displaystyle \frac{D{R}_0{(1-D)}^2}{(1+D)f_{sw}}},\hfill \end{array}$$

(6)

$$\begin{array}{ccc}\hfill C_0& >& {\displaystyle \frac{D}{2R_0{f}_{sw}}}.\hfill \end{array}$$

(7)

2.2. Model of the Passive Filter

2.2.1. Modeling with L Filter

As shown in Figure 2, to enable the converter to operate with PFC functionality, an additional rectifier stage is incorporated. Moreover, two different types of input filters are considered for the rectifier stage. Accordingly, either an L or an $LCL$ coupling filter is employed. To analyze the dynamic behavior of the PFC stage, the system model considering the L-filter is derived as follows:

$$L_{11}{\displaystyle \frac{d{i}_{L11}}{dt}}=v_S-v_i.$$

(8)

To obtain a more convenient system model structure for control scheme design, the electrical grid parameters are taken into account, and the following definition is introduced.

$${\displaystyle \frac{i_{L11}}{\left|i_{L11}\right|}}={\displaystyle \frac{\left|i_{L11}\right|}{i_{L11}}}=\mathrm{sgn}\left(i_{L11}\right)=\left\{\begin{array}{cc}1\hfill & \mathrm{for}{i}_{L11}>0,\hfill \\ \mathrm{undef}\hfill & \mathrm{for}{i}_{L11}=0,\hfill \\ -1\hfill & \mathrm{for}{i}_{L11}<0.\hfill \end{array}\right.$$

(9)

Additionally, the following transformations are considered

$$\begin{array}{ccc}\hfill i_{Li}& =& \mathrm{sgn}\left(i_{L11}\right)i_{L11},\hfill \end{array}$$

(10)

$$\begin{array}{ccc}\hfill v_{DCi}& =& \mathrm{sgn}\left(i_{L11}\right)v_S,\hfill \end{array}$$

(11)

$$\begin{array}{ccc}\hfill e_{i1}& =& \mathrm{sgn}\left(i_{L11}\right)u_1{v}_{C0},\hfill \end{array}$$

(12)

where $i_{L11}$ represents the current flowing through the coupling inductor $L_{11}$, and $\left|i_{L11}\right|$ denotes its absolute value. Moreover, $e_{i1}$ corresponds to the actual control input of the system. Subsequently, by applying the transformations defined in (10)–(12) to (1), the current dynamics of the SISUC-PFC equipped with an L filter are expressed in terms of the grid parameters. As a result, the current dynamics of the system shown in Figure 2 with an L filter are obtained as follows:

$$(L_{11}+L_i){\displaystyle \frac{d{i}_{L11}}{dt}}=-{\displaystyle \frac{e_{i1}}{2}}+v_S-{\delta }_1,$$

(13)

where ${\delta }_1$ is defined as a harmonic disturbance, given as ${\delta }_1=u_1{v}_S/2$.

2.2.2. Modeling with LCL Filter

The second case under analysis considers the system shown in Figure 2 operating with an $LCL$ filter. This filter is composed of two inductors, $L_{21}$ and $L_{22}$, and a capacitor $C_{21}$. Accordingly, the input dynamics are derived by applying Kirchhoff’s current and voltage laws and are expressed as

$$\begin{array}{ccc}\hfill L_{21}{\displaystyle \frac{d{i}_{L21}}{dt}}& =& -v_{C21}+v_S,\hfill \end{array}$$

(14)

$$\begin{array}{ccc}\hfill C_{21}{\displaystyle \frac{d{v}_{C21}}{dt}}& =& i_{L21}-i_{L22},\hfill \end{array}$$

(15)

$$\begin{array}{ccc}\hfill L_{22}{\displaystyle \frac{d{i}_{L22}}{dt}}& =& -v_i+v_{C12}.\hfill \end{array}$$

(16)

Furthermore, to derive a model structure more suitable for control design, and following the procedure previously applied to the current $i_{L11}$, the following definition for $i_{L22}$ is introduced:

$$sgn\left(i_{L22}\right)=\left\{\begin{array}{cc}1\hfill & \mathrm{for}{i}_{L22}>0\hfill \\ \mathrm{undef}\hfill & \mathrm{for}{i}_{L22}=0\hfill \\ -1\hfill & \mathrm{for}{i}_{L22}<0,\hfill \end{array}\right.$$

(17)

and the following transformations are also considered

$$\begin{array}{ccc}\hfill i_{Li}& =& sgn\left(i_{L_{22}}\right)i_{L22},\hfill \end{array}$$

(18)

$$\begin{array}{ccc}\hfill v_{DCi}& =& sgn\left(i_{L_{22}}\right)v_{C21},\hfill \end{array}$$

(19)

$$\begin{array}{ccc}\hfill e_{i2}& =& sgn\left(i_{L_{22}}\right)u_2{v}_{C22},\hfill \end{array}$$

(20)

where $i_{L22}$ represents the inductor current of $L_{22}$ and $e_{i2}$ is the control input to the system. Thus, the current dynamics of the SISUC stage, described by (1), are combined with the transformations (17) to (20), resulting in

$$L_i{\displaystyle \frac{d{i}_{L22}}{dt}}=-{\displaystyle \frac{e_{i2}}{2}}+v_i-u_2{\displaystyle \frac{v_{C21}}{2}}.$$

(21)

Now, the current dynamics describing the inductor currents $L_{22}$ and $L_{i2}$ are obtained by considering (16) and (21), resulting in

$$(L_i+L_{22}){\displaystyle \frac{d{i}_{L22}}{dt}}=-{\displaystyle \frac{e_{i2}}{2}}+v_{C21},$$

(22)

where

$$u_2={\displaystyle \frac{e_{i2}}{sgn\left(i_{L22}\right)v_{C22}}}.$$

(23)

Therefore, the dynamics associated with the $LCL$ filter and the DC–DC stage current are expressed as

$$\begin{array}{ccc}\hfill L_{21}{\displaystyle \frac{d{i}_{L21}}{dt}}& =& -v_{C21}+v_S,\hfill \end{array}$$

(24)

$$\begin{array}{ccc}\hfill C_{21}{\displaystyle \frac{d{v}_{C21}}{dt}}& =& i_{L21}-i_{L22},\hfill \end{array}$$

(25)

$$\begin{array}{ccc}\hfill (L_{22}+L_i){\displaystyle \frac{d{i}_{L22}}{dt}}& =& -{\displaystyle \frac{e_{i2}}{2}}+v_{C21}-{\delta }_2,\hfill \end{array}$$

(26)

as previously mentioned, ${\delta }_2$ represents a harmonic perturbation. It is important to note that the output voltage dynamics of the PFC-SISUC stage are independent of the selected input filter configuration; therefore, the output voltage dynamics of both systems are described by

$$C_0{\displaystyle \frac{d{v}_{C0}}{dt}}=u_{\mathbf{c}}{i}_{Li}-{\displaystyle \frac{v_0}{R_0}}.$$

(27)

To obtain a more convenient structure for control design, (2) can be reformulated in terms of the variable $z_i=v_0/2$, which represents the energy stored at the output. Hence, the output voltage dynamic can be expressed as

$$C_0{\displaystyle \frac{d{z}_i}{dt}}=e_{i\mathbf{c}}{i}_{Li}-{\displaystyle \frac{2z_i}{R_0}}.$$

(28)

In summary, based on the preceding analysis, the average models describing the dynamics of the SISUC-PFC system for the two considered input filter configurations are presented as follows.

For the SISUC-PFC operating with an L filter, the average model is given by

$$\begin{array}{ccc}\hfill (L_{11}+L_i){\displaystyle \frac{d{i}_{L11}}{dt}}& =& -{\displaystyle \frac{e_{i1}}{2}}+v_S-{\delta }_1,\hfill \end{array}$$

(29)

$$\begin{array}{ccc}\hfill C_{12}{\displaystyle \frac{d{z}_1}{dt}}& =& e_{i1}{i}_{L11}-{\displaystyle \frac{2z_1}{R_0}}.\hfill \end{array}$$

(30)

Similarly, for the SISUC-PFC configuration employing an $LCL$ filter, the corresponding average model is expressed as

$$\begin{array}{ccc}\hfill L_{21}{\displaystyle \frac{d{i}_{L21}}{dt}}& =& -v_{C21}+v_S,\hfill \end{array}$$

(31)

$$\begin{array}{ccc}\hfill C_{21}{\displaystyle \frac{d{v}_{C21}}{dt}}& =& i_{L21}-i_{L22},\hfill \end{array}$$

(32)

$$\begin{array}{ccc}\hfill (L_{22}+L_i){\displaystyle \frac{d{i}_{L22}}{dt}}& =& -{\displaystyle \frac{e_{i2}}{2}}+v_{C21}-{\delta }_2,\hfill \end{array}$$

(33)

$$\begin{array}{ccc}\hfill C_{22}{\displaystyle \frac{d{z}_2}{dt}}& =& e_{i2}{i}_{L22}-{\displaystyle \frac{2z_2}{R_0}}.\hfill \end{array}$$

(34)

Notice that, as in several PFC topologies incorporating a DC–DC converter in their structure, system controllability is not guaranteed at $i_{\mathbf{c}1}=0$. In this case, this limitation remains even after applying the proposed transformation used to obtain the representations in (29) to (34). However, this new system representation allows the control to be formulated in terms of the grid parameters, which is more convenient for practical implementation.

3. Control Design Procedure

This section presents the proposed controller design procedure for the SISUC-PFC system. The control strategy is developed to fulfill two main control objectives, namely current tracking and DC-link voltage regulation. The first objective aims to force the grid current to track a sinusoidal reference proportional to the grid voltage. To ensure accurate tracking and mitigate harmonic distortion in the grid current, a proportional-resonant controller is designed, enabling operation with a near-unity power factor. The second control objective focuses on guaranteeing proper regulation of the DC output voltage. The proposed control design strategies are described in detail in the following subsections.

3.1. Control Objectives

To design the control strategies, the following control objectives are established for the operation of the SISUC-PFC.

(i)

The Power factor compensation control objective aims to enforce the grid current to follow a desired reference proportional to the grid voltage. This control objective can be formulated as

$$i_{L\mathbf{cn}}\to i_{L\mathbf{cn}}^{\ast }=g_{\mathbf{c}}{\widehat{v}}_S,$$

(35)

where $i_{L\mathbf{cn}}^{\ast }$ denotes the reference current. The subindex $\mathbf{cn}$ is used to distinguish among the different input filters of the converter and their corresponding elements. For instance, $i_{L11}$ refers to the current flowing through inductor one of the SISUC-PFC converter with an L filter. On the other hand, $g_{\mathbf{c}}$ represents the estimated apparent conductance as seen from the grid side, and is defined as

$$g_{\mathbf{c}}={\displaystyle \frac{p_{\mathbf{c}}}{v_{S,RMS}^2}},$$

(36)

where $v_{S,\mathrm{RMS}}$ denotes the RMS value of the grid voltage. The term $p_c$ is defined as the control input generated by the voltage regulation loop, which is described in a subsequent section. The fundamental component of the grid voltage is denoted by ${\widehat{v}}_S$. To extract this component, a filtering stage is employed, whose transfer function is given by

$${\displaystyle \frac{{\widehat{v}}_S}{v_S}}={\displaystyle \frac{{\lambda }_{G}s}{s^2+{\lambda }_{G}s+{\omega }_0^2}},$$

(37)

where ${\lambda }_G$ is a constant parameter used to adjust the convergence rate of ${\widehat{v}}_S$, and ${\omega }_0=2\pi f_0$ denotes the angular frequency of the fundamental component in rad/s. It is worth noting that the fundamental component extraction mechanism also functions as a phase-locked loop (PLL), ensuring that the current reference remains in phase with the fundamental component of the grid voltage while remaining free of harmonic distortion.

(ii)

Average regulation of the DC-link voltage toward a constant reference $v_{ref\mathbf{c}}$, i.e., ${\langle v_{C0}\rangle }_0\to v_{ref\mathbf{c}}$. This control objective ensures the regulation of the average voltage across the capacitor $C_0$ to the desired constant value, where ${\langle v_{C0}\rangle }_0$ denotes the average output voltage of the SISUC-PFC system. Note that this objective is equivalent to enforcing ${\langle {\tilde{z}}_{\mathbf{c}}\rangle }_0\to 0$.

3.2. Control Design Assumptions

Moreover, the following assumptions are taken into account to perform the controller design.

A1 

The voltage dynamics of the output capacitor $v_0$ are significantly slower than the remaining system dynamics, which enables the application of the time-scale separation principle. As a result, the control design can be decomposed into two independent loops: a fast inner loop dedicated to power factor correction and a slower outer loop responsible for output voltage regulation.

A2 

All PFC system parameters, namely $L_i$, $L_{\mathbf{c}1}$, $L_{\mathbf{c}2}$, $C_{11}$, and $R_0$, are assumed to be known or to vary slowly with respect to time. In addition, possible step changes in the load are considered within the normal operating conditions of the system.

A3 

The fundamental grid frequency, denoted by $f_0$, is assumed to remain constant during the converter operation.

3.2.1. Inner Loop Design for the SISUC-PFC with L Filter

This subsection presents the design procedure of the proposed control strategy for the topology shown in Figure 2, considering the use of a coupling L-filter. The current control loop is designed in accordance with the current tracking objective presented in (i). For the controller design, the system is represented in a state-space form by introducing the state variable $x_{11}\triangleq i_{L11}$. Thus, the averaged model described in (29) and (30) can be rewritten as follows,

$$\begin{array}{ccc}\hfill L_{x1}{\dot{x}}_{11}& =& -{\displaystyle \frac{e_{i1}}{2}}+v_S-{\varphi }_{R1},\hfill \end{array}$$

(38)

$$\begin{array}{ccc}\hfill C_{12}{\dot{z}}_1& =& e_{i1}{x}_{11}-{\displaystyle \frac{2z_1}{R_0}},\hfill \end{array}$$

(39)

where $L_{x1}$ denotes the equivalent inductance, defined as $L_{x1}=L_{11}+L_i$. The inner-loop control design is carried out under the decoupling assumption stated in A1; therefore, only the dynamics described in (38) are considered. The current tracking error is defined as ${\tilde{x}}_{11}\triangleq x_{11}-x_{11}^{\ast }$. By direct substitution into (38), the resulting error dynamics are given by

$$L_{x1}{\dot{\tilde{x}}}_{11}=-{\displaystyle \frac{e_{i1}}{2}}+v_S-{\varphi }_{R1},$$

(40)

where

$${\varphi }_{R1}\triangleq {\delta }_1+L_{i1}{\dot{x}}_{11}.$$

(41)

It is worth noting that the term ${\varphi }_{R1}$ represents a harmonic disturbance composed of multiple harmonics of the fundamental frequency ${\omega }_0$. To ensure accurate current tracking in the presence of this disturbance, a controller based on (40) is proposed and defined as follows,

$$e_{i1}=2(k_{pi1}{\tilde{x}}_{11}+v_S-{\widehat{\varphi }}_{R1}).$$

(42)

Here, ${\widehat{\varphi }}_{R1}$ is introduced as an estimate of the disturbance term ${\varphi }_{R1}$, while the gain $k_{pi1}$ denotes the proportional gain of the proposed controller. This gain is selected as a positive design parameter, i.e., $k_{pi1}>0$, in order to provide damping to the current dynamics. As can be observed, the controller is composed of a proportional action $k_{pi1}$ combined with the harmonic disturbance estimator ${\widehat{\varphi }}_{R1}$. In addition, a feedforward term based on the grid voltage $v_S$ is incorporated to mitigate grid-side disturbances. Consequently, the harmonic estimator ${\widehat{\varphi }}_{R1}$ is implemented as a bank of resonant filters driven by the current tracking error, yielding

$$\begin{array}{ccc}\hfill {\widehat{\varphi }}_{R1}& =& -G_{\varphi ,h1}\left(s\right){\tilde{x}}_{11},\hfill \end{array}$$

(43)

$$\begin{array}{ccc}\hfill G_{\varphi ,h1}\left(s\right)& =& \sum _{n_1\in \{1,3,5,\dots \}}{\displaystyle \frac{{\gamma }_{n_1}s}{s^2+n_1^2{\omega }^2}},\hfill \end{array}$$

(44)

where ${\gamma }_{n_1}$ is a positive design parameter.

3.2.2. Inner Loop Design for the SISUC-PFC with LCL Filter

One of the main challenges of the SISUC DC–DC converters is the presence of high input current ripple. Consequently, a first-order input filter may be insufficient, especially when the converter is connected to a weak grid. The interaction between the input current ripple and the source impedance may lead to undesirable grid-voltage effects, such as distortion. To mitigate these issues, an additional third-order filter, referred to as an $LCL$ filter, is incorporated. This filter provides enhanced attenuation of switching-frequency ripple while enabling a reduction in the required input filter size. Thus, in this subsection, the control scheme for the topology shown in Figure 2 employing an $LCL$ filter is presented. For the design of the current tracking loop, the system states are defined as $i_{L21}\triangleq x_{21}$, $v_{C21}\triangleq x_{22}$, and $i_{L22}\triangleq x_{23}$. Using these definitions, the system dynamics given in (31)–(33) are rewritten in state-variable form, yielding

$$\begin{array}{ccc}\hfill L_{21}{\dot{x}}_{21}& =& -x_{22}+v_S,\hfill \end{array}$$

(45)

$$\begin{array}{ccc}\hfill C_{21}{\dot{x}}_{22}& =& x_{21}-x_{23},\hfill \end{array}$$

(46)

$$\begin{array}{ccc}\hfill L_{x2}{\dot{x}}_{23}& =& -{\displaystyle \frac{e_{2i}}{2}}+x_{22}-{\delta }_2,\hfill \end{array}$$

(47)

where $L_{x2}$ represents the equivalent inductance defined as $L_{x2}=L_{22}+L_i$ and $e_{i2}$ is the control input applied to the system. The reference trajectories of the system are represented as $x_{21}^{\ast }$, $x_{22}^{\ast }$, $x_{23}^{\ast }$. From (45)–(47), and considering the control objectives, the references are calculated as

$$\begin{array}{ccc}\hfill x_{21}^{\ast }& =& g_2{\widehat{v}}_S={\displaystyle \frac{p_2}{v_{S,\mathrm{RMS}}}}{\widehat{v}}_S,\hfill \end{array}$$

(48)

$$\begin{array}{ccc}\hfill x_{22}^{\ast }& =& v_S-L_{21}{\dot{x}}_{21}^{\ast },\hfill \end{array}$$

(49)

$$\begin{array}{ccc}\hfill x_{23}^{\ast }& =& x_{21}^{\ast }-C_{21}{\dot{v}}_s+C_{21}{L}_{21}{\ddot{x}}_{21}^{\ast }.\hfill \end{array}$$

(50)

Note that $x_{21}^{\ast }$ is defined such that the input current $i_{L21}$ follows the fundamental component of the mains voltage, ensuring a power factor close to unity. In this case, $g_2$ denotes the conductance at the mains side. To compute $x_{23}^{\ast }$, the first derivative of the fundamental component of the input voltage ${\dot{\widehat{v}}}_S$, is required. This derivative is obtained through the filter proposed in (37), which is expressed as ${\dot{\widehat{v}}}_S=-{\displaystyle \frac{{\omega }_0^2}{s}}{\widehat{v}}_s$. As in the previous section, the inner-loop design is developed under the decoupling assumption stated in A1, where the output capacitor dynamics are considered slower than the remaining system dynamics. Therefore, the errors of the fast states are defined as follows

$$\begin{array}{ccc}\hfill {\tilde{x}}_{21}& \triangleq & x_{21}-x_{21}^{\ast },\hfill \end{array}$$

(51)

$$\begin{array}{ccc}\hfill {\tilde{x}}_{22}& \triangleq & x_{22}-x_{22}^{\ast },\hfill \end{array}$$

(52)

$$\begin{array}{ccc}\hfill {\tilde{x}}_{23}& \triangleq & x_{23}-x_{23}^{\ast }.\hfill \end{array}$$

(53)

Thus, substituting (51)–(53) in (45)–(47), the model error is given as

$$\begin{array}{cc}\hfill L_{21}{\dot{\tilde{x}}}_{21}& =-{\tilde{x}}_{22},\hfill \end{array}$$

(54)

$$\begin{array}{cc}\hfill C_{21}{\dot{\tilde{x}}}_{22}& ={\tilde{x}}_{21}-{\tilde{x}}_{23},\hfill \end{array}$$

(55)

$$\begin{array}{cc}\hfill L_{x2}{\dot{\tilde{x}}}_{23}& =-{\displaystyle \frac{e_{i2}}{2}}+{\tilde{x}}_{22}+v_S-{\delta }_2\hfill \\ \hfill & -(L_{21}+L_{x2}){\dot{x}}_{21}^{\ast }+C_{21}{L}_{x2}{\omega }_0^2{v}_S-C_{21}{L}_{21}{L}_{x2}{\stackrel{⃛}{x}}_{21}^{\ast }.\hfill \end{array}$$

(56)

Note that (56) contains terms that can be grouped as harmonic disturbances. Therefore, the system can be rewritten as

$$L_{x2}{\dot{\tilde{x}}}_{23}=-{\displaystyle \frac{e_{i2}}{2}}+v_S-{\varphi }_{R2},$$

(57)

where ${\varphi }_{R2}$ represents the grouped harmonic disturbances, expressed as

$${\varphi }_{R2}=-{\delta }_2-(L_{21}+L_{x2}){\dot{x}}_{21}^{\ast }+C_{21}{L}_{x2}{\omega }_0^2{v}_S-C_{21}{L}_{21}{L}_{x2}{\stackrel{⃛}{x}}_{21}^{\ast }+{\tilde{x}}_{22}.$$

(58)

To ensure reaching the current tracking objective, a control law based on the subsystem in (57) is proposed as

$$e_{i2}=2(k_{p,i2}{\tilde{x}}_{23}+v_S-{\widehat{\varphi }}_{R2}),$$

(59)

here, the term ${\varphi }_{R2}$ captures odd harmonics of the grid frequency, and ${\widehat{\varphi }}_{R2}$ is its estimation. The gain $k_{p,i2}$ is a positive proportional term that introduces damping into the system and ensures error convergence. Thus, the controller structure in (59) includes a proportional feedback term $k_{p,i2}{\tilde{x}}_{23}$, a feedforward of the grid voltage $v_S$, and a harmonic compensator ${\widehat{\varphi }}_{R2}$ to cancel grid disturbances. The harmonic compensator yields a structure of a bank of resonant filters applied to the current error, as follows:

$${\widehat{\varphi }}_{R2}=-G_{\varphi h2}\left(s\right){\tilde{x}}_{23},$$

(60)

$$G_{\varphi h2}\left(s\right)=\sum _{n_2\in \{1,3,5,\dots \}}{\displaystyle \frac{{\gamma }_{n_2}s}{s^2+n_2^2{\omega }_0^2}}.$$

(61)

This structure effectively targets and attenuates odd harmonics of the grid frequency ${\omega }_0$. Furthermore, to establish the relationship between the current reference and the system states, an explicit expression for $x_{23}^{\ast }$ is derived from the dynamic model as follows,

$$x_{23}^{\ast }=(1-C_{21}{L}_{21}{\omega }_0^2)x_{21}^{\ast }-2C_{21}{\dot{\widehat{v}}}_S.$$

(62)

This expression accounts for the effect of the output capacitor and enables the tracking of the grid current by sensing the output current of the converter $x_{23}$. This permits the implementation of the current control loop using two signals only, the current $x_{23}$, and the grid voltage $v_S$. The latter contrasts with some approaches that require more than one state of the system, including $v_S$. Nevertheless, as expected, for the voltage control loop, the output capacitor voltage $v_{C22}$ is additionally required to implement the overall control law.

3.2.3. Voltage Regulation Loop

This subsection presents the design of the voltage regulation loop for the system depicted in Figure 2, including an $LCL$ filter. The control objective is to ensure accurate output voltage tracking. The controller is derived under assumption A1, assuming that the current error satisfies ${\tilde{x}}_{23}\to 0$. Under this condition, the dynamics in (2) are reformulated in terms of the energy error defined as ${\tilde{z}}_2\stackrel{\Delta }{=}{z}_2-v_{ref2}^2/2$. Hence, the system dynamics can be expressed as

$$C{\dot{\tilde{z}}}_2=2(1-C_{21}{L}_{21}{\omega }_0^2)p_2-2C_{21}{\dot{\widehat{v}}}_S{\widehat{v}}_S-P_{02}-{\displaystyle \frac{2{\tilde{z}}_2}{R_{C2}}}.$$

(63)

Considering that $1\gg C_{21}{L}_{21}{\omega }_0^2$, the previous expression can be approximated as

$$C_{22}{\dot{\tilde{z}}}_2=2p_2-P_{02}-{\displaystyle \frac{2{\tilde{z}}_2}{R_{c2}}}.$$

(64)

Observed that (64) corresponds to a first-order system with $p_2$ as control input. The objective is to enforce ${\tilde{z}}_2\to 0$, guaranteeing that the average output voltage converges to the reference $v_{\mathrm{ref}2}$. To achieve voltage regulation, a PI controller is formulated in terms of ${\tilde{z}}_2$, and is defined as

$$\begin{array}{ccc}\hfill p_2& =& -{\displaystyle \frac{1}{2}}(k_{i,v2}{\xi }_2+k_{p,v2}{\upsilon }_2),\hfill \end{array}$$

(65)

$$\begin{array}{ccc}\hfill {\dot{\xi }}_2& =& {\tilde{z}}_2,\hfill \end{array}$$

(66)

$$\begin{array}{ccc}\hfill 2{\tau }_{v2}{\dot{\upsilon }}_2& =& {\tilde{z}}_2-{\upsilon }_2,\hfill \end{array}$$

(67)

where ${\xi }_2$ is the integral state introduced to remove steady-state error, $k_{i,v2}$ and $k_{p,v2}$ denote the integral and proportional gains, respectively, and ${\tau }_{v2}$ represents the time constant of the low-pass filter. This filter is implemented to attenuate the harmonic components injected into the voltage loop by the rectification stage. The transfer function of the controller is

$$G_{c,v2}\left(s\right)=-{\displaystyle \frac{1}{2}}\left[{\displaystyle \frac{k_{i,v2}}{s}}+{\displaystyle \frac{k_{p,v2}}{{\tau }_{v2}s+1}}\right].$$

(68)

This controller enforces ${\tilde{z}}_2\to 0$, ensuring DC voltage regulation at the reference value.

3.2.4. Overall Structure of the Proposed Control Strategies

This section presents the control strategies developed for the SISUC-PFC system employing both L and $LCL$ coupling filters to the grid. For the case of an L filter, the control architecture consists of an inner current control loop and an outer voltage control loop. The resulting control law is summarized in (69)–(74) and illustrated in Figure 3.

$$\begin{array}{cc}\hfill & e_{i1}=2(k_{p,i1}{\tilde{x}}_{11}+v_S-{\widehat{\varphi }}_{h1}),\hfill \end{array}$$

(69)

$$\begin{array}{cc}\hfill & {\widehat{\varphi }}_{R1}=-G_{\varphi ,h1}\left(s\right){\tilde{x}}_{11},\hfill \end{array}$$

(70)

$$\begin{array}{cc}\hfill & G_{\varphi ,h1}\left(s\right)=\sum _{n_1\in \{1,3,5,\dots \}}{\displaystyle \frac{{\gamma }_{n_1}s}{s^2+n_1^2{\omega }^2}},\hfill \end{array}$$

(71)

$$\begin{array}{cc}\hfill & G_{c,v1}\left(s\right)=-\left[{\displaystyle \frac{k_{i,v1}}{s}}+{\displaystyle \frac{k_{p,v1}}{{\tau }_{v1}s+1}}\right],\hfill \end{array}$$

(72)

$$\begin{array}{cc}\hfill & u_1={\displaystyle \frac{e_{i1}}{v_{C12}}}{\displaystyle \frac{i_{L11}}{|i_{L11}|}},\hfill \end{array}$$

(73)

$$\begin{array}{cc}\hfill & d_1=1-u_1.\hfill \end{array}$$

(74)

For the SISUC-PFC system employing an $LCL$ grid filter, the overall control structure similarly incorporates current and voltage control loops. The corresponding control expressions are (75)–(80) and depicted in Figure 4.

$$\begin{array}{cc}\hfill & e_{i2}=2(k_{p,i2}{\tilde{x}}_{23}+v_S-{\widehat{\varphi }}_{h2}),\hfill \end{array}$$

(75)

$$\begin{array}{cc}\hfill & {\widehat{\varphi }}_{R2}=-G_{\varphi ,h2}\left(s\right){\tilde{x}}_{23},\hfill \end{array}$$

(76)

$$\begin{array}{cc}\hfill & G_{\varphi ,h2}\left(s\right)=\sum _{n_2\in \{1,3,5,\dots \}}{\displaystyle \frac{{\gamma }_{n_2}s}{s^2+n_2^2{\omega }^2}},\hfill \end{array}$$

(77)

$$\begin{array}{cc}\hfill & G_{c,v2}\left(s\right)=-{\displaystyle \frac{1}{2}}\left[{\displaystyle \frac{k_{i,v2}}{s}}+{\displaystyle \frac{k_{p,v2}}{{\tau }_{v2}s+1}}\right],\hfill \end{array}$$

(78)

$$\begin{array}{cc}\hfill & u_2={\displaystyle \frac{e_{i2}}{v_{C22}}}{\displaystyle \frac{i_{L22}}{|i_{L22}|}},\hfill \end{array}$$

(79)

$$\begin{array}{cc}\hfill & d_2=1-u_2.\hfill \end{array}$$

(80)

4. Experimental and Numerical Results

In this section, the numerical and experimental validation results of the proposed controllers are presented in order to verify their performance under representative operating conditions. First, the results obtained through simulations are shown, allowing the dynamic response of the system, the stability of the control loop, and the steady-state behavior under parameter variations and disturbances to be analyzed. Subsequently, the experimental results obtained from an implemented prototype are presented, through which the practical feasibility of the control strategy is corroborated.

4.1. Numerical Results

Figure 5 shows the numerical validation of the two systems together with the proposed controllers. For this validation, the parameters listed in

Table 1. Experimental and Numerical parameters of SISUC PFC.

Parameters of the SISUC-PFC	L Filter	LCL Filter
Grid Voltage ($v_S$)	24$V_{\mathrm{RMS}}$	24$V_{\mathrm{RMS}}$
Reference Voltage ($V_{ref\mathbf{c}}$)	75 V	75 V
Switching Frequency ($f_{sw}$)	10 kHz	10 kHz
Inductor ($L_{\mathbf{c}1}$, $L_{\mathbf{c}2}$, $L_i$)	1 mH, –, 2 mH	1 mH, 2 mH, 2 mH
Capacitor ($C_{11}$)	–	10 $\mathsf{\mu }$F
Output Capacitor ($C_0$)	680 $\mathsf{\mu }$F	680 $\mathsf{\mu }$F
Control Loop	Value	Value
Rectifier-side current tracking	$K_{p,i1}=20$	$K_{p,i2}=16$
Voltage proportional gain	$K_{p,v1}=1.3$	$K_{p,v2}=1.7$
Voltage integral gain	$K_{i,v1}=0.3$	$K_{i,v2}=0.4$

Note: “–” indicates that the entry is not applicable.

are considered. In Figure 5a, the steady-state response of the SISUC-PFC converter with an L filter is presented. A noticeable level of noise is observed in the input voltage. This behavior is attributed to the fact that the simulation environment is configured to replicate the conditions of the experimental setup to be implemented. In particular, the grid is replaced by a 24 $V_{RMS}$ transformer used as the power supply for the proposed systems. Due to the relatively high output impedance of the employed source, unlike a stiff grid, the voltage at the point of common coupling (PCC) becomes highly sensitive to switching dynamics. As a result, current ripple is directly reflected as noticeable voltage distortions, leading to the observed noise in the input voltage. However, even under these non-ideal conditions, the proposed control law demonstrates adequate performance. It can be observed that the input current $i_{L11}$ presents a sinusoidal waveform and remains in phase with the input voltage, achieving a power factor close to unity. In addition, the output voltage is regulated at the reference value of $75V$. Therefore, both control objectives are properly achieved. On the other hand, Figure 5b shows the steady-state response of the SISUC PFC system with an $LCL$ filter. As can be observed, an improved performance is achieved compared to the L-type filter, since a lower input current ripple and a reduced THD are obtained. In addition, both control objectives, current tracking and output voltage regulation, are properly ensured. It should be noted that the $LCL$ filter is designed considering a resonance frequency higher than the grid frequency and significantly lower than the switching frequency, thus avoiding the excitation of resonant modes under normal operating conditions.

Figure 6 and Figure 7 illustrate the transient response of the proposed systems under load variations from 150 $\mathsf{\Omega }$ to 75 $\mathsf{\Omega }$ and from 75 $\mathsf{\Omega }$ to 150 $\mathsf{\Omega }$, respectively. In both scenarios, it can be observed that the output voltage remains regulated despite the changes in load conditions, indicating that the control objectives for which the controllers were designed are effectively achieved.

As an additional test, a nonlinear load is connected to the proposed system, particularly to the SISUC-PFC converter with an $LCL$ filter, as shown in Figure 8. The implemented load consists of a high-frequency H-bridge followed by a 1:1 high-frequency transformer, a full-wave rectifier, and an output LC filter. The obtained results are presented in Figure 9. As can be observed, the proposed system continues to satisfy the control objectives even under nonlinear loading conditions, exhibiting an adequate performance. In particular, the input current preserves a sinusoidal waveform with low THD and a power factor close to unity, while the output voltage remains properly regulated, even under transient changes, as shown in Figure 10.

4.2. Experimental Results

Now this subsection presents the experimental validation of the SISUC-PFC. The experimental validation is carried out using a low-power academic prototype developed as a proof of concept. The main objective of this implementation is to verify the proposed control strategy and the modeling approach of the DC–DC topology with power factor correction capability. The controller is implemented on a dSPACE 1104 DAQ board, while the switching signals are transmitted via fiber optics to guarantee electrical isolation and reduce electromagnetic interference. Current and voltage measurements are obtained through a dedicated sensing board using CLN-50 and LV-25P sensors. All signals are monitored and recorded using ControlDesk software. The block diagram of the implemented closed-loop system is shown in Figure 11. As can be observed, the system is mainly composed of the power stage and the control stage. For the experimental validation, the system parameters and the controller gain values summarized in Table 1 are considered. The performance of the converter and the controllers is evaluated under two operating scenarios: steady-state and transient conditions. It is important to highlight that the gains of both control loops are selected using a heuristic procedure based on numerical results. First, the proportional gains are set to low values and then gradually increased until the current and voltage responses approach their reference values. Subsequently, the integral gains are progressively increased to eliminate the steady-state error.

Figure 12 shows the steady-state grid voltage and line current of the SISUC-PFC using L and $LCL$ input filters. Figure 12a corresponds to the L-filter case. The line current is sinusoidal and in phase with the grid voltage, resulting in a power factor close to 0.9. Some distortion in the grid voltage $v_S$ is observed, which is attributed to the transformer impedance. However, this distortion is not reflected in the line current, since no distortion is observed in its waveform. Furthermore, Figure 12b shows the steady-state response of the grid voltage and line current of the SISUC-PFC converter with an $LCL$ filter. As observed, the grid voltage and current are in phase, yielding a power factor of 0.99. In particular, the use of the $LCL$ filter provides improved performance in terms of grid current THD, current ripple levels $\Delta i_{21}$, and power factor compared to the L-filter case. As shown in Figure 12b, the grid current $i_{L21}$ exhibits a reduced switching ripple, which lowers the harmonic content and directly contributes to the improvement of the THD. Consequently, the $LCL$ filter enhances the grid current quality and the overall performance of the PFC converter.

Figure 13 presents, from top to bottom, the input voltage $v_S$, input current $i_{Li\mathbf{c}}$, output voltage $v_0$, and inductor current $i_{Li\mathbf{c}}$ of the SISUC-PFC with L and $LCL$ filters. In particular, Figure 13a illustrates the steady-state response of the SISUC-PFC when an L filter is employed. As observed, the grid voltage and grid current are in phase, demonstrating appropriate power factor correction performance. Under these conditions, the input current exhibits a THD of 0.759%, which is obtained through the fast Fourier transform (FFT) of the current signals acquired using the Tektronix MSO 3034 (Tektronix, Inc., Beaverton, OR, USA) oscilloscope and the current probes TCP202A. This approach provides a more accurate estimation under the experimental conditions, particularly considering the low current levels involved. Additionally, note that the output voltage is observed to converge to the reference value, which confirms that the proposed controller satisfactorily fulfills the output voltage regulation objective. On the other hand, the inductor current $i_{Li}$ exhibits a full-wave rectified waveform as a direct consequence of the AC-DC rectification process. As a result, the output voltage of the DC–DC stage contains a low-frequency ripple at 120 Hz.

In Figure 13b, the steady-state response of the SISUC-PFC using an $LCL$ filter is presented. As observed, the grid voltage and grid current are in phase. In this case, the grid current exhibits a THD of 0.203%, which is lower than that obtained when an L filter is employed. Similarly, the inductor current $i_{Li}$ exhibits a full-wave rectified waveform. It is worth noting that the use of an $LCL$ filter at the rectifier input provides significant advantages compared to an L filter, since it offers higher attenuation of switching harmonics, resulting in a reduction in both the harmonic content and the ripple of the grid current. Furthermore, the higher attenuation provided by the $LCL$ filter contributes to a reduction in the output voltage ripple, particularly the ripple associated with the rectification process. As a consequence, the value of the output capacitance can be reduced while maintaining the same voltage ripple level compared to the use of an L filter.

The transient responses of the grid voltage and grid current, as well as the output voltage and output current, are presented in Figure 14 and Figure 15 for different load conditions of the SISUC-PFC employing L and $LCL$ input filters. In particular, Figure 14a–c illustrates the transient behavior associated with a load variation from 150 $\mathsf{\Omega }$ to 75 $\mathsf{\Omega }$ and back. The results show that the output voltage remains well regulated under load variations, confirming the effectiveness of the proposed controller. Moreover, the amplitudes of both the grid current and the output current are observed to increase proportionally with the load variation, as expected. Specifically, as shown in Figure 14c, the grid current preserves a sinusoidal waveform in phase with the grid voltage, demonstrating that power factor correction is maintained even under load variations.

Figure 15 illustrates, from top to bottom, the transient responses of the grid voltage, grid current, output voltage, and output current of the SISUC-PFC with an $LCL$ filter under load variations. The reference voltage is set to 75 V, while the load is changed from 150 $\mathsf{\Omega }$ to 75 $\mathsf{\Omega }$ and back. As shown in Figure 15a,c, output voltage regulation is achieved despite the load changes, although a voltage overshoot is observed during the load transitions. Subsequently, the output voltage converges to the reference value. Moreover, due to the use of the $LCL$ filter, reduced noise is exhibited in the voltage and current waveforms compared to those obtained when an L filter is employed. Similarly, as shown in Figure 15c, a sinusoidal grid current with low harmonic content is preserved and remains in phase with the grid voltage, demonstrating that power factor correction is maintained even under load variations.

The experimental results show a behavior very similar to that obtained through numerical simulations. As can be observed, the output voltage and input current exhibit comparable dynamic responses and steady-state performance. In addition, both the transient response and the waveform profiles show strong agreement, with only minor discrepancies mainly attributed to non-ideal effects in the experimental implementation. These results validate the accuracy of the proposed model and the effectiveness of the control strategy, demonstrating a close correspondence between simulation and experimental results.

4.3. Efficiency Analysis

In this subsection, the efficiency analysis of the proposed systems is presented. For this purpose, the parasitic resistances of both semiconductor and passive components are considered based on the manufacturers’ datasheets. The efficiency is evaluated following the methodology described in [37]. As shown in Figure 16, both systems exhibit similar efficiency levels; however, the configuration with the L filter achieves a slightly higher efficiency compared to the $LCL$ filter. In particular, a maximum efficiency of 92.8% is obtained at 250 W for the L filter, whereas the $LCL$ filter reaches approximately 91.9%.

In

Table 2. Comparison of the main performance metrics of the proposed SISUC-PFC converter using L and $LCL$ filters.

Metrics	SISUC-PFC with L Filter	SISUC-PFC with LCL Filter
Power Factor ($PF$)	0.9	0.99
$THD{i}_{\mathbf{c}n}$	0.759%	0.203%
Efficiency ($\eta$)	92.8%	91.9%
Current ripple ($\Delta i_{11},\Delta i_{21}$)	High	Low

, the main performance metrics of the proposed systems are summarized. As can be observed, the SISUC-PFC system with an $LCL$ filter exhibits improved power quality, achieving a higher PF and lower total THD compared to the L filter configuration. However, the system with an L filter attains a slightly higher efficiency. In addition, the L-filter-based system presents a higher current ripple level compared to the LCL configuration. Despite this, the LCL-based configuration is considered a more suitable option due to its superior PF and THD performance, as well as its reduced current ripple. It is worth mentioning that, although the efficiency of both systems is below 95%, it can be improved through an appropriate selection of the components.

5. Conclusions

This paper presents a high-gain AC–DC converter based on the switched-inductor technique, capable of achieving a high conversion ratio for power factor correction applications. The system consists of an AC–DC stage with an uncontrolled full-wave rectifier and a passive input filter, followed by a DC–DC stage that provides the high conversion ratio. Both L and $LCL$ filters are considered to improve input current quality. The main contribution of this work is the development of the system model and the design of the control strategy. In particular, a model-based approach is used to derive the control design from the averaged system model, resulting in a structured control scheme that includes an inner current loop based on a proportional-resonant controller and an outer voltage loop based on a PI controller with a low-pass filter.

The proposed system and control scheme were validated using a laboratory prototype. The experimental results demonstrate adequate input current tracking and stable output voltage under load variations within the tested operating conditions. The system with an $LCL$ input filter achieves improved current quality, with a power factor close to unity, reduced current ripple, and lower harmonic distortion compared to the L filter case, as well as lower output voltage ripple. Although the LCL configuration requires more passive components, the inductance and capacitance values are smaller, resulting in reduced overall size and cost. Both configurations use the same sensing scheme, indicating that the improved performance is achieved without increasing implementation complexity.

It is important to highlight that the experimental validation presented in this work is based on a low-power academic prototype designed as a proof of concept. Although the operating conditions differ significantly from those of practical Level 1/Level 2 on-board EV chargers, which represent one of the potential applications of this system, the obtained results can be extrapolated to higher-power applications, since the proposed modeling approach and control law exhibit consistent performance and are not inherently dependent on the power level. Therefore, with an appropriate selection of passive components, semiconductor devices, and proper thermal management, similar dynamic behavior and control performance can be expected at higher power levels, with the potential for further improvements in PF and THD. In future work, the performance of the proposed system will be validated under higher output power conditions through appropriate component selection and an improved experimental prototype design. Additionally, future research will address the control design, analysis, and experimental validation of isolated high-gain converter topologies, such as Flyback-derived systems, to further evaluate their suitability for this type of application.