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Open AccessArticle

Robust Offset-Cancellation Sense Amplifier for an Offset-Canceling Dual-Stage Sensing Circuit in Resistive Nonvolatile Memories

Department of Electronics Engineering, Incheon National University, Incheon 22012, Korea
Electronics 2020, 9(9), 1403; https://doi.org/10.3390/electronics9091403
Received: 14 August 2020 / Revised: 26 August 2020 / Accepted: 28 August 2020 / Published: 30 August 2020
With technology scaling, achieving a target read yield of resistive nonvolatile memories becomes more difficult due to increased process variation and decreased supply voltage. Recently, an offset-canceling dual-stage sensing circuit (OCDS-SC) has been proposed to improve the read yield by canceling the offset voltage and utilizing a double-sensing-margin structure. In this paper, an offset-canceling zero-sensing-dead-zone sense amplifier (OCZS-SA) combined with the OCDS-SC is proposed to significantly improve the read yield. The OCZS-SA has two major advantages, namely, offset voltage cancellation and a zero sensing dead zone. The Monte Carlo HSPICE simulation results using a 65-nm predictive technology model show that the OCZS-SA achieves 2.1 times smaller offset voltage with a zero sensing dead zone than the conventional latch-type SAs at the cost of an increased area overhead of 1.0% for a subarray size of 128 × 16. View Full-Text
Keywords: nonvolatile memory (NVM); offset voltage; offset-canceling dual-stage sensing circuit (OCDS-SC); read yield; sense amplifier (SA); sensing dead zone; time-difference inputs nonvolatile memory (NVM); offset voltage; offset-canceling dual-stage sensing circuit (OCDS-SC); read yield; sense amplifier (SA); sensing dead zone; time-difference inputs
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Na, T. Robust Offset-Cancellation Sense Amplifier for an Offset-Canceling Dual-Stage Sensing Circuit in Resistive Nonvolatile Memories. Electronics 2020, 9, 1403.

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