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Visconti P, Capoccia S, Venere E, Velázquez R, Fazio Rd. 10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform. Electronics. 2020; 9(10):1665. https://doi.org/10.3390/electronics9101665

Visconti, Paolo, Stefano Capoccia, Eugenio Venere, Ramiro Velázquez, and Roberto de Fazio. 2020. "10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform" Electronics 9, no. 10: 1665. https://doi.org/10.3390/electronics9101665

Visconti, P., Capoccia, S., Venere, E., Velázquez, R., & Fazio, R. d. (2020). 10 Clock-Periods Pipelined Implementation of AES-128 Encryption-Decryption Algorithm up to 28 Gbit/s Real Throughput by Xilinx Zynq UltraScale+ MPSoC ZCU102 Platform. Electronics, 9(10), 1665. https://doi.org/10.3390/electronics9101665