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Area-Efficient Embedded Resistor-Triggered SCR with High ESD Robustness

State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China
Author to whom correspondence should be addressed.
Electronics 2019, 8(4), 445;
Received: 21 March 2019 / Revised: 13 April 2019 / Accepted: 17 April 2019 / Published: 18 April 2019
(This article belongs to the Section Microelectronics and Optoelectronics)
PDF [3772 KB, uploaded 25 April 2019]


The trigger voltage of the direct-connected silicon-controlled rectifier (DCSCR) was effectively reduced for electrostatic discharge (ESD) protection. However, a deep NWELL (DNW) is required to isolate PWELL from P-type substrate (PSUB) in DCSCR, which wastes part of the layout area. An area-efficient embedded resistor-triggered silicon-controlled rectifier (ERTSCR) is proposed in this paper. As verified in a 0.3-μm CMOS process, the proposed ERTSCR exhibits lower triggering voltage due to series diode chains and embedded deep n-well resistor in the trigger path. Additionally, the proposed ERTSCR has a failure current of more than 5 A and a corresponding HBM ESD robustness of more than 8 KV. Furthermore, compared with the traditional DCSCR, to sustain the same ESD protection capability, the proposed ERTSCR will consume 10% less silicon area by fully utilizing the lateral dimension in the deep n-well extension region, while the proposed ERTSCR has a larger top metal width. View Full-Text
Keywords: electrostatic discharge (ESD); silicon-controlled rectifier (SCR); deep n-well resistor; trigger voltage electrostatic discharge (ESD); silicon-controlled rectifier (SCR); deep n-well resistor; trigger voltage

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Hou, F.; Du, F.; Yang, K.; Liu, J.; Liu, Z. Area-Efficient Embedded Resistor-Triggered SCR with High ESD Robustness. Electronics 2019, 8, 445.

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