Analysis of a DC Converter with Low Primary Current Loss and Balance Voltage and Current

Abstract

A dc/dc pulse width modulation (PWM) circuit was investigated to realize the functions of reduced primary current loss and balanced voltage and current distribution. In the presented dc/dc converter, two full bridge pulse width modulation circuits were used with the series/parallel connection on the high-voltage/low-voltage side. The flying capacitor was adopted on the input side to achieve voltage balance on input split capacitors. The magnetic coupling element was employed to achieve current sharing between two parallel circuits. A capacitor-diode passive circuit was adopted to lessen the primary current at the commutated interval. The phase-shifted duty cycle control approach was employed to regulate load voltage and implement soft switching characteristics of power metal-oxide-semiconductor field-effect transistors (MOSFETs). Finally, the experimental results using a 1.68 kW prototype converter were obtained to confirm the performance and feasibility of the studied circuit topology.

1. Introduction

High power density/efficiency dc/dc converters [1,2] have been proposed to reduce unnecessary power loss in order to reduce environmental pollution and met global energy demands. Clean and renewable energy sources meet these requirements to provide available ac or dc power to ac utilities, dc micro-grids, residential houses and commercial buildings by using power electronic based converters or inverters. High-voltage pulse width modulation (PWM) converters have been presented for industry power units [3,4], dc micro-grid systems [5,6,7] and dc traction or dc light rail transportation systems [8,9]. For these applications, the dc bus voltage is regulated between 750 V and 800 V. Full bridge circuits with a high switching frequency high-voltage rating SiC MOSFET or high-voltage rating insulated gate bipolar transistor (IGBT) devices can be adopted for high dc voltage applications. However, 1200 V SiC MOSFET devices are expensive and 1200 V IGBT devices have low switching frequency problems. Cost and performance are always the two main issues in the development of the available and high reliability power converters. Therefore, MOSFET power devices have been widely adopted in high efficiency power electronics. To improve the low-voltage drawback of MOSFETs in high-voltage applications, zero voltage switching, multi-level circuit topologies [10,11,12,13,14] have been developed and proposed to decrease conduction and switching losses. The phase shift pulse width modulation (PSPWM) and frequency modulation have normally been adopted to regulate duty cycle or switching frequency. However, the main disadvantage of conventional PSPWM is high circulating current losses at low effective duty cycle. In order to reduce circulating current, an active or passive snubber used on the low-voltage side has been proposed in [15,16,17]. A modular dc/dc converter [18] using low power rating modular circuits in series or parallel connection has been proposed to increase circuit efficiency and power rating. However, the current between each modular circuit may be unbalanced. To accomplish current balance issue, several current balancing approaches have been presented in [19,20].

A series/parallel-connected dc/dc converter is proposed to accomplish reduced primary circulating current, a soft switching operation, and balanced input voltages and output currents. Two full bridge circuits with series/parallel connection on input/output side are used in the studied circuit to achieve voltage and current sharing for the high voltage input and current output. Therefore, power devices on each full bridge circuit have V_in/2 voltage stress. To prevent input split voltages imbalance, a voltage balance capacitor was used on the input side to automatically achieve split voltages balance. Passive snubber circuits were employed on output side to create a positive voltage on the secondary rectified terminal under the commutated state so that the primary current at the commutated state can be reduced. To realize current sharing of two full bridge circuits, a current-balance magnetic component was adopted on the high-voltage side. If two currents are unbalanced, then one induced voltage of MC component is decreased to lessen the larger converter current. Therefore, two converter currents can be compensated automatically. PSPWM was adopted to control power devices and accomplish soft switching operation of active switches. The organization of this paper is as follows: The circuit structure and the principle of operation are discussed in Section 2. The steady state operation of the presented converter is shown in Section 3. Test results with a laboratory prototype are presented and investigated in Section 4. The conclusions of the studied converter are discussed in Section 5.

2. Circuit Structure and Principle of Operation

High-voltage converters were researched and presented for industry power supplies, dc traction vehicle and dc micro-grid systems. Ac/dc power converters with low harmonic currents, high power factor (PFC) and a stable dc voltage shown in Figure 1a are required for industry power converters. Normally, the dc voltage V_H is controlled at 760 V. Then, a high-frequency link converter is adopted to provide low-voltage output. Figure 1b illustrates the basic power distributed diagrams on dc light rail vehicle. A high-voltage dc converter can convert a 760 V input to supply a low-voltage output for battery charger, control, and communication demands. Figure 1c demonstrates the blocks of a bipolar dc micro-grid system to integrate ac utility system, clean energy generators and industry load and residential load into a common dc bus voltage.

Figure 2 gives the converter configuration of the developed circuit with series/parallel connection of full bridge circuits to achieve low circulating current loss, soft switching for power MOSFETs, and balanced input split voltages and output current sharing. The first full bridge circuit has power MOSFETs S₁-S₄ with the output capacitors C₁-C₄, leakage or external inductor L_r1, transformer T₁, magnetic core MC, filter inductor L_o1, secondary-side rectifier diodes D₁ and D₂, and passive circuit including C_a1, D_a1 and D_b1. Likewise, the second full bridge circuit includes the components S₅-S₈, C₅-C₈, L_r2, T₂, MC, L_o2, D₃, D₄, C_a2, D_a2 and D_b2. C_in,1 and C_in,2 are input split capacitors and C_b is the balance capacitor. Each circuit can transfer one-half rated power to the secondary side. The magnetic core [20] is used to balance i_Lr1 and i_Lr2. Under the balanced primary currents (|i_Lr1| = |i_Lr2|), the induced voltages V_L1 and V_L2 are zero. If i_Lr1 and i_Lr2 are unbalanced (such as |i_Lr1| > |i_Lr2|), the induced voltage V_L1 of MC cell is decreased in order to decrease i_Lr1 and V_L2 is increased to increase i_Lr2. Thus, i_Lr1 will equal i_Lr2 and V_L1 = V_L2 = 0. PSPWM is used to control S₁~S₈ and have zero voltage switching on the MOSFETs. Power switches S₁~S₄ and S₅~S₈ have identical PWM waveforms. The balance capacitor C_b is linked between points a and c. If S₁ and S₅ are on and S₂ and S₆ are off, then V_Cb = V_Cin,1. Likewise, V_Cb = V_Cin,2 if S₂ and S₆ are on and S₁ and S₅ are in the off. Since the duty cycle d_S1 = d_S2 = 0.5, it is obvious that V_Cb = V_Cin,1 = V_Cin,2 = V_in/2. Thus, the drain voltages of S₁~S₈ are V_in/2. To decrease the primary-side circulating currents, passive snubbers, C_a1, D_a1, D_b1, C_a2, D_a2, D_b2, are used on the presented circuit. At the same time, the filter inductor voltages v_Lo1 = v_Ca1 − V_o and v_Lo2 = v_Ca2 − V_o rather than −V_o in the traditional full bridge duty cycle converters.

The operation principle of the presented circuit is discussed with the assumptions: (1) C_in,1 = C_in,2; (2) C₁ =….= C₈ = C_oss; (3) C_a1 = C_a2 = C_a; (4) L_m1 = L_m2 = L_m; (5) L_o1 = L_o2 = L_o; (6) L_r1 = L_r2 = L_r; (7) V_Cb = V_Cin,1 = V_Cin,2 = V_in/2; and (8) n₁ = n₂ = n. Figure 3 shows the PWM waveforms of the studied converter. The duty cycle of S₁~S₈ is 0.5. The gating signals of S₄ (S₃) is shifted to S₁ (S₂), respectively. Due to the switching states of power devices, the converter has fourteen steps in a switching period. The PWM waveforms are symmetrical for every half cycle. Therefore, only the first seven steps are discussed and the circuits of first seven operating steps are illustrated in Figure 4.

Step 1 [t₀, t₁]: Before t₀, S₁, S₄, S₅, S₈, D₁ and D₃ conduct, i_Lr1 > 0 and i_Lr2 > 0. After t₀, power MOSFETs S₁ and S₅ turn off. C₁ and C₅ are charged and C₂ and C₆ are discharged. The energy on L_r1, L_r2, L_o1 and L_o2 can discharge C₂ and C₆. Equations (1) and (2) give the soft switching conditions of S₂ and S₆.

$$(L_{r1}+n_1^2{L}_{o1})i_{Lr1}^2(t_0)\ge C_{oss}{V}_{in}^2/2$$

(1)

$$(L_{r2}+n_2^2{L}_{o2})i_{Lr2}^2(t_0)\ge C_{oss}{V}_{in}^2/2$$

(2)

If these conditions are satisfied, then v_C1 = v_C5 = V_in/2 and v_C2 = v_C6 = 0 at t₁. The time duration in step 1 is obtained in Equation (3).

$$\Delta t_{01}=t_1-t_0=\frac{C_{oss}{V}_{in}}{i_{Lr1}(t_0)}\approx \frac{n_1{C}_{oss}{V}_{in}}{i_{Lo,peak}}\approx \frac{2n_1{C}_{oss}{V}_{in}}{I_o}$$

(3)

The time duration Δt₀₁ is related to the load current and input voltage.

Step 2 [t₁, t₂]: At t₁, v_C2 = v_C6 = 0. The positive primary currents i_Lr1 and i_Lr2 will flow through the body diode of S₂ and S₆. Thus, power MOSFETs S₂ and S₆ can achieve zero-voltage switching after t₁. The ac side voltages v_ab = v_cd = 0 and i_Lr1 and i_Lr2 decrease. Therefore, D_a1 and D_a2 conduct at this freewheeling state. The magnetizing voltages v_Lm1 and v_Lm2 are clamped at v_Ca1 and v_Ca2, respectively. The primary inductor voltages v_Lr1 = −n₁v_Ca1 and v_Lr2 = −n₂v_Ca2 and the filter inductor voltages v_Lo1 = v_Ca1 − V_o < 0 and v_Lo2 = v_Ca2 − V_o < 0. Therefore, i_Lr1, i_Lr2, i_Lo1 and i_Lo2 are all decreased in this step.

$$i_{Lr1}(t)\approx i_{Lr1}(t_1)-\frac{n_1{v}_{Ca1}}{L_{r1}}(t-t_1)$$

(4)

$$i_{Lr2}(t)\approx i_{Lr2}(t_1)-\frac{n_2{v}_{Ca2}}{L_{r2}}(t-t_1)$$

(5)

$$i_{Lo1}(t)\approx i_{Lo1}(t_1)+\frac{v_{Ca1}-V_o}{L_{o1}}(t-t_1)$$

(6)

$$i_{Lo2}(t)\approx i_{Lo2}(t_1)+\frac{v_{Ca2}-V_o}{L_{o2}}(t-t_1)$$

(7)

Thus, the circulating current is decreased under the commutated state. In this step, the balance capacitor voltage V_Cb = V_Cin,2.

Step 3 [t₂, t₃]: At time t₂, i_D1 = i_D3 = 0 and D₁ and D₃ are off. Then, i_Ca1 = −i_Lo1, i_Ca2 = −i_Lo2, i_Lr1 = i_Lm1(t₂) and i_Lr2 = i_Lm2(t₂). Since i_Lm1(t₂) and i_Lm2(t₂) are close to zero, the circulating current is removed. The filter inductor voltages v_Lo1 = v_Ca1 − V_o < 0 and v_Lo2 = v_Ca2 − V_o < 0. The secondary-side currents i_Lo1 and i_Lo2 are lessened.

Step 4 [t₃, t₄]: At t₃, power MOSFETs S₄ and S₈ turn off. C₃ and C₇ are discharged and C₄ and C₈ are charged. The energy on L_r1 and L_r2 can discharge C₃ and C₇ and the soft switching conditions of S₃ and S₇ are expressed in Equations (8) and (9).

$$L_{r1}{i}_{Lr1}^2(t_3)\ge C_{oss}{V}_{in}^2/2$$

(8)

$$L_{r2}{i}_{Lr2}^2(t_3)\ge C_{oss}{V}_{in}^2/2$$

(9)

Step 5 [t₄, t₅]: This step starts at t₄ when v_C3 = v_C7 = 0. Due to i_Lr1(t₄) > 0 and i_Lr2(t₄) > 0, the body diodes of S₃ and S₇ conduct. Then, S₃ and S₇ naturally conduct at zero-voltage switching after t₄. In this step, v_ab = −V_Cin,1, v_cd = −V_Cin,2, V_Cb = V_Cin,2, v_Lm1 = −n₁v_Ca1, v_Lm2 = −n₂v_Ca2, v_Lo1 = v_Ca1 − V_o and v_Lo2 = v_Ca2 − V_o. In order to balance i_Lr1 and i_Lr2, the magnetic core MC is employed on the high-voltage side. Under current balance condition, V_L1 = V_L2 = 0. Therefore, v_Lr1 ≈ n₁v_Ca1 − V_in/2 and v_Lr2 ≈ n₂v_Ca2 − V_in/2. It can be observed that i_Lr1, i_Lr1, i_Lo1 and i_Lo2 all decrease in this step. When the secondary-side diode currents i_D2 = i_Lo1 and i_D4 = i_Lo2 at time t₅, diodes D_a1 and D_a2 are reverse biased. In this step, i_D2 and i_D4 increase from zero to i_Lo1 and i_Lo2, respectively and the time duration in step 5 can be obtained as:

$$\Delta t_{45}=\frac{L_{r1}{I}_{Lo1,\min }}{n_1{V}_{in}/2-n_1^2{v}_{Ca1}}\approx \frac{L_{r1}{I}_o}{n_1{V}_{in}-2n_1^2{v}_{Ca1}}$$

(10)

Since D_a1 and D_a2 are still conducting in this step, the duty loss is calculated in Equation (11).

$$d_{5,loss}\approx \frac{L_{r1}{I}_o{f}_{sw}}{n_1{V}_{in}-2n_1^2{v}_{Ca1}}$$

(11)

Step 6 [t₅, t₆]: At time t₅, i_D2 = i_Lo1 and i_D4 = i_Lo2. Then, the secondary-side diodes D_a1 and D_a2 are off and D_b1 and D_b2 are on in this step. The inductances L_r1/(n₁)² (L_r2/(n₂)²) and C_a1 (C_a2) are resonant with frequency $f_R=n_1/(2\pi \sqrt{L_{r1}{C}_{ca1}})$. Since v_Lo1 = v_Ca1 and v_Lo2 = v_Ca2, i_Lo1 and i_Lo2 both increase in this step. In order to force i_Db1 = i_Db2 = 0 at t₆, the half resonant cycle 1/(2f_R) must be less than d_eff,minT_sw/2. The primary magnetizing voltages v_Lm1 = n₁(v_Ca1 + V_o) and v_Lm2 = n₂(v_Ca2 + V_o) and the primary inductor current i_Lr1 ≈ −(i_Lo1 + i_Ca1)/n₁ and i_Lr2 ≈ −(i_Lo2 + i_Ca2)/n₂.

Step 7 [t₆, t₇]: At time t₆, i_D2 = i_Lo1 and i_D4 = i_Lo2. Then diodes D_b1 and D_b2 are off. The filter inductor voltages v_Lo1 ≈ V_in/(2n₁) − V_o and v_Lo2 ≈ V_in/(2n₂) − V_o so that i_Lo1 and i_Lo2 increase. At t₇, S₂ and S₆ turn off.

3. Steady State Analysis

Each full bridge converter in the presented converter supplies one-half of load power to low-voltage side. To balance i_Lr1 and i_Lr2, the magnetic component MC is employed in the studied converter. Under current balance condition, V_L1 = V_L2 = 0. It can be observed that the average voltages V_Ca1= V_Ca2 = V_in/(2n₁) − V_o in step 6. Under steady state operation, i_Lo1 and i_Lo2 at t₀ and t₀ + T_sw in every switching period are identical, i_Lo1(t₀) = i_Lo1(t₀ + T_sw) and i_Lo2(t₀) = i_Lo2(t₀ + T_sw). Thus, Equation (12) is derived according to voltage-second balance condition.

$$(d-d_5-d_6)(\frac{V_{in}}{2n_1}-V_o)+d_6{V}_{Ca1}=(\frac{1}{2}-d+d_5)(V_o-V_{Ca1})$$

(12)

where d₅ and d₆ are duty cycles in steps 5 and 6, respectively. Based on V_Ca1 = V_in/(2n₁) − V_o, V_o can be derived in Equation (13) under steady state.

$$V_o=\frac{V_{in}}{4n_1(1-d+d_5)}=\frac{V_{in}}{4n_1(1-d_{eff})}$$

(13)

where d_eff = d − d₅ is an effective duty ratio and δ is duty ratio when S₁ (S₂) and S₄ (S₃) are conducting. From Equation (13), the voltage gain is expressed in Equation (14).

$$G_{dc}=V_o/V_{in}=\frac{1}{4n_1(1-d_{eff})}$$

(14)

From the given input and output voltages, the turns ratio n is derived as:

$$n=n_1=n_2=\frac{V_{in}}{4V_o(1-d_{eff})}$$

(15)

Therefore, the minimum primary turns n_p and secondary turns n_s are derived in Equation (16).

$$n_p\ge \frac{V_{Lm}d{T}_{sw}}{\Delta B_{\max }{A}_e},n_s=\frac{n_p}{n}$$

(16)

where ΔB_max: maximum flux density range, A_e: effective cross area, and V_Lm: primary voltage. In steady state, I_Lo1 = I_Lo2 = I_o/2, V_Cin,1 = V_Cin,2 = V_Cb = V_in/2 and v_S1,ds =…= v_S8,ds = V_in/2. If the effective duty cycle is defined, then the ripple currents ΔL_o1 and ΔL_o2 can be obtained in Equation (17).

$$\Delta i_{Lo1}=\Delta i_{Lo2}=(V_o-V_{Ca1})(0.5-d_{eff})T_{sw}/L_o\approx (2V_o-\frac{V_{in}}{2n_1})(0.5-d_{eff})T_{sw}/L_o$$

(17)

If the ripple currents Δi_Lo1 = Δi_Lo2 = Δi_Lo are given or selected, then output inductances are achieved in Equation (18).

$$L_{o1}=L_{o2}=L_o\ge (2V_o-\frac{V_{in}}{2n_1})(0.5-d_{eff})T_{sw}/\Delta i_{Lo}$$

(18)

The winding turns of filter inductors L_o1 and L_o6 are expressed as:

$$n_{Lo1}=n_{Lo2}\ge \frac{L_{o1}{i}_{Lo1,peak}}{B_{\max }{A}_e}$$

(19)

The voltage ratings and average currents on D₁~D₄ are expressed in Equations (20)–(23).

$$V_{D1,rating}=\dots =V_{D4,rating}\approx V_{in}/n_1$$

(20)

$$V_{Da1,\mathrm{rating}}=V_{Da2,\mathrm{rating}}=V_{Db1,\mathrm{rating}}=V_{Db2,\mathrm{rating}}\approx V_o$$

(21)

I_D1,av = I_D2,av = I_D3,av = I_D4,av ≈ I_o/4

(22)

I_Da1,av = I_Da2,av = I_Db1,av = I_Db2,av ≈ dI_o/2

(23)

Based on Equation (11), the necessary inductances L_r1 and L_r2 are obtained as:

$$L_{r1}=L_{r2}\approx \frac{d_{5,loss}(n_1{V}_{in}-2n_1^2{v}_{Ca1})}{I_o{f}_{sw}}$$

(24)

4. Test Results

The studied circuit was verified through a prototype. In the prototype circuit, V_in was between 750 V and 800 V, V_o was 24 V, I_o,rated was 70 A, f_sw is 60 kHz, the effective duty cycle d_eff was 0.35, and the duty loss in step 5 was 0.01. Therefore, the turn-ratio and the primary-side inductances were obtained as:

$$n=n_1=n_2=\frac{V_{in,\min }}{4V_o(1-d_{eff})}\approx 12$$

(25)

$$L_{r1}=L_{r2}\approx \frac{d_{5,loss}(n_1{V}_{in\min }-2n_1^2{v}_{Ca1})}{I_o{f}_{sw}}\approx 16.5 \mathsf{\mu }\mathrm{H}$$

(26)

In the prototype circuit, the actual magnetizing inductance, L_m1 = L_m2 = 2 mH, the primary turns n_1,p and n_2,p were 48 and the secondary turns n_1,s and n_2,s were 4 with TDK EER-42 magnetic core. The maximum ripple currents Δi_Lo was assumed as 4 A. The L_o1 and L_o2 can be obtained in Equation (27).

$$L_{o1}=L_{o2}=(2V_o-\frac{V_{in,\min }}{2n_1})(0.5-d_{eff})T_{sw}/\Delta i_{Lo}\approx 10.5 \mathsf{\mu }\mathrm{H}$$

(27)

MOSFETs SiHG20N50C with 500 V/20 A ratings were selected for S₁~S₈. MBR40100PT with 100 V/40 A ratings were selected for D₁~D₄ and D_a1~D_b2. The magnetic coupling (MC) transformer n_p:n_s = 24 turns:24 turns. The adopted capacitors were C_in,1 = C_in,2 = 240 μF/450 V, C_b = 1 μF, C_a1 = C_a2 = 8.8 μF and C_o = 2200 μF/100 V. The PSPWM integrated circuit UCC3895 was selected as a controller to control S₁~S₈.

The experimental test bench is given in Figure 5. The dc power source was using a two Chroma 62016P-600-8 programmable dc power supply connected in series to supply 800 V at the input side of the proposed circuit. The dc electronic load was a Chroma 63112A programmable dc load. The digital oscilloscope Tektronix TDS3014B was adopted to measure the test waveforms. Figure 6 illustrates the test waveforms of the gate voltages of switches S₁~S₄ in first full bridge circuit at rated power. The phase-shift angle between S₁ and S₄ depended on the input voltage. The gating voltages of S₅~S₈ in second full bridge circuit were identical to S₁~S₄, respectively. The gating voltages v_S1,g and v_S4,g and ac voltages v_ab and v_cd at rated power are demonstrated in Figure 7. Three-level voltages were observed on v_ab and v_cd. Figure 8 illustrates the test waveforms v_ab, v_cd, i_Lr1 and i_Lr2 under 20% power and rated power. Two primary-side currents were well balanced with each other due to the current balance magnetic core is used to achieve current sharing. Figure 9 gives the test results of V_Cin1, V_Cin2 and V_Cb at rated power. Split capacitor voltages were well balanced with V_Cin1 = 401.6 V and V_Cin2 = 398.4 V. Figure 10 gives the measured waveforms of output side currents. Figure 11 provides the test waveforms of i_Lo1, i_Db1, i_o1 and i_o2 under different load conditions. It is clear that i_o1 and i_o2 were balanced. Figure 12 provides the measured results of S₁ under 20% power and rated power. The soft switching of S₁ was succeeded from 20% power to rated power. The other switches such as S₂, S₅ and S₆ had the same characteristics as S₁. Therefore, S₂, S₅ and S₆ were also turned on with soft switching turn-on from 20% power. Figure 13 demonstrates the measured waveforms of S₄ under half and full loads. The soft switching of S₄ are realized from 50% load due to the energy on L_m1 and L_m2. Likewise, S₃, S₇ and S₈ have same characteristics as S₄ and S₃, S₇ and S₈ with soft switching turn-on from 50% power. The test efficiencies of the presented circuit are 91.7% at 20% power, 93.5% at 50% power and 92.9% at 100% power and shown in Figure 14.

5. Conclusions

A parallel dc/dc converter was proposed and investigated to achieve the main benefits of balanced input split voltages, load current sharing and reduced circulating current loss. Input split voltage balance was realized using a balance capacitor to automatically charge/discharge split capacitors in every switching cycle. The current sharing of two series full bridge circuits was achieved using a magnetic core. Passive circuits were employed on output side to decrease primary circulating current at commutated state. However, the proposed converter was out of work under power switch failure. Therefore, some bypass circuits may be added in the circuit to protect the converter from damage. This protection procedure is the next study case to further improve the circuit reliability. The theoretical analysis was well supported by the test waveforms of a prototype.