Analysis of a DC Converter with Low Primary Current Loss and Balance Voltage and Current

Abstract: A dc/dc pulse width modulation (PWM) circuit was investigated to realize the functions of reduced primary current loss and balanced voltage and current distribution. In the presented dc/dc converter, two full bridge pulse width modulation circuits were used with the series/parallel connection on the high-voltage/low-voltage side. The flying capacitor was adopted on the input side to achieve voltage balance on input split capacitors. The magnetic coupling element was employed to achieve current sharing between two parallel circuits. A capacitor-diode passive circuit was adopted to lessen the primary current at the commutated interval. The phase-shifted duty cycle control approach was employed to regulate load voltage and implement soft switching characteristics of power metal-oxide-semiconductor field-effect transistors (MOSFETs). Finally, the experimental results using a 1.68 kW prototype converter were obtained to confirm the performance and feasibility of the studied circuit topology.


Introduction
High power density/efficiency dc/dc converters [1,2] have been proposed to reduce unnecessary power loss in order to reduce environmental pollution and met global energy demands.Clean and renewable energy sources meet these requirements to provide available ac or dc power to ac utilities, dc micro-grids, residential houses and commercial buildings by using power electronic based converters or inverters.High-voltage pulse width modulation (PWM) converters have been presented for industry power units [3,4], dc micro-grid systems [5][6][7] and dc traction or dc light rail transportation systems [8,9].For these applications, the dc bus voltage is regulated between 750 V and 800 V. Full bridge circuits with a high switching frequency high-voltage rating SiC MOSFET or high-voltage rating insulated gate bipolar transistor (IGBT) devices can be adopted for high dc voltage applications.However, 1200 V SiC MOSFET devices are expensive and 1200 V IGBT devices have low switching frequency problems.Cost and performance are always the two main issues in the development of the available and high reliability power converters.Therefore, MOSFET power devices have been widely adopted in high efficiency power electronics.To improve the low-voltage drawback of MOSFETs in high-voltage applications, zero voltage switching, multi-level circuit topologies [10][11][12][13][14] have been developed and proposed to decrease conduction and switching losses.The phase shift pulse width modulation (PSPWM) and frequency modulation have normally been adopted to regulate duty cycle or switching frequency.However, the main disadvantage of conventional PSPWM is high circulating current losses at low effective duty cycle.In order to reduce circulating current, an active or passive snubber used on the low-voltage side has been proposed in [15][16][17].A modular dc/dc converter [18] using low power rating modular circuits in series or parallel connection has been proposed to increase circuit efficiency and power rating.However, the current between each modular circuit may be unbalanced.To accomplish current balance issue, several current balancing approaches have been presented in [19,20].
A series/parallel-connected dc/dc converter is proposed to accomplish reduced primary circulating current, a soft switching operation, and balanced input voltages and output currents.Two full bridge circuits with series/parallel connection on input/output side are used in the studied circuit to achieve voltage and current sharing for the high voltage input and current output.Therefore, power devices on each full bridge circuit have V in /2 voltage stress.To prevent input split voltages imbalance, a voltage balance capacitor was used on the input side to automatically achieve split voltages balance.Passive snubber circuits were employed on output side to create a positive voltage on the secondary rectified terminal under the commutated state so that the primary current at the commutated state can be reduced.To realize current sharing of two full bridge circuits, a current-balance magnetic component was adopted on the high-voltage side.If two currents are unbalanced, then one induced voltage of MC component is decreased to lessen the larger converter current.Therefore, two converter currents can be compensated automatically.PSPWM was adopted to control power devices and accomplish soft switching operation of active switches.The organization of this paper is as follows: The circuit structure and the principle of operation are discussed in Section 2. The steady state operation of the presented converter is shown in Section 3. Test results with a laboratory prototype are presented and investigated in Section 4. The conclusions of the studied converter are discussed in Section 5.

Circuit Structure and Principle of Operation
High-voltage converters were researched and presented for industry power supplies, dc traction vehicle and dc micro-grid systems.Ac/dc power converters with low harmonic currents, high power factor (PFC) and a stable dc voltage shown in Figure 1a are required for industry power converters.Normally, the dc voltage V H is controlled at 760 V.Then, a high-frequency link converter is adopted to provide low-voltage output.Figure 1b illustrates the basic power distributed diagrams on dc light rail vehicle.A high-voltage dc converter can convert a 760 V input to supply a low-voltage output for battery charger, control, and communication demands.Figure 1c demonstrates the blocks of a bipolar dc micro-grid system to integrate ac utility system, clean energy generators and industry load and residential load into a common dc bus voltage.
Figure 2 gives the converter configuration of the developed circuit with series/parallel connection of full bridge circuits to achieve low circulating current loss, soft switching for power MOSFETs, and balanced input split voltages and output current sharing.The first full bridge circuit has power MOSFETs S 1 -S 4 with the output capacitors C 1 -C 4 , leakage or external inductor L r1 , transformer T 1 , magnetic core MC, filter inductor L o1 , secondary-side rectifier diodes D 1 and D 2 , and passive circuit including C a1 , D a1 and D b1 .Likewise, the second full bridge circuit includes the components S 5 -S 8 , C 5 -C 8 , L r2 , T 2 , MC, L o2 , D 3 , D 4 , C a2 , D a2 and D b2 .C in,1 and C in,2 are input split capacitors and C b is the balance capacitor.Each circuit can transfer one-half rated power to the secondary side.The magnetic core [20] is used to balance i Lr1 and i Lr2 .Under the balanced primary currents (|i Lr1 | = |i Lr2 |), the induced voltages V L1 and V L2 are zero.If i Lr1 and i Lr2 are unbalanced (such as |i Lr1 | > |i Lr2 |), the induced voltage V L1 of MC cell is decreased in order to decrease i Lr1 and V L2 is increased to increase i Lr2 .Thus, i Lr1 will equal i Lr2 and V L1 = V L2 = 0. PSPWM is used to control S 1 ~S8 and have zero voltage switching on the MOSFETs.Power switches S 1 ~S4 and S 5 ~S8 have identical PWM waveforms.The balance capacitor C b is linked between points a and c.If S 1 and S 5 are on and S 2 and S 6 are off, then V Cb = V Cin,1 .Likewise, V Cb = V Cin,2 if S 2 and S 6 are on and S 1 and S 5 are in the off.Since the duty cycle d S1 = d S2 = 0.5, it is obvious that V Cb = V Cin,1 = V Cin,2 = V in /2.Thus, the drain voltages of S 1 ~S8 are V in /2.To decrease the primary-side circulating currents, passive snubbers, C a1 , D a1 , D b1 , C a2 , D a2 , D b2 , are used on the presented circuit.At the same time, the filter inductor voltages v Lo1 = v Ca1 − V o and v Lo2 = v Ca2 − V o rather than −V o in the traditional full bridge duty cycle converters.
Normally, the dc voltage VH is controlled at 760 V.Then, a high-frequency link converter is adopted to provide low-voltage output.Figure 1b illustrates the basic power distributed diagrams on dc light rail vehicle.A high-voltage dc converter can convert a 760 V input to supply a low-voltage output for battery charger, control, and communication demands.Figure 1c demonstrates the blocks of a bipolar dc micro-grid system to integrate ac utility system, clean energy generators and industry load and residential load into a common dc bus voltage.
Three-phase ac/dc dc/dc converter Figure 2 gives the converter configuration of the developed circuit with series/parallel connection of full bridge circuits to achieve low circulating current loss, soft switching for power MOSFETs, and balanced input split voltages and output current sharing.The first full bridge circuit has power MOSFETs S1-S4 with the output capacitors C1-C4, leakage or external inductor Lr1, transformer T1, magnetic core MC, filter inductor Lo1, secondary-side rectifier diodes D1 and D2, and passive circuit including Ca1, Da1 and Db1.Likewise, the second full bridge circuit includes the components S5-S8, C5-C8, Lr2, T2, MC, Lo2, D3, D4, Ca2, Da2 and Db2.Cin,1 and Cin,2 are input split capacitors and Cb is the balance capacitor.Each circuit can transfer one-half rated power to the secondary side.The magnetic core [20] is used to balance iLr1 and iLr2.Under the balanced primary currents (|iLr1| = |iLr2|), the induced voltages VL1 and VL2 are zero.If iLr1 and iLr2 are unbalanced (such as |iLr1| > |iLr2|), the induced voltage VL1 of MC cell is decreased in order to decrease iLr1 and VL2 is increased to increase iLr2.Thus, iLr1 will equal iLr2 and VL1 = VL2 = 0. PSPWM is used to control S1~S8 and have zero voltage switching on the MOSFETs.Power switches S1~S4 and S5~S8 have identical PWM waveforms.The balance capacitor Cb is linked between points a and c.If S1 and S5 are on and S2 and S6 are off, then VCb = VCin,1.Likewise, VCb = VCin,2 if S2 and S6 are on and S1 and S5 are in the off.Since the duty cycle dS1 = dS2 = 0.5, it is obvious that VCb = VCin,1 = VCin,2 = Vin/2.Thus, the drain voltages of S1~S8 are Vin/2.To decrease the primary-side circulating currents, passive snubbers, Ca1, Da1, Db1, Ca2, Da2, Db2, are used on the presented circuit.At the same time, the filter inductor voltages vLo1 = vCa1-Vo and vLo2 = vCa2-Vo rather than −Vo in the traditional full bridge duty cycle converters. :1:1 The operation principle of the presented circuit is discussed with the assumptions: (1) Cin,1 = Cin,2; (2 VCin,2 = Vin/2; and (8) n1 = n2= n. Figure 3 shows the PWM waveforms of the studied converter.The duty The operation principle of the presented circuit is discussed with the assumptions: 3 shows the PWM waveforms of the studied converter.The duty cycle of S 1 ~S8 is 0.5.The gating signals of S 4 (S 3 ) is shifted to S 1 (S 2 ), respectively.Due to the switching states of power devices, the converter has fourteen steps in a switching period.The PWM waveforms are symmetrical for every half cycle.Therefore, only the first seven steps are discussed and the circuits of first seven operating steps are illustrated in Figure 4.  Step 1 [t0, t1]: Before t0, S1, S4, S5, S8, D1 and D3 conduct, iLr1 > 0 and iLr2 > 0. After t0, power MOSFETs S1 and S5 turn off.C1 and C5 are charged and C2 and C6 are discharged.The energy on Lr1, Lr2, Lo1 and Lo2 can discharge C2 and C6.Equations ( 1) and ( 2) give the soft switching conditions of S2 and S6.
The time duration t01 is related to the load current and input voltage.
Thus, the circulating current is decreased under the commutated state.In this step, the balance capacitor voltage VCb = VCin,2.Step If these conditions are satisfied, then v C1 = v C5 = V in /2 and v C2 = v C6 = 0 at t 1 .The time duration in step 1 is obtained in Equation (3).
The time duration ∆t 01 is related to the load current and input voltage.
Step 2 [t 1 , t 2 ]: At t 1 , v C2 = v C6 = 0.The positive primary currents i Lr1 and i Lr2 will flow through the body diode of S 2 and S 6 .Thus, power MOSFETs S 2 and S 6 can achieve zero-voltage switching after t 1 .
The ac side voltages v ab = v cd = 0 and i Lr1 and i Lr2 decrease.Therefore, D a1 and D a2 conduct at this freewheeling state.The magnetizing voltages v Lm1 and v Lm2 are clamped at v Ca1 and v Ca2 , respectively.The primary inductor voltages Thus, the circulating current is decreased under the commutated state.In this step, the balance capacitor voltage V Cb = V Cin,2 .
Step 5 [t 4 , t 5 ]: This step starts at t 4 when v C3 = v C7 = 0. Due to i Lr1 (t 4 ) > 0 and i Lr2 (t 4 ) > 0, the body diodes of S 3 and S 7 conduct.Then, S 3 and S 7 naturally conduct at zero-voltage switching after t 4 .
In this step, In order to balance i Lr1 and i Lr2 , the magnetic core MC is employed on the high-voltage side.Under current balance condition, It can be observed that i Lr1 , i Lr1 , i Lo1 and i Lo2 all decrease in this step.When the secondary-side diode currents i D2 = i Lo1 and i D4 = i Lo2 at time t 5 , diodes D a1 and D a2 are reverse biased.In this step, i D2 and i D4 increase from zero to i Lo1 and i Lo2 , respectively and the time duration in step 5 can be obtained as: Since D a1 and D a2 are still conducting in this step, the duty loss is calculated in Equation (11).
Step 6 [t 5 , t 6 ]: At time t 5 , i D2 = i Lo1 and i D4 = i Lo2 .Then, the secondary-side diodes D a1 and D a2 are off and D b1 and D b2 are on in this step.The inductances L r1 /(n 1 ) 2 (L r2 /(n 2 ) 2 ) and C a1 (C a2 ) are resonant with frequency f R = n 1 /(2π , i Lo1 and i Lo2 both increase in this step.In order to force i Db1 = i Db2 = 0 at t 6 , the half resonant cycle 1/(2f R ) must be less than d eff,min T sw /2.The primary magnetizing voltages v Lm1 = n 1 (v Ca1 + V o ) and v Lm2 = n 2 (v Ca2 + V o ) and the primary inductor current i Lr1 ≈ −(i Lo1 + i Ca1 )/n 1 and i Lr2 ≈ −(i Lo2 + i Ca2 )/n 2 .
Step 7 [t 6 , t 7 ]: At time t 6 , i D2 = i Lo1 and i D4 = i Lo2 .Then diodes D b1 and D b2 are off.The filter inductor voltages v Lo1 ≈ V in /(2n 1 ) − V o and v Lo2 ≈ V in /(2n 2 ) − V o so that i Lo1 and i Lo2 increase.At t 7 , S 2 and S 6 turn off.
Step 4 [t3, t4]: At t3, power MOSFETs S4 and S8 turn off.C3 and C7 are discharged and C4 and C8 are charged.The energy on Lr1 and Lr2 can discharge C3 and C7 and the soft switching conditions of S3 and S7 are expressed in Equations ( 8) and ( 9).

Steady State Analysis
Each full bridge converter in the presented converter supplies one-half of load power to lowvoltage side.To balance iLr1 and iLr2, the magnetic component MC is employed in the studied converter.Under current balance condition, VL1 = VL2 = 0.It can be observed that the average voltages VCa1= VCa2 = Vin/(2n1)-Vo in step 6.Under steady state operation, iLo1 and iLo2 at t0 and t0+Tsw in every switching period are identical, iLo1(t0) = iLo1(t0+Tsw) and iLo2(t0) = iLo2(t0+Tsw).Thus, Equation ( 12) is derived according to voltage-second balance condition.
where d5 and d6 are duty cycles in steps 5 and 6, respectively.Based on VCa1 = Vin/(2n1)-Vo, Vo can be derived in Equation ( 13) under steady state.
where deff = d-d5 is an effective duty ratio and  is duty ratio when S1 (S2) and S4 (S3) are conducting.
From Equation ( 13), the voltage gain is expressed in Equation ( 14).
From the given input and output voltages, the turns ratio n is derived as:

Steady State Analysis
Each full bridge converter in the presented converter supplies one-half of load power to low-voltage side.To balance i Lr1 and i Lr2 , the magnetic component MC is employed in the studied converter.Under current balance condition, V L1 = V L2 = 0.It can be observed that the average voltages V Ca1 = V Ca2 = V in /(2n 1 ) − V o in step 6.Under steady state operation, i Lo1 and i Lo2 at t 0 and t 0 + T sw in every switching period are identical, i Lo1 (t 0 ) = i Lo1 (t 0 + T sw ) and i Lo2 (t 0 ) = i Lo2 (t 0 + T sw ).Thus, Equation ( 12) is derived according to voltage-second balance condition.
where d 5 and d 6 are duty cycles in steps 5 and 6, respectively.Based on V Ca1 = V in /(2n 1 ) − V o , V o can be derived in Equation ( 13) under steady state.
where d eff = d − d 5 is an effective duty ratio and δ is duty ratio when S 1 (S 2 ) and S 4 (S 3 ) are conducting.From Equation ( 13), the voltage gain is expressed in Equation ( 14).
From the given input and output voltages, the turns ratio n is derived as: Therefore, the minimum primary turns n p and secondary turns n s are derived in Equation (16).
where ∆B max : maximum flux density range, A e : effective cross area, and V Lm : primary voltage.
In steady state, If the effective duty cycle is defined, then the ripple currents ∆L o1 and ∆L o2 can be obtained in Equation (17).
If the ripple currents ∆i Lo1 = ∆i Lo2 = ∆i Lo are given or selected, then output inductances are achieved in Equation (18).
The winding turns of filter inductors L o1 and L o6 are expressed as: The voltage ratings and average currents on D 1 ~D4 are expressed in Equations ( 20)-(23).

Test Results
The studied circuit was verified through a prototype.In the prototype circuit, V in was between 750 V and 800 V, V o was 24 V, I o,rated was 70 A, f sw is 60 kHz, the effective duty cycle d eff was 0.35, and the duty loss in step 5 was 0.01.Therefore, the turn-ratio and the primary-side inductances were obtained as: In the prototype circuit, the actual magnetizing inductance, L m1 = L m2 = 2 mH, the primary turns n 1,p and n 2,p were 48 and the secondary turns n 1,s and n 2,s were 4 with TDK EER-42 magnetic core.The maximum ripple currents ∆i Lo was assumed as 4 A. The L o1 and L o2 can be obtained in Equation (27).The experimental test bench is given in Figure 5.The dc power source was using a two Chroma 62016P-600-8 programmable dc power supply connected in series to supply 800 V at the input side of the proposed circuit.The dc electronic load was a Chroma 63112A programmable dc load.The digital oscilloscope Tektronix TDS3014B was adopted to measure the test waveforms.Figure 6 illustrates the test waveforms of the gate voltages of switches S 1 ~S4 in first full bridge circuit at rated power.The phase-shift angle between S 1 and S 4 depended on the input voltage.The gating voltages of S 5 ~S8 in second full bridge circuit were identical to S 1 ~S4 , respectively.The gating voltages v S1,g and v S4,g and ac voltages v ab and v cd at rated power are demonstrated in Figure 7. Three-level voltages were observed on v ab and v cd .Figure 8 illustrates the test waveforms v ab , v cd , i Lr1 and i Lr2 under 20% power and rated power.Two primary-side currents were well balanced with each other due to the current balance magnetic core is used to achieve current sharing.Figure 9 gives the test results of V Cin1 , V Cin2 and V Cb at rated power.Split capacitor voltages were well balanced with V Cin1 = 401.6V and V Cin2 = 398.4V. Figure 10 gives the measured waveforms of output side currents.Figure 11 provides the test waveforms of i Lo1 , i Db1 , i o1 and i o2 under different load conditions.It is clear that i o1 and i o2 were balanced.Figure 12 provides the measured results of S 1 under 20% power and rated power.The soft switching of S 1 was succeeded from 20% power to rated power.The other switches such as S 2 , S 5 and S 6 had the same characteristics as S 1 .Therefore, S 2 , S 5 and S 6 were also turned on with soft switching turn-on from 20% power.Figure 13 demonstrates the measured waveforms of S 4 under half and full loads.The soft switching of S 4 are realized from 50% load due to the energy on L m1 and L m2 .Likewise, S 3 , S 7 and S 8 have same characteristics as S 4 and S 3 , S 7 and S 8 with soft switching turn-on from 50% power.The test efficiencies of the presented circuit are 91.7% at 20% power, 93.5% at 50% power and 92.9% at 100% power and shown in Figure 14.
The experimental test bench is given in Figure 5.The dc power source was using a two Chroma 62016P-600-8 programmable dc power supply connected in series to supply 800 V at the input side of the proposed circuit.The dc electronic load was a Chroma 63112A programmable dc load.The digital oscilloscope Tektronix TDS3014B was adopted to measure the test waveforms.Figure 6 illustrates the test waveforms of the gate voltages of switches S1~S4 in first full bridge circuit at rated power.The phase-shift angle between S1 and S4 depended on the input voltage.The gating voltages of S5~S8 in second full bridge circuit were identical to S1~S4, respectively.The gating voltages vS1,g and vS4,g and ac voltages vab and vcd at rated power are demonstrated in Figure 7. Three-level voltages were observed on vab and vcd. Figure 8 illustrates the test waveforms vab, vcd, iLr1 and iLr2 under 20% power and rated power.Two primary-side currents were well balanced with each other due to the current balance magnetic core is used to achieve current sharing.Figure 9 gives the test results of VCin1, VCin2 and VCb at rated power.Split capacitor voltages were well balanced with VCin1 = 401.6V and VCin2 = 398.4V. Figure 10 gives the measured waveforms of output side currents.Figure 11 provides the test waveforms of iLo1, iDb1, io1 and io2 under different load conditions.It is clear that io1 and io2 were balanced.Figure 12 provides the measured results of S1 under 20% power and rated power.The soft switching of S1 was succeeded from 20% power to rated power.The other switches such as S2, S5 and S6 had the same characteristics as S1.Therefore, S2, S5 and S6 were also turned on with soft switching turn-on from 20% power.Figure 13 demonstrates the measured waveforms of S4 under half and full loads.The soft switching of S4 are realized from 50% load due to the energy on Lm1 and Lm2.Likewise, S3, S7 and S8 have same characteristics as S4 and S3, S7 and S8 with soft switching turn-on from 50% power.The test efficiencies of the presented circuit are 91.7% at 20% power, 93.5% at 50% power and 92.9% at 100% power and shown in Figure 14.

Conclusions
A parallel dc/dc converter was proposed and investigated to achieve the main benefits of balanced input split voltages, load current sharing and reduced circulating current loss.Input split voltage balance was realized using a balance capacitor to automatically charge/discharge split capacitors in every switching cycle.The current sharing of two series full bridge circuits was achieved using a magnetic core.Passive circuits were employed on output side to decrease primary circulating current at commutated state.However, the proposed converter was out of work under power switch failure.Therefore, some bypass circuits may be added in the circuit to protect the converter from damage.This protection procedure is the next study case to further improve the circuit reliability.The theoretical analysis was well supported by the test waveforms of a prototype.

Figure 1 .
Figure 1.High-voltage dc/dc converters in (a) ac/dc converters, (b) dc light rail transportation vehicle, (c) dc micro-grid system with bipolar voltages.

Figure 2
Figure 2 gives the converter configuration of the developed circuit with series/parallel connection of full bridge circuits to achieve low circulating current loss, soft switching for power MOSFETs, and balanced input split voltages and output current sharing.The first full bridge circuit has power MOSFETs S1-S4 with the output capacitors C1-C4, leakage or external inductor Lr1, transformer T1, magnetic core MC, filter inductor Lo1, secondary-side rectifier diodes D1 and D2, and passive circuit including Ca1, Da1 and Db1.Likewise, the second full bridge circuit includes the components S5-S8, C5-C8, Lr2, T2, MC, Lo2, D3, D4, Ca2, Da2 and Db2.Cin,1 and Cin,2 are input split capacitors and Cb is the balance capacitor.Each circuit can transfer one-half rated power to the secondary side.The magnetic core [20] is used to balance iLr1 and iLr2.Under the balanced primary currents (|iLr1| = |iLr2|), the induced voltages VL1 and VL2 are zero.If iLr1 and iLr2 are unbalanced (such as |iLr1| > |iLr2|), the induced voltage VL1 of MC cell is decreased in order to decrease iLr1 and VL2 is increased to increase iLr2.Thus, iLr1 will equal iLr2 and VL1 = VL2 = 0. PSPWM is used to control S1~S8 and have zero voltage switching on the MOSFETs.Power switches S1~S4 and S5~S8 have identical PWM waveforms.The balance capacitor Cb is linked between points a and c.If S1 and S5 are on and S2 and S6 are off, then VCb = VCin,1.Likewise, VCb = VCin,2 if S2 and S6 are on and S1 and S5 are in the off.Since the duty cycle dS1 = dS2 = 0.5, it is obvious that VCb = VCin,1 = VCin,2 = Vin/2.Thus, the drain voltages of S1~S8 are Vin/2.To decrease the primary-side circulating currents, passive snubbers, Ca1, Da1, Db1, Ca2, Da2, Db2, are used on the presented circuit.At the same time, the filter inductor voltages vLo1 = vCa1-Vo and vLo2 = vCa2-Vo rather than −Vo in the traditional full bridge duty cycle converters.

Figure 2 .
Figure 2. Circuit configuration of the studied converter.

Figure 5 .
Figure 5. Pictures of the presented circuit in the laboratory: (a) experimental setup and (b) prototype circuit.

1 &S 5 i D1 +i D2 i Ca1 , i Ca2 i Lo1 , i Lo2 t 0 t 1 t 2 t 3 t 4 t 5 t 6 t V in /2 0 -V in /2 t 7 S 2 &S 6 S 4 &S 8 S 3 &S 7 v ab , v cd i Lr1 , i Lr2 i D3 +i D4
Electronics 2019, 8, 439 4 of 15 cycle of S1~S8 is 0.5.The gating signals of S4 (S3) is shifted to S1 (S2), respectively.Due to the switching states of power devices, the converter has fourteen steps in a switching period.The PWM waveforms are symmetrical for every half cycle.Therefore, only the first seven steps are discussed and the circuits of first seven operating steps are illustrated in Figure4.
Before t 0 , S 1 , S 4 , S 5 , S 8 , D 1 and D 3 conduct, i Lr1 > 0 and i Lr2 > 0. After t 0 , power MOSFETs S 1 and S 5 turn off.C 1 and C 5 are charged and C 2 and C 6 are discharged.The energy on L r1 , L 1 [t 0 , t 1 ]: r2 , L o1 and L o2 can discharge C 2 and C 6 .Equations (1) and (2) give the soft switching conditions of S 2 and S 6 .
Lo1 , i Ca2 = −i Lo2 , i Lr1 = i Lm1 (t 2 ) and i Lr2 = i Lm2 (t 2 ).Since i Lm1 (t 2 ) and i Lm2 (t 2 ) are close to zero, the circulating current is removed.The filter inductor voltagesv Lo1 = v Ca1 − V o < 0 and v Lo2 = v Ca2 − V o < 0.The secondary-side currents i Lo1 and i Lo2 are lessened.Step 4 [t 3 , t 4 ]: At t 3 , power MOSFETs S 4 and S 8 turn off.C 3 and C 7 are discharged and C 4 and C 8 are charged.The energy on L r1 and L r2 can discharge C 3 and C 7 and the soft switching conditions of S 3 and S 7 are expressed in Equations ( 3 [t 2 , t 3 ]: At time t 2 , i D1 = i D3 = 0 and D 1 and D 3 are off.Then, i Ca1 = −i