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Open AccessArticle

A Fast-Transient All-Digital LDO with Adaptive Clock Technique

by Yi Yu 1,2, Jia Yuan 1, Shushan Qiao 1,2,* and Yong Hei 1
1
Smart sensing R&D center, Institute of microelectronics of Chinese academy of sciences, Beijing 100029, China
2
School of Electronic, Electrical and Communication Engineering, University of Chinese academy of sciences, Beijing 100049, China
*
Author to whom correspondence should be addressed.
Electronics 2019, 8(12), 1422; https://doi.org/10.3390/electronics8121422
Received: 17 October 2019 / Revised: 8 November 2019 / Accepted: 26 November 2019 / Published: 28 November 2019
(This article belongs to the Section Microelectronics and Optoelectronics)
To get a better tradeoff between the transient performance and current efficiency of Digital Low-Dropout(DLDO) regulator, this paper proposes an all-digital Low-Dropout(LDO) regulator with adaptive clock technique. The sample clock is supplied by a proposed digital oscillator (DOSC) whose output frequency can be changed seamlessly. The frequency of sample clock and loop gain boost adaptively when the output voltage undershoot/overshoot is detected. Proposed DLDO integrates a ripple controller to eliminate steady-state supply ripple and reduce steady-state power. The proposed DLDO is simulated at Semiconductor Manufacturing International Corporation (SMIC) 55 nm with 5.03e-4 mm2 active area. The simulation results show that the operating voltage of proposed DLDO can be down to 0.5 V and the peak current efficiency is 99.99%. The measured voltage undershoot is 40 mV and transient response time is 500 ns with load step of 10 to 800 uA.
Keywords: digital low dropout (DLDO), current efficiency; regulator; low voltage digital low dropout (DLDO), current efficiency; regulator; low voltage
MDPI and ACS Style

Yu, Y.; Yuan, J.; Qiao, S.; Hei, Y. A Fast-Transient All-Digital LDO with Adaptive Clock Technique. Electronics 2019, 8, 1422.

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