A Fast-Transient All-Digital LDO with Adaptive Clock Technique

Abstract

To get a better tradeoff between the transient performance and current efficiency of Digital Low-Dropout (DLDO) regulator, this paper proposes an all-digital Low-Dropout (LDO) regulator with adaptive clock technique. The sample clock is supplied by a proposed digital oscillator (DOSC) whose output frequency can be changed seamlessly. The frequency of sample clock and loop gain boost adaptively when the output voltage undershoot/overshoot is detected. Proposed DLDO integrates a ripple controller to eliminate steady-state supply ripple and reduce steady-state power. The proposed DLDO is simulated at Semiconductor Manufacturing International Corporation (SMIC) 55 nm with 5.03e-4 mm2 active area. The simulation results show that the operating voltage of proposed DLDO can be down to 0.5 V and the peak current efficiency is 99.99%. The measured voltage undershoot is 40 mV and transient response time is 500 ns with load step of 10 to 800 uA.

1. Introduction

Internet of Things (IoT), mobile and medical application have urge the Very Large Scale Integrated circuites (VLSI) designer to build ultra-low power (ULP) circuits [1,2]. Since power consumption deceases quadratically with the drop of supply voltage, low-voltage technology is one of the important means to reduce the power consumption of digital circuits [3,4,5]. As power supply voltages are scaling down to near/sub-threshold, traditional power management faces new challenges [6,7]. A Low-Dropout (LDO) regulator is widely utilized as a post-regulator to provide a clean supply voltage for a system-on–chip (SoC) [8]. Traditional analog LDO (ALDO) cannot operate at very low voltages due to the presence of an analog amplifier [9,10]. Digital LDO has been proposed to solve this problem [11]. Moreover, the DLDO has a better process scalability and the ability of fine-grained power control [12]. Digital LDO replaces the error amplifier in the analog LDO with comparators and shift register (S/R). Figure 1 shows the schematic diagram of analog LDO and digital LDO respectively. DLDO consists of a comparator (CMP), a bi-direction shift register (S/R) and a PMOS array. The comparator compares the output voltage (Vout) with the reference voltage (Vref) and gives a direction signal for S/R. The S/R increases or decreases the number of PMOS turned-on according to the output of the comparator to make the error between Vout and Vref as small as possible. Since only one PMOS is turned on/off per clock cycle, the transient response time of this DLDO is mainly determined by its sample frequency Fs. Increasing Fs can reduce the transient response time, but the negative impact is a larger steady-state power consumption and lower current efficiency. Moreover, traditional DLDOs also have a supply ripple at the steady state.

Figure 1. (a) traditional analog Low-Dropout (LDO) regulator, (b) basic diagram of DLDO.

Several previous works have been proposed to solve those problems. The literature [10] proposes an asynchronous DLDO which significantly reduces the power introduced by the clock and speeds up the transient response of DLDO. However, the asynchronous circuits are complicated, which introduces excessive area overhead and difficulty of synthesizing and timing analyzing. Literature [13] proposed a DLDO based TSPC which has achieved a faster loop time with the penalty of degrading of current efficiency. Literature [14] proposed a DLDO controlled by phase-locked clock, which achieves a fast transient response, but the stacking of power PMOS causes a drop of current efficiency and make it unable to work at very low voltages. A DLDO combined coarse-tuning and fine-tuning (CFT) proposed by [15] makes a good tradeoff between power consumption and transient response time, but it needs two clock, which make a large area overhead.

This paper proposes a DLDO based on adaptive clock technique which achieves a fast transient response with low supply ripple and a high current efficiency. The measured voltage undershoot are 55 mV with load steps of 10 to 800 uA with 40 ns edge time. The current efficiency of the proposed DLDO is 99.99% at steady state.

2. Proposed Technique

The block diagram of proposed DLDO is shown as Figure 2. PMOS array is consists of 128 low-threshold PMOS transistors controlled by a bi-direction S/R with tunable shift step. The shift step of S/R determines the loop gain of DLDO. The resistor ladder provides five different reference voltages to comparators for undershoot/overshoot detecting. The schematic of comparator is shown as Figure 2b. The resistor ladder together with comparator act like an analog-digital convertor (ADC). The 5-bit output RCMP of the comparator reflects the difference between the output voltage Vout and the reference voltage Vref. The sample clock is supplied by a ring oscillator whose output frequency is digitally controllable (DOSC). RCMP controls the shift step of S/R and the output frequency of DOSC. That is when undershoot/overshoot of output voltage is detected, the loop gain and sample clock increase adaptively for a fast transient response. Table 1 shows the S/R shift step and the output frequency of DOSC corresponding to different RCMP values. Traditional DLDO also suffer from supply ripple and large consumption at steady state, just as shown in Figure 3. In order to solve those problems, we integrates a ripple controller into the design. Figure 4 shows the structure of ripple controller. When the output voltage reaches the steady state, that is, the output voltage oscillates around Vref, the ripple controller detects this fluctuation and generates a clock gating signal PCK_E to gated the clock of S/R by integrated clock gating cell (ICG). The supply ripple is eliminated and power consumption is reduced at the steady-state. The DOSC provides a variable sample clock for this design. Its structure is shown in Figure 2c. An odd number of inverters are connected end to end to form a ring oscillator. Similar to the current starved oscillator, the ring oscillator is powered by three parallel PMOS and NMOS devices with different sizes. The output frequency of DOSC can change seamlessly depending on the value of the FCTR. The FCTR is obtained by simple decoding (DEC) of RCMP. The truth table of DEC is shown in Table 2. When the difference between Vout and Vref increases, the sampling clock frequency generated by the DOSC also increases, causing the output voltage to reach reference voltage rapidly.

Figure 2. Structure of proposed DLDO. (a) The block diagram of proposed DLDO, (b) the structure of comparator, (c) the structure of Digital Oscillator(DOSC).

Table 1. The shift step of S/R and frequency of DOSC corresponding to different RCMP.

RCMP	Shift Step of S/R	Freq. of DOSC
00000	3	12~350 MHz
00001	2	9~200 MHz
00011	1	6~100 MHz
00111	1	6~100 MHz
01111	2	9~200 MHz
11111	3	12~350 MHz

Figure 3. Steady-state supply ripple of traditional DLDO.

Figure 4. Structure of ripple controller.

Table 2. The truth table of DEC.

RCMP	FCTR
00000	000
00001	100
00011	110
00111	110
01111	100
11111	000
others	110

3. Design Consideration

The Value of ΔV

Resistance ladder generates 5 reference voltages, Vref, Vref ± ΔV, Vref ± 2ΔV. The value of ΔV can greatly affects the performance of DLDO. If the value of ΔV is too small, it may cause a large fluctuation in the output voltage Vout. Conversely, if the value of ΔV is too large, the transient response time will be longer. Therefore, the value of ΔV should avoid the output voltage from oscillating, which should satisfy the following conditions.

ΔV ≥ max{ΔVstep}

where the ΔVstep is the variation in output voltage caused by turning on or off a PMOS. For this design, the ΔV is set to 10 mV according to results of simulation by HSPICE.

4. Experiments

We have simulated proposed DLDO in SMIC 55 nm by HSPICE. The simulation results are shown as Figure 5. It shows the drop of output voltage Vout when the load current is changed from 10 to 800 uA at a transition time of 40 ns. When the comparator detects the drop of the output voltage, clock frequency and loop gain increase adaptively to accelerate the output voltage into a steady state. After entering the steady state, the ripple controller asserts clock gating signal to turns off the clock of the shift register, reducing the steady state power consumption and supply ripple. The simulation results of load regulation from maximum load 1 mA to minimum load 100 uA at a transition time 1ns is shown in Figure 6. The maximum overshoot voltage is 25 mV. Figure 7 shows simulation results of line regulation from 0.5 to 0.6 V Vin at a trasition time 500 ns. The output Vout has a ripple of 50 mV. Figure 8 shows the simulation results from steady state to tracking state when Vref is changed. The tracking time is 800 ns when Vref change from 0.45 to 0.5 V.

Figure 5. Simulation results of proposed DLDO.

Figure 6. Simulation results of load regulation from maximum load to minimal load.

Figure 7. Simulation results of line regulation from 0.5 to 0.6 V Vin.

Figure 8. Simulation results from steady state to tracking state.

In Table 3, The quiescent current of resistor ladder and comparators is presented.

Table 3. The quiescent current of the resistor ladder and comparators.

Resistor Ladder	Comparators
1 uA @0.5 V	0.62 uA @0.5 V

In Table 4, we present the comparison between several representative DLDOs. Compared with other DLDO, proposed DLDO have better figure of merit (FOM), which is 0.17.

Table 4. Comparison with other works.

	This Work	[13]	[15]	[16]
Process	55 nm	28 nm	65 nm	65 nm
Area (mm2)	0.000503	0.019	0.01	0.0374
Controller	quantized controller with a dead zone	quantized controller with a dead zone	quantized controller with a dead zone	quantized controller
Structure	Adaptive clock	S/R+TSPC	CFT	VCO based ADC
Loop bandwidth control mechanism	Fine-grained Fs scaling, Clock gating	Fs fixed	Coarse-grained Fs scaling	Coarse-grained Fs scaling
Synthesizable	Yes	No	Yes	No
Minimum VIN (V)	0.5	0.6	0.6	0.6
Nominal VOUT (V)	0.45	0.55	0.4	0.4
Max.ILOAD (mA)	1	25	100	100
COUT (nF)	0.0001nF	0.15	1	0.04nF
Min.IQ (uA)	2.3	28	82	100
Peak current efficiency	99.99%	99.96%	99.92%	99.5%
FOM * (ps)	0.17	0.59	0.4	0.19

* $\mathrm{FOM}=\frac{\mathrm{C}\times \Delta {\mathrm{V}}_{\mathrm{OUT}}}{\Delta {\mathrm{I}}_{\mathrm{LOAD}}}\times \frac{{\mathrm{I}}_{\mathrm{Q}}}{\Delta {\mathrm{I}}_{\mathrm{LOAD}}}$ Smaller FOM are better.

5. Conclusions

This paper proposed an all-digital LDO with adaptive clock technique. The sample clock is supplied by an all-digital ring oscillator with a tunable output clock frequency. When output voltage undershoot/overshoot occurs, the sample clock frequency and loop gain are increased adaptively to make the proposed DLDO has better transient response. The proposed DLDO is simulated at SMIC 55 nm with 5.03 e-4 mm2 active area. The simulation results shows that the operating voltage of proposed DLDO can be down to 0.5 V and the peak current efficiency is 99.99%. The transient response time is 500 ns with load step of 10 to 800 uA. The implementation of all-digital ensures that proposed DLDO can be easily transplanted between different processes.