To get a better tradeoff between the transient performance and current efficiency of Digital Low-Dropout(DLDO) regulator, this paper proposes an all-digital Low-Dropout(LDO) regulator with adaptive clock technique. The sample clock is supplied by a proposed digital oscillator (DOSC) whose output frequency can be changed seamlessly. The frequency of sample clock and loop gain boost adaptively when the output voltage undershoot/overshoot is detected. Proposed DLDO integrates a ripple controller to eliminate steady-state supply ripple and reduce steady-state power. The proposed DLDO is simulated at Semiconductor Manufacturing International Corporation (SMIC) 55 nm with 5.03e-4 mm2 active area. The simulation results show that the operating voltage of proposed DLDO can be down to 0.5 V and the peak current efficiency is 99.99%. The measured voltage undershoot is 40 mV and transient response time is 500 ns with load step of 10 to 800 uA.
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