An Optoelectronic CMOS Transimpedance Amplifier Using an FVF-Based Low-Dropout Regulator for PSRR Enhancement
Round 1
Reviewer 1 Report
Comments and Suggestions for AuthorsThis manuscript presents an integrated optoelectronic receiver front-end combining an inverter-based CMOS transimpedance amplifier (TIA) with an on-chip flipped-voltage-follower low-dropout regulator (FVF-LDO) aimed at enhancing power-supply rejection ratio (PSRR). The work incorporates a bandgap reference (BGR) with a 3-bit trimming DAC, a super-source-follower (SSF) assisted LDO architecture, and demonstrates improved PSRR and stable operation under PVT variations through post-layout simulations.
The integration of an on-chip LDO for PSRR improvement in inverter-based TIAs is technically meaningful. However, several important issues limit its current suitability for publication.
1) The manuscript reports only post-layout simulation results without any silicon measurement data. For analog/RF IC designs, especially integrated optical front-ends, measurement validation is typically expected. The absence of measured results significantly weakens the credibility and impact of the work.
2) The individual components, including FVF-based LDO, SSF enhancement, and BGR with trimming DAC, are well established in the literature. The manuscript does not clearly articulate a fundamentally new architectural or theoretical contribution beyond incremental integration. The novelty should be clarified and better positioned with respect to prior work.
3) Although a comparison table is provided, the evaluation is not fully convincing. For example:
- Technologies and photodiode configurations vary significantly.
- No unified figure-of-merit (FoM) is presented.
- PSRR comparison lacks frequency-specific context. A more rigorous and normalized comparison is required.
4) The reported LDO PSRR (~−30 dB) is moderate compared to state-of-the-art designs. While system-level improvement is demonstrated, the manuscript should better contextualize its contribution relative to alternative approaches (e.g., differential architectures or filtering techniques).
5) Please clarify whether the on-chip APD is fabricated or only modeled.
Author Response
1. The manuscript reports only post-layout simulation results without any silicon measurement data. For analog/RF IC designs, especially integrated optical front-ends, measurement validation is typically expected. The absence of measured results significantly weakens the credibility and impact of the work.
-> We are fully aware that silicon measurement results are important for analog/RF IC designs. However, the chip implementation was not ready yet. So, we have conducted extensive post-layout simulations to ensure the reliability and practical feasibility of the proposed design. In particular, the key biasing and supply blocks have been thoroughly verified under comprehensive process, voltage, and temperature (PVT) conditions. For the bandgap reference (BGR), five process corners (SS, TT, FF, SF, FS) were considered, since the reference voltage is sensitive to process variation and device mismatch. For the LDO, three primary process corners (SS, TT, FF) were evaluated along with supply voltage and temperature variations to ensure stable regulation across all conditions. These results would confirm that stable and reliable biasing and supply conditions are maintained under severe PVT variations. Therefore, the combined verification of the biasing circuitry, power regulation, and the TIA would provide strong confidence in the overall system reliability and practical feasibility, even in the absence of silicon measurement data. We authors do hope for a real implementation as a future work.
2. The individual components, including FVF-based LDO, SSF enhancement, and BGR with trimming DAC, are well established in the literature. The manuscript does not clearly articulate a fundamentally new architectural or theoretical contribution beyond incremental integration. The novelty should be clarified and better positioned with respect to prior work.
-> We reckon that the main contribution of this work lies in the system-level design of the optoelectronic receiver against power-supply noise. In conventional designs, each component (e.g. TIA, LDO, and reference circuit) is optimized independently with PSRR improvements addressed at the individual block. However, in a practical optical receiver system, supply noise propagates through multiple paths and directly affects the signal integrity. Therefore, block-level optimization alone might be insufficient to guarantee robust system performance.
In this work, we integrate an on-chip LDO with an inverter-based TIA, in which the impact of supply noise is evaluated by comparing the PSRR characteristic of a conventional TIA with the proposed LDO-integrated receiver, clearly demonstrating significant improvement in the overall power-supply rejection when the LDO-assisted architecture is employed.
3. Although a comparison table is provided, the evaluation is not fully convincing. For example:
- Technologies and photodiode configurations vary significantly.
- No unified figure-of-merit (FoM) is presented.
- PSRR comparison lacks frequency-specific context. A more rigorous and normalized comparison is required.
-> Thank you for the comment. We have revised the manuscript, according to this comment.
(1) Technologies and photodiode configurations vary across prior works, which makes direct comparison inherently challenging. Only a limited number of papers provide sufficient information (such as detailed photodiode configurations and frequency-dependent PSRR characteristics) for consistent comparison. As an example, for prior works where frequency-specific PSRR values were not reported, we have estimated from the published figures and are clearly marked accordingly in the table. Therefore, the revised manuscript would provide more consistent and meaningful evaluation. It should be noted that PSRR has not been a primary design focus in many existing approaches, whereas the proposed design explicitly targets system-level power-supply noise suppression, hence distinguishing it from prior work.
(2) A figure-of-merit (FoM) is introduced to ensure a physically consistent and fair comparison across different works.
(3) The PSRR values are now reported at two frequencies, i.e., 1 kHz and 100 kHz, to capture both low-frequency and mid-frequency behavior. This provides a more complete comparison of supply-noise rejection performance across different designs.
4. The reported LDO PSRR (~−30 dB) is moderate compared to state-of-the-art designs. While system-level improvement is demonstrated, the manuscript should better contextualize its contribution relative to alternative approaches (e.g., differential architectures or filtering techniques).
-> As shown in the table, a design implemented in the same 180-nm technology achieved higher PSRR at the cost of substantially increased power consumption. In contrast, our work focuses on the system-level PSRR improvement with significantly reduced power consumption, highlighting a design tradeoff between PSRR and power efficiency. It is clearly seen that the proposed architecture provides a favorable balance between power consumption and PSRR, which is particularly important for power-constrained optoelectronic receiver applications.
5. Please clarify whether the on-chip APD is fabricated or only modeled.
-> Thank you for the comment. The on-chip APD used in this work is a physically fabricated and experimentally characterized device, which has been previously reported in J.-E. Joo et al., “A CMOS Fully Differential Optoelectronic Receiver for Short-Range LiDAR Sensors”. In this work, the APD is integrated with the proposed receiver front-end, and its characteristics are based on the measured results reported in that study. Therefore, the presented results are obtained by using realistic device-level implementation rather than purely modeled photodiode. This point has been clarified in the revised manuscript.
Author Response File: 
Author Response.pdf
Reviewer 2 Report
Comments and Suggestions for Authors1.The manuscript analyzes only the fast loop, while the system is a dual-loop architecture. The stability of the slow loop is not discussed.
2.While the stability of the error amplifier (EA) under different load conditions is presented, the overall loop stability of the LDO across varying load conditions is not analyzed.
3.The PSRR measurement results are provided; however, it is not specified whether the results correspond to light-load or heavy-load conditions.
3.In Equation (10), the location of the zero is not clearly specified in terms of LHP or RHP conditions, which is a significant gap in the compensation analysis.
4.The simulation conditions for PSRR are not sufficiently described. In particular, when the BGR and LDO use different supplies, this should be clearly explained.
5.Although the paper focuses on the LDO, the comparison table does not include a thorough performance analysis of other LDO designs (e.g., IQ, line regulation, load regulation, etc.).
6.Please add a figure of merit (FOM) in Table 1.
Author Response
1. The manuscript analyzes only the fast loop, while the system is a dual-loop architecture. The stability of the slow loop is not discussed.
-> Thank you for the comment. In the revised manuscript, we have added the frequency response of the slow loop and supplemented the discussion on its role and stability. This revision clarifies that, in the proposed dual-loop architecture, not only the fast loop but also the slow loop operates stably.
2. While the stability of the error amplifier (EA) under different load conditions is presented, the overall loop stability of the LDO across varying load conditions is not analyzed.
-> Thank you for the comment. First, we would like to clarify that the result shown in Fig. 12 of the original manuscript is not the stability analysis of the EA itself, but rather the stability analysis of the fast loop in the proposed FVF-LDO. However, we agree that the meaning of this figure may not have been sufficiently clear in the original version, which may have caused some confusion. Therefore, in the revised manuscript, we have clarified in both the main text and the figure caption that Fig. 13 corresponds to the fast-loop stability of the FVF-LDO. In addition, we have included the stability analysis of the slow loop as well, so that the stability of the proposed dual-loop LDO can be explained more systematically.
3. The PSRR measurement results are provided; however, it is not specified whether the results correspond to light-load or heavy-load conditions.
-> Thank you for the comment. We believe this point may have arisen because the target and condition of each result were not sufficiently distinguished in the original manuscript. Specifically, the PSRR values presented in the table correspond to the system-level PSRR of the TIA combined with the FVF-LDO, rather than the PSRR of the LDO alone. In contrast, the PSR characteristics of the FVF-LDO itself are presented separately in Fig. 15 under light-load and medium-load conditions. In the revised manuscript, we have clarified this distinction in the table description and the main text so that the meaning of each result is more clearly conveyed.
4. In Equation (10), the location of the zero is not clearly specified in terms of LHP or RHP conditions, which is a significant gap in the compensation analysis.
-> Thank you for the comment. As pointed out, the original manuscript did not clearly explain whether the zero derived from Equation (10) is located in the LHP or RHP. In the revised manuscript, we have added further explanation so that the condition determining the zero location and its implication can be more clearly understood.
5. The simulation conditions for PSRR are not sufficiently described. In particular, when the BGR and LDO use different supplies, this should be clearly explained.
-> Thank you for the comment. In the revised manuscript, we have added a more detailed explanation of the simulation conditions. Specifically, the BGR was biased with a constant supply, while the supply ripple was applied only to the LDO supply during the PSRR simulation. This has now been clarified in the revised manuscript.
6. Although the paper focuses on the LDO, the comparison table does not include a thorough performance analysis of other LDO designs (e.g., IQ, line regulation, load regulation, etc.).
-> Thank you for the comment. We agree that metrics such as , line regulation, and load regulation are useful for a comprehensive comparison of standalone LDO designs. However, the purpose of this work is not to position the proposed circuit as a standalone state-of-the-art LDO, but to demonstrate the system-level benefit of integrating the proposed FVF-LDO with the inverter-based TIA for improved PSRR and stable front-end operations. Therefore, the comparison table was intentionally limited to the metrics most relevant to the objective of this work.
7. Please add a figure of merit (FOM) in Table 1.
-> Thank you for the comment. As suggested, a figure of merit (FoM) has been added to Table 1 in the revised manuscript.
Author Response File: Author Response.pdf
Round 2
Reviewer 1 Report
Comments and Suggestions for AuthorsThank you for your revision and modification according to my comments and suggestions.
Reviewer 2 Report
Comments and Suggestions for AuthorsAll reviewer comments have been carefully considered and addressed.
