Improving Hardware Security Through Logic-Probability- Guided Gate Replacement Using Emerging Devices

Abstract

Security threats in the integrated circuit (IC) supply chain are intensifying as demand drives fabrication to off-shore, potentially untrusted foundries. To mitigate theft and reverse engineering, recent work has focused on logic locking, encryption, and camouflaging. This paper introduces a probabilistic logic-driven algorithm that selects optimal locations for polymorphic gate replacement to strengthen circuit protection. Our approach leverages emerging polymorphic devices—namely the Giant Spin-Hall Effect (GSHE) switch, the 5-terminal magnetic domain wall motion (DWM) device, and the threshold-voltage-defined (TVD) switch—to diversify functional behavior and obscure true circuit intent. Evaluated on ISCAS-85 and ISCAS-89 benchmarks under state-of-the-art SAT and AppSAT Attacks, the proposed method substantially increases decryption time while achieving a marked improvement in Output Corruption Rate (OCR) relative to prior techniques. In particular, by deploying the GSHE Switch at the highest-probability nodes, we achieve more than 40% OCR along with strong resilience against SAT and AppSAT Attacks, further demonstrating the effectiveness of the proposed approach as a practical and scalable hardware obfuscation strategy.

1. Introduction

In recent years, there has been a growing concern over the protection of integrated circuits (ICs) across the global supply chain. As chip demand surges, fabrication is increasingly outsourced to off-shore, potentially untrusted foundries, heightening the risk of design theft and reverse engineering. Designs can be identified—for example, transistor types within commercial processors can be inferred [1]—and netlists can be extracted [2], enabling leaks or pirated designs [3]. These threats compromise both the confidentiality of intellectual property (IP) and the integrity of deployed systems. Traditionally, as shown in Figure 1, the design begins in written systemVerilog, describing the hardware. The code is then synthesized in order to create a netlist, i.e., a representation of all connections on the chip. This netlist is valuable—if recreated by a malicious user, the integrity of the chip is lost as the malicious user now has an understanding of the connections and can leak or pirate the design. The netlist is turned into a layout in the style of GDSII, which then is sent to the offshore foundry to be manufactured. The offshore foundry can reverse engineer to discover the netlist, and they can also produce extra as to sell. After manufacturing, the chip is tested to ensure inputs and outputs are correct—this can also lead to reverse engineering. After all this, the final product is received by the end user, but they may not be aware that the chip may have been pirated and stolen.

To address these risks, the community has advanced a spectrum of IP protection techniques. Nevertheless, modern reverse-engineering strategies and solver-based attacks continue to improve in effectiveness and scalability, motivating stronger, more adaptable defenses that raise the difficulty of inferring true circuit intent and recovering keys at scale.

1.1. IP Protection

There are methods already researched to assist in IP protection. Logic Encryption/Logic Locking is used with key inputs—key inputs are exactly as they sound, where the correct logic is only found when the correct key is applied [4,5,6,7,8]. Polymorphic gates expand on this idea—the polymorphic gate is capable of performing multiple boolean functions, and only the key input, known by the designer, is capable of providing the correct functionality of the gate. IC Camouflaging is gate replacement, which will be expanded more in later sections. Splitting the manufacturing process into the Front End of Line (FEOL) layers and the Back End of Line (BEOL) layers. The FEOL layers, which is primarily transistor fabrication and some earlier metal layers, is manufactured offshore, while the BEOL layers, which are primarily metal layers, are manufactured onshore [9]. These are just a few examples of IP protection and the recent research performed on this subject.

1.2. Emerging Devices

A wide range of emerging device technologies has been explored for enhancing logic encryption. Notable examples include polymorphic devices such as the GSHE Switch [10], DWM Switch [11,12], and TVD [13]. Additional approaches leverage memristor-based encryption, as demonstrated in the works of Shirinzadeh et al. [14] and Kvatinsky et al. [15]. Other hardware-centric security primitives, including Physically Unclonable Functions (PUFs) [16,17,18] and Look-Up Tables (LUTs) [19,20], have also been employed to strengthen design obfuscation. Collectively, these emerging technologies offer diverse opportunities to enhance logic encryption and support robust intellectual property (IP) protection.

1.3. Camouflaging Technique

We incorporate GSHE, DWM, and TVD polymorphic gates in our design. These three device technologies were selected due to their complementary switching mechanisms and their demonstrated potential to enhance attack resiliency. It is important to know that these methodologies are not yet fully compatible with industry, as Han et al. notes [21]. Thus, an encouraging and emerging topic is to introduce EDA-compatible tools [22]. The proposed Hybrid Shielding framework operates at the post-synthesis netlist level and is compatible with standard industrial RTL-to-GDSII flows without requiring modifications to commercial EDA tools; while experimental validation was conducted using a commercial synthesis environment, full-scale industrial deployment and sign-off validation remain part of future work.

Modern reverse-engineering and machine-learning-assisted attacks have become increasingly sophisticated and capable of analyzing complex hardware designs. In this context, polymorphism plays a crucial role by introducing functional ambiguity at the device level. Specifically, polymorphic gates can exhibit different functionalities depending on the applied control conditions, making it significantly more challenging for an adversary to determine the actual behavior of the circuit. As a result, even with advanced analysis techniques or machine-learning-based approaches, accurately inferring the true functionality of individual gates and the overall design becomes substantially more difficult. This inherent ambiguity strengthens the resilience of the system against reverse-engineering efforts and helps protect the underlying intellectual property [4].

Building on these foundations, this paper presents a novel algorithm based on logic probability that determines the optimal gates chosen for polymorphic gate replacement. By integrating GSHE, DWM, and TVD devices—each offering distinct polymorphic characteristics such as magneto-spintronic switching (GSHE), domain wall motion-based configurability (DWM), and threshold-voltage-dependent functionality (TVD)—we create a heterogeneous polymorphic layer that maximizes uncertainty for attackers while maintaining circuit-level robustness. We evaluate our approach using the ISCAS 1985 benchmarks against SAT and AppSAT Attacks, demonstrating a strong increase in decryption time and a significant improvement in Output Corruption Rate (OCR) compared to previous research.

The paper is organized in the following format: Section 1 is the Introduction. Section 2 is the background and motivation, describing prior research and ideas. Section 3 is our proposed method. Section 4 is the experiments, along with a way for a reader of this paper to reproduce these experiments. Section 5 is the results and discussion of the results. Lastly, Section 6 is the conclusion.

2. Background and Motivation

Over the past decade, both industry and academia have intensified efforts to secure integrated circuits (ICs) amid escalating supply-chain threats. As fabrication and test have become more globally distributed, the community has developed—and systematically evaluated—security tools that expose vulnerabilities and guide the design of stronger defenses. This section reviews key attack methodologies that catalyzed progress in logic encryption and camouflaging, and motivates our focus on polymorphic devices as a path toward resilient protection.

2.1. Background

A pronounced “attack–defense” cycle has shaped IC security: new obfuscation and locking schemes have been met by increasingly capable deobfuscation tools. The Boolean Satisfiability Attack (SAT Attack), introduced in 2015 [23], demonstrated that many contemporary logic-locking schemes could be efficiently compromised. Building on this, the Approximate SAT Attack (AppSAT), proposed in 2017 [24], further expanded the practical reach of solver-based attacks by targeting approximate keys and outputs.

2.1.1. SAT Attack

The SAT Attack (also referred to as the SAT Tool) iteratively identifies distinguishing input patterns by querying a functional oracle and pruning incorrect keys until a single valid key remains. In practice, this approach defeated most early circuit encryption attempts, highlighting the need for stronger protection mechanisms. Subsequent research introduced both enhanced attack variants—such as AppSAT by Shamsi et al. [24] and IcySAT by Shamsi et al. [25]—as well as SAT-resistant locking schemes, including SARLock by Yasin et al. [26], to counter solver-based deobfuscation. Operationally, the SAT Tool seeks consistent input–output behavior; when successful, it returns the recovered key. When the SAT Tool runs for more than two days, it is considered unable to solve the circuit.

2.1.2. AppSAT Attack

The AppSAT Attack (or AppSAT Tool) extends SAT-based methods to recover approximate keys and outputs, often with greater practical effectiveness than exact SAT. Consequently, we define an inability to solve a circuit as taking more than one day. AppSAT’s key parameters include the iterations between sampling (a), the number of sampling queries (q), and the settlement threshold (S). Every a iterations, AppSAT issues q randomized sampling queries; if the number of inputs tested remains insufficient, the settlement count (initialized to 0) is incremented. Once the settlement count reaches S, the tool returns an approximated key [26,27].

2.2. Motivation

Several hardware security techniques have been proposed to protect integrated circuits against reverse engineering and SAT-based attacks. Patnaik et al. [28] introduced polymorphic logic based on spin–orbit torque (SOT) devices for hardware security, demonstrating how device-level polymorphism can obscure circuit functionality and increase resistance to structural analysis. However, their approach primarily focuses on device-level polymorphic behavior and does not incorporate a hybrid logic encryption framework that combines multiple locking mechanisms to further strengthen security. SARLock, proposed by Yasin et al. [26], introduces a SAT-resistant locking technique based on a point-function structure that significantly increases the number of iterations required by SAT Attacks. Nevertheless, SARLock typically results in very low Output Corruption Rates (OCRs), meaning that many incorrect keys still produce outputs that are largely correct, which limits the practical strength of the protection. More recent work such as Hybrid Shielding by Saxena et al. [4] improves the OCR compared to several earlier logic-locking schemes by combining different protection strategies. However, that approach relies on identifying and protecting sensitive nodes within the circuit, which can be a tedious and design-dependent process. In contrast, the approach presented in this work focuses on further improving the achievable OCR while employing a simpler and more systematic gate-selection strategy, avoiding the need for extensive sensitive-node analysis and making the method easier to integrate into practical design flows.

Solver-driven attacks such as SAT and AppSAT exploit the deterministic, fixed functionality of conventional gates and structural regularities in netlists, rapidly pruning candidate keys using distinguishing input patterns. To disrupt this process, our research requires polymorphic gates that introduce per-gate functional ambiguity and expand the effective key space at the device level. By enabling multiple Boolean behaviors within the same physical footprint—selectable through designer-known configuration inputs—polymorphic gates degrade an attacker’s ability to infer true circuit intent from layout or test observations, reduce the efficacy of oracle-guided query strategies, and hinder feature extraction for machine-learning-assisted deobfuscation. Moreover, polymorphism can create equivalence classes of keys and behaviors that yield indistinguishable outputs over practical query budgets, thereby increasing decryption time and improving output corruption for incorrect keys, all while maintaining compatibility with standard design flows and acceptable overheads. In this work, we therefore explored three complementary polymorphic technologies—the GSHE Switch, the DWM Device, and the TVD Switch—to diversify gate-level behavior, strengthen resilience against solver-based and reverse-engineering attacks, and preserve circuit performance and practicality.

2.2.1. Comparison with Probability-Based Gate Selection Approaches

Existing methods such as ProbLock [29] leverage logical probability primarily as a filtering mechanism to guide gate selection in logic locking. These approaches focus on identifying candidate gates that maximize locking effectiveness within a conventional logic-locking framework. Probability analysis in these methods is generally applied to prioritize gates for insertion but does not integrate additional functional transformations or encryption strategies.

In contrast, the proposed framework employs probability analysis as part of a broader strategy that combines polymorphic gate insertion and hybrid encryption. This integration enhances functional ambiguity and improves the Output Corruption Rate (OCR). Unlike prior methods, our approach avoids complex structural analysis, such as identifying sensitive nodes or performing extensive structural filtering, and instead relies on a straightforward probability-driven selection mechanism that can be systematically applied across the circuit. This design choice enables a practical and effective combination of polymorphic behavior and logic encryption, emphasizing OCR improvement while maintaining implementation simplicity.

2.2.2. The GSHE Switch

The GSHE Switch is a two-magnet dipolar coupling device [30]. Ref. [31] first proposed using it for boolean logic, and GSHE was shown to be compatible with CMOS by Zhang et al. [31], while it is known to be CMOS compatible, there are some integration issues regarding spin diffusion and integration density [32]. As shown in Figure 2, the leftmost layer consists of the GSHE material, commonly silicon or another semiconductor-based material [10]. The free magnet layer next is W (Write) while the rightmost layer is a free magnet layer R (Read), both being nanomagnets. In between there are two ferromagnetic layers in green, where one is positive current (+I, Logic 1) and the other is negative current (−I, Logic 0). The black arrow represents a charge current and the yellow arrows represent the transverse direction to show the accumulation of spin.

2.2.3. The 5-Terminal Magnetic Domain Wall Motion Device

The 5-Terminal Magnetic Domain Wall Device, known as the DWM Device, combines a domain wall motion component with three magnetic tunnel junctions. Each junction comprises two ferromagnetic layers separated by a tunnel barrier [11,12]. This architecture enables configurable behavior suitable for polymorphic logic, as shown in Figure 3.

2.2.4. The Threshold-Voltage-Defined Switch

The Threshold-Voltage-Defined Switch (TVD Switch) can implement multiple Boolean functions by exploiting threshold-voltage-dependent configurations [13]. As [33] demonstrates, simply adjusting an NMOS transistor’s gate voltage bias enables different functional behaviors, making TVD an effective polymorphic primitive for encryption and camouflaging. The visual representation is shown in Figure 4.

3. Proposed Method

We integrate our gate-selection algorithm with polymorphic gates to realize a resilient encryption framework that supports fine-grained, reconfigurable logic locking and high key entropy.

3.1. GSHE Switch

The GSHE Switch can be represented as a 16 × 1 multiplexer (MUX) as shown in Figure 5. Dynamic A and Dynamic B use what is known as HTrigger [4], which for our method is a random primary input. RNG is a random binary 0 or 1. The MUX table can be seen in

Table 1. The GSHE Switch, DWM Device, and TVD Switch key inputs.

Functionality	GSHE Key	DWM Key	TVD Key
a NAND b	XX111111	111	000
a AND b	XX111110	110	001
a NOR b	XX111011	011	011
a OR b	XX111010	010	010
a XOR b	XX001111	001	101
a XNOR b	XX001110	000	100
NOT a	XX001011	100	N/A
BUF a	XX001010	N/A	N/A
a AND NOT b	XX101111	N/A	N/A
NOT a AND b	XX101110	N/A	N/A
a OR NOT b	XX101011	N/A	N/A
NOT a OR b	XX101010	N/A	N/A
NOT b	XX011111	N/A	N/A
BUF b	XX011110	N/A	N/A
1 (True)	XX011011	N/A	N/A
0 (False)	XX011010	N/A	N/A

N/A means the device does not have this functionality.

, which shows the inputs and keys. The first two key inputs, k1 and k2, are crossed out—this is because they are not necessary to determine the specific functionality of the device; rather, they are necessary in determining the input value of either Dynamic A or Dynamic B. In our construction, the 16-way selection enables a rich configuration space that couples the HTrigger and RNG sources of randomness with the key-controlled routing inside the MUX. This combination yields a large functional repertoire and elevates the effective key entropy, improving resistance to structural inference and brute-force strategies. Moreover, the GSHE-based switch cleanly interfaces with our gate-selection algorithm, allowing adaptive instantiation of Boolean behaviors while preserving timing closure and minimizing area overhead.

The 5T Domain Wall Magnet Device, named the DWM Device, also has polymorphic properties—this can be represented by an 8 × 1 MUX, shown in Figure 6. The key inputs are shown in Table 1. The DWM configuration space is therefore narrower than GSHE’s, providing eight selectable behaviors under a given key schedule; while the device supports efficient reconfiguration, its reduced fan-in and smaller key space limit the number of distinct logic functions realizable per instance, which in turn lowers the achievable obfuscation density for a fixed gate budget.

However, the Threshold-Voltage-Defined Switch, named the TVD Switch, has polymorphic properties and can offer 6 functionalities. This can be represented by an 8 × 1 MUX, shown in Figure 7. The key inputs are shown in Table 1. The TVD approach benefits from CMOS compatibility, but the smaller functional set and sensitivity to threshold variations constrain its role in high-entropy logic locking. In practice, the reduced number of behaviors per switch complicates the design of uniformly strong key schedules across heterogeneous logic blocks.

Finally, GSHE is selected as the polymorphic gate for this research because it offers superior configurability (16 × 1 selection versus 8 × 1), higher effective key entropy through the joint use of HTrigger [4] and RNG, and seamless integration with our gate-selection algorithm, while DWM can support up to 16 logic functions [11,12], we selected the GSHE Switch as it has superior CMOS capabilities and more favorable PPA trade-offs, making it far more practical for scalable integration. These attributes enable a broader set of realizable Boolean functions per gate, deeper obfuscation layers without excessive area or timing penalties, and stronger resistance to structural and key-recovery attacks compared with the DWM Device and the TVD Switch.

3.2. Key Distribution

There are three sets of keys, $S1$, $S2$, and $S3$. $S1$ is used for the Reinstate Block, $S2$ for the SAT–Resilient Block, and $S3$ for the polymorphic gates. The value of $S1$ depends on the type of Reinstate Block; for a CMOS implementation (as used in [4]) only 1 key input is necessary. In our method, we use a GSHE-based Reinstate Block and add a 9th key input as the B input, so $S1 = 9$. $S2$ requires one key input per polymorphic gate; with 45 polymorphic gates, $S2 = 45$. $S3$ equals the number of polymorphic gates times the key inputs per gate: using 45 GSHE Switches with 8 keys each gives $S3 = 45 · 8 = 360$. If DWM switches (3 keys each) were used instead, $S3$ would be 135. The total number of key inputs is $S1 + S2 + S3$, which for our configuration is $9 + 45 + 360 = 414$.

Limiting the number of keys is not the goal of this work; if that were desired, keys can be shared as in [4]. Therefore, we used 360 key inputs for $S3$ instead of applying key-sharing. This does not pose a problem, and key-sharing can be employed later to reduce the total number of keys if needed. Keys are akin to transistors; if a 5000 gate circuit includes only 20,000 or 30,000 transistors, our keys make up only 1–2% of the total transistor count. For a design with one million transistors, the keys would take up an insignificant number of transistors—less than 0.1%.

3.3. Gate Replacement Algorithm

Algorithm 1 computes probabilities across the circuit. Primary inputs are initialized with P(0) = P(1) = 0.5 (each logic value has a 50% probability). Each gate’s output probability is then computed using Algorithm 1 according to the gate type. These calculations are inspired by Brkic et al. [34], Qian et al. [35], and Parker and McCluskey [36]. Gates are ranked by their output probability and grouped as follows: “highest” is the top 45 gates with the largest P(1) (smallest P(0)); “lowest” is the top 45 with the largest P(0) (smallest P(1)); “50/50” consists of the top 22 or 23 gates by P(1) and the top 22 or 23 by P(0); and “random” is selected uniformly at random. The Python-to-LaTeX conversion was produced with the help of generative AI (Claude Sonnet 4.5), and the Python 3.11.4. code is provided [37]. The probability calculations are performed as follows:

3.3.1. BUF

Buffer (BUF) gates have a single input and directly propagate the input probabilities to the output without modification. In other words, the output probabilities are identical to the input probabilities. For instance, if the probability of a logic 1 is 70% (i.e., $P\left(1\right) = 0.7$), then the probability of a logic 0 is 30% (i.e., $P\left(0\right) = 0.3$).

Algorithm 1 Gate Selection

1: Require: Netlist file, selection type $t\in \{\mathrm{highest},\mathrm{lowest},50/50,\mathrm{random}\}$   2: Ensure: List of 45 selected gate names   3: Parse netlist to extract inputs I, outputs O, and gates G   4: Build dependency graph and perform topological sort on G   5: Initialize $P(i=1)=0.5$ for all $i\in I$   6: for each gate $g\in G$ in topological order:   7:    if g is BUF:       $P(g=1)\leftarrow P(x_1=1)$   8:    elseif g is NOT:       $P(g=1)\leftarrow 1 - P(x_1=1)$   9:    elseif g is AND:       $P(g=1)\leftarrow {\prod }_{i=1}^{n}P(x_i=1)$ 10:    elseif g is NAND:       $P(g=1)\leftarrow 1 - {\prod }_{i=1}^{n}P(x_i=1)$ 11:    elseif g is OR:       $P(g=1)\leftarrow 1 - {\prod }_{i=1}^{n}P(x_i=0)$ 12:    elseif g is NOR:       $P(g=1)\leftarrow {\prod }_{i=1}^{n}P(x_i=0)$ 13:    elseif g is XOR:       $P(g=1)={\sum }_{\begin{array}{c}S\subseteq \{1,\dots ,n\}\\ \left|S\right|\mathrm{odd}\end{array}}\left({\prod }_{i\in S}P(x_i=1){\prod }_{j\notin S}P(x_j=0)\right)$ 14:    elseif g is XNOR:       $P(g=1)={\sum }_{\begin{array}{c}S\subseteq \{1,\dots ,n\}\\ \left|S\right|\mathrm{even}\end{array}}\left({\prod }_{i\in S}P(x_i=1){\prod }_{j\notin S}P(x_j=0)\right)$ 15: Filter G to internal 2-input gates $C\leftarrow G\setminus (I\cup O)$ 16: if $t=″\mathrm{highest}″$:    Select top 45 gates from C by $P(g=1)$ 17: elseif $t=″\mathrm{lowest}″$:    Select top 45 gates from C by $P(g=0)$ 18: elseif $t=″50/50″$:    $N\leftarrow$ random choice from $\{22,23\}$    Select N gates by highest $P(g=1)$ and $45 - N$ by highest $P(g=0)$ 19: elseif $t=″\mathrm{random}″$:    Select 45 random gates from C 20: end

3.3.2. NOT

NOT gates also have a single input, but they invert the input probabilities at the output. Specifically, the probability of a logic 1 at the output equals the probability of a logic 0 at the input, and vice versa. For example, if the input probabilities are $P\left(1\right) = 0.7$ and $P\left(0\right) = 0.3$, then the output probabilities become $P\left(1\right) = 0.3$ and $P\left(0\right) = 0.7$.

3.3.3. AND

AND gates support two or more inputs. The output probability of logic 1, $P\left(1\right)$, is obtained by multiplying the $P\left(1\right)$ values of all inputs. For example, consider three inputs A, B, and C with probabilities $P_A\left(1\right) = 0.4$, $P_B\left(1\right) = 0.2$, and $P_C\left(1\right) = 0.8$. The resulting output probability is $P_{total}\left(1\right) = P_A\left(1\right) · P_B\left(1\right) · P_C\left(1\right) = 0.4 · 0.2 · 0.8=0.064$, or 6.4%. Since $P\left(0\right) = 1 - P\left(1\right)$, the output probability of logic 0 is $P_{total}\left(0\right) = 1 - 0.064=0.936$, or 93.6%.

3.3.4. NAND

NAND gates also have two or more inputs and produce the logical complement of an AND gate. Thus, if an AND gate yields $P\left(1\right) = 0.064$ and $P\left(0\right) = 0.936$, the corresponding NAND gate produces $P\left(1\right) = 0.936$ and $P\left(0\right) = 0.064$. The probability calculations are identical to those of the AND gate, except that the final output probabilities are swapped.

3.3.5. OR

OR gates have two or more inputs. The output probability of logic 0 is computed by multiplying the input probabilities of logic 0. The probability of logic 1 is obtained as the complement of this value. As an example, consider three inputs A, B, and C with probabilities $P_A\left(0\right) = 1$, $P_B\left(0\right) = 0.9$, and $P_C\left(0\right) = 0.1$. The output probability of logic 0 is $P_{total}\left(0\right) = P_A\left(0\right) · P_B\left(0\right) · P_C\left(0\right) = 1 · 0.9 · 0.1 = 0.09$, or 9%. Consequently, the probability of logic 1 is $P_{total}\left(1\right) = 1 - 0.09 = 0.91$, or 91%.

3.3.6. NOR

NOR gates have two or more inputs and implement the logical complement of an OR gate. Therefore, if the OR gate produces $P\left(0\right) = 0.09$ and $P\left(1\right) = 0.91$, the corresponding NOR gate produces $P\left(0\right) = 0.91$ and $P\left(1\right) = 0.09$. The probability computation follows the same process as the OR gate, followed by complementing the resulting output probability.

3.3.7. XOR

XOR gates support two or more inputs. The computation iterates over all possible input combinations from 0 to $2^n - 1$, where n is the number of inputs. For each combination, the algorithm checks whether the number of logic 1 s in the binary representation is odd. XOR outputs a logic 1 when an odd number of inputs are 1. For every such valid combination, the corresponding input probabilities are multiplied, and all resulting values are summed to obtain $P_{total}\left(1\right)$.

For example, consider two inputs X and Y with probabilities $P_X\left(1\right) = 0.6$, $P_X\left(0\right) = 0.4$, $P_Y\left(1\right) = 0.1$, and $P_y\left(0\right) = 0.9$. There are two cases with odd parity: $(X = 1,Y = 0)$ and $(X = 0,Y = 1)$. For the first case, $P_1\left(1\right) = P_X\left(1\right) · P_Y\left(0\right) = 0.6 · 0.9 = 0.54$. For the second case, $P_2\left(1\right) = P_X\left(0\right) · P_Y\left(1\right) = 0.4 · 0.1 = 0.04$. Summing these values gives $P_{total}\left(1\right) = 0.54 + 0.04 = 0.58$, or 58%. Accordingly, $P\left(0\right) = 1 - 0.58 = 0.42$, or 42%.

3.3.8. XNOR

XNOR gates have two or more inputs and operate similarly to XOR gates, except that the algorithm checks for even parity in the number of logic 1 s. For each input combination with an even number of 1s, the corresponding probabilities are multiplied and summed to compute $P_{total}\left(1\right)$.

For example, consider two inputs X and Y with probabilities $P_X\left(1\right) = 0.3$, $P_X\left(0\right) = 0.7$, $P_Y\left(1\right) = 0.65$, and $P_y\left(0\right) = 0.35$. The two even-parity cases are  $(X = 0,Y = 0)$ and $(X = 1,Y = 1)$. For the first case, $P_1\left(1\right) = P_X\left(0\right) · P_Y\left(0\right) = 0.7 · 0.35 = 0.245$. For the second case, $P_2\left(1\right) = P_X\left(1\right) · P_Y\left(1\right) = 0.3 · 0.65 = 0.195$. Adding these yields $P_{total}\left(1\right) = 0.245 + 0.195 = 0.44$, or 44%. Consequently, $P\left(0\right) = 1 - 0.44 = 0.56$, or 56%.

3.4. Logic Encryption Method

We adopt a logic encryption scheme inspired by [4], retaining all components except the Internal State Block, which is unnecessary for our purposes. The contrast between the two designs is illustrated in Figure 8 and Figure 9.

3.4.1. The SAT–Resilient Block

After substituting polymorphic gates, each polymorphic gate’s output is routed to its own 2-input XOR gate, with the first input being the polymorphic output and the second a key input. The outputs of all XOR gates are then combined with an AND, completing the SAT–Resilient Block.

3.4.2. The Reinstate Block

The Reinstate Block restores the intended output behavior. In prior research such as [4,5], it is implemented as a CMOS logic gate, commonly an AND or OR. In our encryption, we instead incorporate an additional GSHE Switch as the Reinstate Block itself, substantially increasing encryption strength and corruptibility; while the RNG input of the Reinstate Block introduces inherent randomness as shown in Section 4, if the first two keys, k1 and k2, are known, you can choose your Dynamic A or Dynamic B values.

3.5. Proposed Method

To realize strong encryption, we proceed in several steps. First, we select the gates to be replaced using the gate replacement algorithm, choosing among highest, lowest, 50/50, or randomly selected gates. Once identified, these gates are replaced with our chosen polymorphic gate. We may employ a 16-function gate, such as the GSHE Switch, or 7- or 6-function gates that emulate the DWM and TVD Switches, respectively. The new polymorphic gates continue to drive their original destinations and also feed the SAT–Resilient Block. For each output designated for obfuscation, the signal is sent to both the Reinstate Block and a new XOR gate. The output of the SAT–Resilient Block is applied to this XOR gate, and the result is then XOR’d with the output of the Reinstate Block to produce the new, obfuscated output. A block diagram for clarity is shown in Figure 10.

4. Experiments

This section outlines our experimental methodology, expands on the tools employed, explains how to reproduce our experiments, and defines the basis of our reported results.

For consistency across benchmarks, a fixed budget of 45 gate replacements was used in all experiments. This value was selected to provide a meaningful security perturbation while maintaining functional integrity and avoiding excessive structural modification. The use of a fixed replacement budget ensures fair cross-benchmark comparison of OCR and SAT/AppSAT resilience under identical modification constraints. The selection of 45 polymorphic gates is also consistent with configurations adopted in prior studies. Earlier works such as ISPLock [7] and Hybrid Shielding [4] have demonstrated that increasing the number of polymorphic gates from smaller values (e.g., 30) to around 45 leads to a noticeable improvement in resilience against SAT-based and related attacks while keeping the implementation overhead manageable. Based on these findings, the value of 45 was chosen as a practical baseline that provides a balanced trade-off between security enhancement and structural overhead, while allowing meaningful comparison with previously reported results.

4.1. Setup and Reproducibility

All tests were executed on an i7-1355U with 32GB RAM. Our repository contains many python files as from [37]. There are two separate programs in the repository. The first generates the benchmark used by the SAT Tool, with parameters including the benchmark name, the set of gates to be replaced (as determined by the probability algorithm), and the replacement type (highest probability, lowest probability, 50/50, or random). You can then run the SAT Tool by comparing the generated benchmark with the original, unencrypted benchmark. The second program produces verilog code and test bench code, to be used with the simulator icarus Verilog [38]. There is an additional text file that includes icarus Verilog code. We used benchmarks from the ISCAS ‘85 [39] group, excluding c17 due to its small size, and we also used two benchmarks from ISCAS ’89 [40]: s13207 and s38584. We chose to obfuscate a random 50% of primary outputs. For smaller circuits such as c432, which has 7 primary outputs, there is little variation in the selected outputs. For larger circuits such as c7552, which has 107 primary outputs, the selection exhibits greater variation.

4.2. SAT Tool

The SAT Tool, also known as the SAT Attack, attempts to solve the circuit [23]. It takes two files as input: the original circuit in the .bench format and the encrypted circuit in the .bench format. We have a python program as per [37] that incorporates polymorphic gates based on the chosen gates and the type of polymorphic gates. A strong circuit can withstand the SAT Attack for over 2 days, which we demonstrate by showing SAT Attack results from our encrypted circuits.

4.3. Output Corruption Rate

Output Corruption Rate (OCR) measures the percentage of outputs that are corrupted. It is defined by the following equation as described in [41]:

$$OCR = \left(1/M\right)\times \sum _{i = 1}^M\left(C_i/P\right)$$

In our experiments we define M as 10,000, corresponding to 10,000 different cases.

Given the inherent randomness of Htrigger, RNG, output gate selection, etc., we evaluate each case 10 times and report the average. To compute the average OCR for each test type, we take the mean across all benchmarks.

4.4. AppSAT Pass/Fail

To assess the effectiveness of AppSAT, we evaluate the OCR using the key provided by the attack. The AppSAT Tool is included in the SAT Tool package. As per [24], we use the following parameters for our tests: a (iterations between sampling) is 12, q (number of sampling queries) is 50, and S (settlement threshold) is 5.

The AppSAT Tool performs approximate decryption; consequently, the key it outputs may not be the true key held by the designer. We take the approximated key returned by AppSAT, supply it to icarus Verilog, and compute the resulting OCR at the circuit output. If the OCR is greater than 0%, the key provided by AppSAT is not fully accurate, and the circuit is considered to have resisted the AppSAT Attack. Conversely, if the key from AppSAT yields 0% OCR, the circuit fails the AppSAT Attack, as this indicates that the correct key has been recovered.

We set 0% OCR as the threshold because the Reinstate Block is implemented using a GSHE Switch that incorporates inherent randomness, which can corrupt up to 50% of the outputs under incorrect key conditions. Therefore, an OCR greater than 0% implies that the AppSAT-derived key is incorrect. The randomness originates from the RNG input to Dynamic A or Dynamic B; however, this effect can be bypassed if the correct k1/k2 values are known, as discussed in Section 3.

To evaluate AppSAT, we follow the same OCR computation procedure described earlier, except that instead of applying a random key input, we use the key returned by AppSAT. Alternatively, if AppSAT fails to produce a valid key within 24 h, we denote the result as TIMEOUT and mark the test as passed, indicating that the encrypted circuit survived the AppSAT Attack. The results are presented in Table 8.

4.5. PPA Overhead

Power, Performance, and Area (PPA) overheads are necessary tools for analysis of polymorphic gates. It describes three key factors when looking at device replacement: power, delay, and area. When replacing logic gates with the GSHE Switch, it is important to consider the changes in power, delay, and area across the circuit.

The PPA discussion has already been addressed in prior work such as [4]; therefore, we do not repeat the full analysis here. However, the PPA data for the GSHE Switch is provided in Table 9. PPA Overhead is an essential metric for evaluating polymorphic gates, as it captures three key factors in device replacement analysis: power, delay, and area. When replacing conventional logic gates with the GSHE Switch, it is necessary to carefully assess the resulting variations in these metrics at the circuit level.

As shown in Table 9, the GSHE Switch [28] demonstrates advantages over 15 nm [42] and 45 nm [43] CMOS gates in certain PPA aspects, although it exhibits a significantly higher delay. This delay penalty limits large-scale substitution; while the reported values correspond to an isolated gate, the delay impact accumulates with increasing circuit complexity. Consequently, replacing all gates with GSHE Switches is not a viable design option.

5. Results and Discussion

The comparative analysis presented in this section focuses on logic-locking and cloaking methodologies that are directly comparable in terms of threat model, evaluation metrics (e.g., OCR), and SAT/AppSAT-based adversarial analysis; while Section 1.2 discusses a broader range of emerging security primitives—including memristor-based encryption, PUF-based approaches, and LUT-based mechanisms—these techniques target different security objectives and are evaluated under different performance metrics. Therefore, to ensure methodological consistency and fairness, the comparison in Tables 10 and 11 is limited to works that report SAT-based resilience and OCR metrics under similar benchmark settings. We present results from the SAT Tool, AppSAT Tool, and OCR computations, compare them against prior work, and interpret the factors underlying the observed performance.

5.1. Results

We compiled multiple tables to summarize the outcomes of our algorithm.

Table 2. The GSHE Switch OCR values with standard deviation for all four types of tests.

Benchmark	Highest Probability OCR (%)	Lowest Probability OCR (%)	50/50 Probability OCR (%)	Random Probability OCR (%)
c432	37.39 $\sigma$ 4.92	39.05 $\sigma$ 5.89	30.23 $\sigma$ 0.53	36.05 $\sigma$ 9.67
c499	35.06 $\sigma$ 0.19	55.46 $\sigma$ 0.15	48.45 $\sigma$ 3.10	44.24 $\sigma$ 3.19
c880	37.30 $\sigma$ 2.84	34.89 $\sigma$ 0.17	37.89 $\sigma$ 2.29	36.75 $\sigma$ 2.27
c1355	52.08 $\sigma$ 0.09	55.50 $\sigma$ 0.12	49.17 $\sigma$ 2.41	40.82 $\sigma$ 3.43
c1908	49.61 $\sigma$ 4.16	39.19 $\sigma$ 1.79	50.66 $\sigma$ 2.88	37.64 $\sigma$ 3.01
c2670	35.00 $\sigma$ 0.41	35.67 $\sigma$ 1.18	36.22 $\sigma$ 1.31	35.82 $\sigma$ 1.64
c3540	37.15 $\sigma$ 2.85	38.53 $\sigma$ 3.00	37.89 $\sigma$ 2.64	39.94 $\sigma$ 2.51
c5315	35.35 $\sigma$ 0.38	36.24 $\sigma$ 0.95	35.29 $\sigma$ 0.64	36.14 $\sigma$ 0.74
c6288	48.34 $\sigma$ 1.10	44.13 $\sigma$ 2.68	45.08 $\sigma$ 2.79	45.59 $\sigma$ 1.85
c7552	36.89 $\sigma$ 1.42	38.66 $\sigma$ 1.71	36.96 $\sigma$ 1.43	36.87 $\sigma$ 1.21
s13207	36.55 $\sigma$ 1.00	34.95 $\sigma$ 0.35	34.76 $\sigma$ 0.23	35.81 $\sigma$ 0.86
s38584	51.54 $\sigma$ 1.04	36.15 $\sigma$ 0.45	36.46 $\sigma$ 0.63	36.77 $\sigma$ 1.06
Average	41.02 $\sigma$ 1.70	40.70 $\sigma$ 1.53	39.92 $\sigma$ 1.74	38.54 $\sigma$ 2.62

reports OCR across all benchmarks for the GSHE Switch; similarly,

Table 3. The DWM Switch OCR values with standard deviation for all four types of tests.

Benchmark	Highest Probability OCR (%)	Lowest Probability OCR (%)	50/50 Probability OCR (%)	Random Probability OCR (%)
c432	44.76 $\sigma$ 6.65	35.07 $\sigma$ 10.85	29.94 $\sigma$ 0.18	35.49 $\sigma$ 6.66
c499	35.03 $\sigma$ 0.17	57.52 $\sigma$ 0.13	51.84 $\sigma$ 5.76	47.22 $\sigma$ 4.37
c880	37.71 $\sigma$ 2.09	34.84 $\sigma$ 0.20	38.15 $\sigma$ 2.12	37.14 $\sigma$ 2.98
c1355	56.32 $\sigma$ 0.61	57.47 $\sigma$ 0.09	50.17 $\sigma$ 4.54	41.69 $\sigma$ 4.82
c1908	46.22 $\sigma$ 2.97	39.02 $\sigma$ 1.51	47.92 $\sigma$ 2.99	37.35 $\sigma$ 2.03
c2670	35.17 $\sigma$ 0.50	35.91 $\sigma$ 1.03	36.48 $\sigma$ 0.86	36.68 $\sigma$ 2.32
c3540	40.84 $\sigma$ 4.22	35.41 $\sigma$ 2.34	39.30 $\sigma$ 2.03	40.22 $\sigma$ 2.19
c5315	35.33 $\sigma$ 0.39	36.44 $\sigma$ 0.86	35.97 $\sigma$ 0.78	35.73 $\sigma$ 0.75
c6288	45.00 $\sigma$ 0.93	43.34 $\sigma$ 2.28	45.18 $\sigma$ 1.41	46.95 $\sigma$ 2.44
c7552	37.01 $\sigma$ 1.12	36.82 $\sigma$ 0.97	37.18 $\sigma$ 1.00	36.87 $\sigma$ 1.07
s13207	35.79 $\sigma$ 1.07	34.89 $\sigma$ 0.32	34.75 $\sigma$ 0.22	35.40 $\sigma$ 0.71
s38584	36.44 $\sigma$ 1.44	36.25 $\sigma$ 0.54	37.36 $\sigma$ 0.33	37.76 $\sigma$ 1.16
Average	40.47 $\sigma$ 1.85	40.25 $\sigma$ 1.87	40.35 $\sigma$ 1.85	39.04 $\sigma$ 2.63

and

Table 4. The TVD Switch OCR values with standard deviation for all four types of tests.

Benchmark	Highest Probability OCR (%)	Lowest Probability OCR (%)	50/50 Probability OCR (%)	Random Probability OCR (%)
c432	44.74 $\sigma$ 10.67	43.04 $\sigma$ 15.76	29.89 $\sigma$ 0.11	34.98 $\sigma$ 8.05
c499	34.89 $\sigma$ 0.20	55.64 $\sigma$ 0.16	50.07 $\sigma$ 3.43	45.53 $\sigma$ 5.69
c880	37.72 $\sigma$ 1.81	34.84 $\sigma$ 0.23	36.98 $\sigma$ 2.00	36.03 $\sigma$ 1.79
c1355	58.00 $\sigma$ 0.68	55.58 $\sigma$ 0.17	51.78 $\sigma$ 4.60	43.37 $\sigma$ 3.14
c1908	45.00 $\sigma$ 3.91	37.11 $\sigma$ 2.12	46.42 $\sigma$ 2.44	38.14 $\sigma$ 2.37
c2670	35.09 $\sigma$ 0.49	35.47 $\sigma$ 0.82	35.82 $\sigma$ 1.16	36.37 $\sigma$ 1.64
c3540	40.23 $\sigma$ 4.39	37.30 $\sigma$ 4.10	36.18 $\sigma$ 1.53	39.73 $\sigma$ 4.06
c5315	35.25 $\sigma$ 0.39	36.46 $\sigma$ 0.88	35.40 $\sigma$ 0.53	36.05 $\sigma$ 1.11
c6288	44.36 $\sigma$ 0.79	43.97 $\sigma$ 2.71	45.35 $\sigma$ 1.63	47.24 $\sigma$ 1.96
c7552	36.70 $\sigma$ 1.16	37.25 $\sigma$ 1.30	36.68 $\sigma$ 0.87	36.40 $\sigma$ 0.75
s13207	35.59 $\sigma$ 1.32	34.93 $\sigma$ 0.32	34.84 $\sigma$ 0.18	35.34 $\sigma$ 0.76
s38584	37.51 $\sigma$ 1.24	35.05 $\sigma$ 0.47	35.24 $\sigma$ 0.83	37.87 $\sigma$ 1.16
Average	40.42 $\sigma$ 2.25	40.55 $\sigma$ 2.42	39.55 $\sigma$ 1.61	38.92 $\sigma$ 2.71

report OCR values for the DWM Device and TVD Switch, respectively. This view highlights, for example, how smaller designs (e.g., c432) respond relative to larger ones (e.g., c7552), clarifying which polymorphic gates yield stronger or weaker OCR and illustrating the advantage of highest-probability selections in terms of SAT Tool time. This also shows the strong OCR output of our algorithm, even without the use of GSHE Switches.

Table 5. The GSHE Switch’s best times for benchmarks, demonstrating the strength of the GSHE Switch with highest probability gate selection. Each use 45 replaced gates and 414 keys.

Benchmark	Highest Probability		Lowest Probability		50/50 Probability		Random Probability
	SAT Time (s)	Iteration Count	SAT Time (s)	Iteration Count	SAT Time (s)	Iteration Count	SAT Time (s)	Iteration Count
c432	>48 h	>7000	275.84 $\sigma$ 55.44	124.10 $\sigma$ 9.96	>48 h	>4000	48.93 $\sigma$ 12.37	93.90 $\sigma$ 4.98
c499	>48 h	>150	179.08 $\sigma$ 36.97	125.10 $\sigma$ 16.82	413.80 $\sigma$ 124.45	134.40 $\sigma$ 20.06	1955.87 $\sigma$ 1050.35	129.20 $\sigma$ 24.19
c880	>48 h	>11,000	90.59 $\sigma$ 17.96	83.50 $\sigma$ 7.66	93.20 $\sigma$ 7.96	91.90 $\sigma$ 10.05	89.85 $\sigma$ 17.01	75.70 $\sigma$ 7.39
c1355	>48 h	>7000	172.55 $\sigma$ 45.83	118.80 $\sigma$ 22.07	52.75 $\sigma$ 14.72	92.80 $\sigma$ 6.41	573.71 $\sigma$ 510.11	175.50 $\sigma$ 165.40
c1908	>48 h	>9000	445.98 $\sigma$ 44.25	174.10 $\sigma$ 16.40	245.38 $\sigma$ 43.13	173.00 $\sigma$ 25.29	77.82 $\sigma$ 17.92	70.80 $\sigma$ 10.80
c2670	>48 h	>8500	294.10 $\sigma$ 35.32	123.80 $\sigma$ 12.43	>48 h	>5000	766.76 $\sigma$ 1594.01	467.00 $\sigma$ 772.55
c3540	>48 h	>7000	16.96 $\sigma$ 3.70	69.50 $\sigma$ 7.15	69.40 $\sigma$ 19.92	73.00 $\sigma$ 13.22	33.41 $\sigma$ 3.21	76.80 $\sigma$ 5.96
c5315	>48 h	>8000	33.19 $\sigma$ 10.33	92.80 $\sigma$ 10.77	76.11 $\sigma$ 23.55	92.10 $\sigma$ 13.14	23.85 $\sigma$ 7.49	68.70 $\sigma$ 10.13
c6288	>48 h	>25	>48 h	>10	>48 h	>20	>48 h	>20
c7552	207.20 $\sigma$ 29.41	493.50 $\sigma$ 36.29	173.64 $\sigma$ 24.57	137.40 $\sigma$ 11.13	114.44 $\sigma$ 25.68	121.10 $\sigma$ 10.71	38.04 $\sigma$ 8.81	94.90 $\sigma$ 16.07
s13207	>48 h	>2500	>48 h	>2200	>48 h	>2100	>48 h	>3000
s38584	>48 h	>1700	>48 h	>1000	>48 h	>1100	>48 h	>1100

presents the best CPU times for each benchmark, underscoring the dominance of the GSHE Switch. Similarly,

Table 6. The DWM Device’s best times for benchmarks. Each use 45 replaced gates and 189 keys.

Benchmark	Highest Probability		Lowest Probability		50/50 Probability		Random Probability
	SAT Time (s)	Iteration Count	SAT Time (s)	Iteration Count	SAT Time (s)	Iteration Count	SAT Time (s)	Iteration Count
c432	>48 h	>31,000	5.22 $\sigma$ 1.98	69.40 $\sigma$ 8.92	11.41 $\sigma$ 4.42	82.30 $\sigma$ 5.78	2.44 $\sigma$ 0.52	46.20 $\sigma$ 5.51
c499	>48 h	>13,000	13.72 $\sigma$ 4.11	67.70 $\sigma$ 6.93	6.06 $\sigma$ 2.90	72.60 $\sigma$ 20.81	40.16 $\sigma$ 23.46	84.10 $\sigma$ 19.35
c880	2.03 $\sigma$ 0.52	43.10 $\sigma$ 5.34	2.65 $\sigma$ 0.71	40.50 $\sigma$ 7.40	4.66 $\sigma$ 1.04	50.00 $\sigma$ 9.08	3.46 $\sigma$ 0.98	42.70 $\sigma$ 8.45
c1355	>48 h	>12,000	8.44 $\sigma$ 3.62	63.80 $\sigma$ 15.86	2.20 $\sigma$ 0.29	50.10 $\sigma$ 1.73	12.74 $\sigma$ 7.38	71.70 $\sigma$ 21.04
c1908	>48 h	>21,000	14.15 $\sigma$ 10.91	95.30 $\sigma$ 52.80	13.74 $\sigma$ 7.92	128.10 $\sigma$ 44.52	4.21 $\sigma$ 2.19	30.90 $\sigma$ 7.64
c2670	7 h $\sigma$ 0.5 h	3345.30 $\sigma$ 157.04	7.67 $\sigma$ 1.77	62.40 $\sigma$ 8.50	372.60 $\sigma$ 142.62	586.80 $\sigma$ 130.34	67.34 $\sigma$ 113.89	340.70 $\sigma$ 463.92
c3540	4.57 $\sigma$ 1.70	79.00 $\sigma$ 16.11	2.03 $\sigma$ 0.32	39.50 $\sigma$ 5.50	2.75 $\sigma$ 0.50	35.80 $\sigma$ 3.22	2.95 $\sigma$ 0.48	40.90 $\sigma$ 4.51
c5315	23.60 $\sigma$ 6.84	228.80 $\sigma$ 42.48	2.60 $\sigma$ 0.33	42.90 $\sigma$ 4.18	3.18 $\sigma$ 0.31	44.40 $\sigma$ 2.67	3.44 $\sigma$ 0.74	36.50 $\sigma$ 4.74
c6288	9.7 h $\sigma$ 3.6 h	19.7 $\sigma$ 3.27	>48 h	>5	>48 h	>10	>48 h	>5
c7552	88.00 $\sigma$ 27.43	401.60 $\sigma$ 78.56	3.49 $\sigma$ 0.79	54.70 $\sigma$ 6.95	3.62 $\sigma$ 0.71	52.10 $\sigma$ 6.90	2.33 $\sigma$ 0.51	33.50 $\sigma$ 5.25
s13207	10.57 $\sigma$ 2.73	171.00 $\sigma$ 17.32	5.04 $\sigma$ 1.21	41.55 $\sigma$ 7.60	3.55 $\sigma$ 1.40	135.80 $\sigma$ 5.65	2.96 $\sigma$ 1.85	86.70 $\sigma$ 6.9
s38584	>48 h	>1900	>48 h	>1500	>48 h	>1200	>48 h	>1000

and

Table 7. The TVD Switch’s best times for benchmarks. Each use 45 replaced gates and 144 keys.

Benchmark	Highest Probability		Lowest Probability		50/50 Probability		Random Probability
	SAT Time (s)	Iteration Count	SAT Time (s)	Iteration Count	SAT Time (s)	Iteration Count	SAT Time (s)	Iteration Count
c432	2.12 $\sigma$ 0.98	40.40 $\sigma$ 7.65	3.82 $\sigma$ 0.77	57.30 $\sigma$ 9.41	7.98 $\sigma$ 1.87	81.60 $\sigma$ 13.13	2.70 $\sigma$ 0.84	47.60 $\sigma$ 6.42
c499	>48 h	>13,000	9.18 $\sigma$ 4.03	64.00 $\sigma$ 15.78	10.55 $\sigma$ 3.83	78.70 $\sigma$ 18.73	29.21 $\sigma$ 12.89	83.60 $\sigma$ 16.98
c880	1.01 $\sigma$ 0.25	38.50 $\sigma$ 7.91	4.12 $\sigma$ 0.78	47.60 $\sigma$ 5.02	3.85 $\sigma$ 0.81	45.70 $\sigma$ 7.30	3.08 $\sigma$ 0.66	40.20 $\sigma$ 6.80
c1355	2.55 $\sigma$ 0.41	63.30 $\sigma$ 8.62	5.37 $\sigma$ 2.35	53.10 $\sigma$ 10.34	2.43 $\sigma$ 0.80	53.60 $\sigma$ 3.50	4.94 $\sigma$ 2.24	52.70 $\sigma$ 15.14
c1908	>48 h	>21,000	4.85 $\sigma$ 1.25	62.70 $\sigma$ 12.53	5.81 $\sigma$ 1.25	72.00 $\sigma$ 13.47	2.44 $\sigma$ 1.27	32.40 $\sigma$ 13.24
c2670	4.25 h $\sigma$ 0.25 h	2462.70 $\sigma$ 149.17	7.67 $\sigma$ 1.77	62.40 $\sigma$ 8.50	4.86 $\sigma$ 0.89	56.60 $\sigma$ 8.00	4.57 $\sigma$ 2.10	55.60 $\sigma$ 22.71
c3540	5.38 $\sigma$ 1.63	89.40 $\sigma$ 19.55	1.51 $\sigma$ 0.45	35.00 $\sigma$ 2.21	2.66 $\sigma$ 0.29	33.70 $\sigma$ 2.31	3.80 $\sigma$ 0.94	41.00 $\sigma$ 4.45
c5315	23.98 $\sigma$ 3.64	225.70 $\sigma$ 19.79	2.24 $\sigma$ 0.36	43.40 $\sigma$ 4.40	2.90 $\sigma$ 0.38	42.10 $\sigma$ 3.31	2.33 $\sigma$ 0.33	32.60 $\sigma$ 3.03
c6288	>48 h	>15	>48 h	>5	>48 h	>5	>48 h	>5
c7552	59.99 $\sigma$ 19.60	374.30 $\sigma$ 70.50	4.04 $\sigma$ 0.55	54.30 $\sigma$ 3.92	2.54 $\sigma$ 0.24	46.40 $\sigma$ 2.91	2.53 $\sigma$ 1.62	39.90 $\sigma$ 17.19
s13207	74.45 $\sigma$ 10.13	1178.01 $\sigma$ 121.32	7.11 $\sigma$ 4.56	49.43 $\sigma$ 8.43	4.65 $\sigma$ 2.82	176.72 $\sigma$ 7.19	2.38 $\sigma$ 2.32	97.74 $\sigma$ 5.1
s38584	>48 h	>1100	>48 h	>1700	>48 h	>2200	>48 h	>1200

show the time it takes for the SAT Tool to solve the circuits with the DWM Device and TVD Switch replacements, respectively. This shows the extreme dominance of using GSHE Switches under Highest Probability replacement, as nearly all tests survive the SAT Attack.

Table 8. AppSAT results for GSHE Switch, showing the OCR for the provided key.

Benchmark	Highest Probability		Lowest Probability		50/50 Probability		Random Probability
	Highest OCR (%)	Pass/Fail	Highest OCR (%)	Pass/Fail	Highest OCR (%)	Pass/Fail	Highest OCR (%)	Pass/Fail
c432	72.20	Pass	77.16	Pass	60.66	Pass	34.49	Pass
c499	TIMEOUT	Pass	68.27	Pass	59.29	Pass	59.49	Pass
c880	53.85	Pass	50.13	Pass	56.86	Pass	8.73	Pass
c1355	50.13	Pass	61.43	Pass	56.24	Pass	57.56	Pass
c1908	40.12	Pass	51.62	Pass	38.92	Pass	51.42	Pass
c2670	51.06	Pass	53.00	Pass	28.15	Pass	51.39	Pass
c3540	14.05	Pass	53.65	Pass	50.94	Pass	30.09	Pass
c5315	2.83	Pass	6.52	Pass	51.69	Pass	50.65	Pass
c6288	TIMEOUT	Pass	TIMEOUT	Pass	55.97	Pass	55.65	Pass
c7552	52.18	Pass	12.48	Pass	7.65	Pass	9.77	Pass
s13207	49.65	Pass	50.09	Pass	50.00	Pass	51.97	Pass
s38584	51.23	Pass	49.91	Pass	50.24	Pass	48.71	Pass

indicates whether the GSHE Switch defeats the AppSAT Attack by reporting the highest observed OCR or, alternatively, survival for 24 h as marked with a TIMEOUT in the OCR percentage. Finally,

Table 9. PPA values of 15 nm [42] and 45 nm [43] CMOS gates compared to the PPA values of the GSHE Switch [28].

Type	Power ($\mathsf{\mu }\mathbf{W}$)	Delay (ns)	Area ($\mathsf{\mu }{\mathbf{m}}^2$)
15 nm CMOS AND	0.6340	N/A	0.4915
45 nm CMOS OR	0.2788	0.0420	3.6200
45 nm CMOS XOR	0.4768	0.0500	7.2000
MUX-Based GSHE	0.2673	1.8300	0.0290

N/A refers to the reference not having this information.

shows PPA values for 15 nm CMOS AND [42], 45 nm CMOS OR and XOR [43], and the GSHE Switch [28].

5.2. Discussion

Averaging across all benchmarks, the highest-probability selection for GSHE Switches yields the highest OCR, outperforming the lowest-probability selection. This trend extends across other polymorphic gate types as well except for DWM switch. That said, the effect is benchmark-dependent: for designs such as c1908, highest-probability consistently exceeds lowest-probability, whereas c499 exhibits the opposite behavior. Crucially, OCR alone does not determine overall security. SAT Tool runtime is also decisive, and highest-probability selection offers a clear advantage here; GSHE Switches with highest-probability gate selection defeat the SAT Tool in nearly all cases. We also best all recent research, as shown in

Table 10. SAT Time comparison of our highest probability and lowest probability using GSHE Switches and recent works from Yue and Tehranipoor [29] and Lopez and Rezaei [44] as well as the slightly older work from Yasin et al. [26].

Benchmark	Highest Probability w/ GSHE Switch SAT Time (s)	K-Gate Locking RANE w/ Scalable Keys SAT Time [44] (s)	ProbLock SAT Time [29] (s)	SARLock w/ 14 Keys SAT Time [26] (s)
c432	>48 h	0.14	0.10	N/A
c499	>48 h	0.45	0.23	N/A
c880	>48 h	0.22	1.66	N/A
c1355	>48 h	3.08	>48 h	N/A
c1908	>48 h	0.47	2.04	N/A
c2670	>48 h	N/A	145.80	N/A
c3540	>48 h	0.52	8.29	N/A
c5315	>48 h	3.46	94.02	4.41 h
c6288	>48 h	2.77	1.23	N/A
c7552	207.20	1.32	674.5	4.05 h
s13207	>48 h	N/A	N/A	N/A
s38584	>48 h	N/A	N/A	N/A

N/A refers to the reference not having tests on the benchmark.

and

Table 11. OCR comparison of our Highest Probability and Lowest Probability using GSHE Switches and recent OCR demonstrated from Saxena et al. [4].

Benchmark	Highest Probability w/ GSHE Switch OCR (%)	Lowest Probability w/ GSHE Switch OCR (%)	Hybrid Shielding Sensitive Nodes [4] OCR (%)	Hybrid Shielding Stable Nodes [4] OCR (%)
c432	37.39	39.05	40.76	31.92
c499	35.06	55.46	4.66	49.61
c880	37.30	34.89	21.05	38.13
c1355	52.08	55.50	25.78	30.20
c1908	49.61	39.19	11.74	28.37
c2670	35.00	35.67	N/A	N/A
c3540	37.15	38.53	N/A	N/A
c5315	35.35	36.24	15.65	19.71
c6288	48.34	44.13	40.29	34.89
c7552	36.89	38.66	13.99	15.62
s13207	36.55	34.95	N/A	N/A
s38584	51.54	36.15	N/A	N/A
Average	41.02	40.70	21.79	31.06

N/A refers to the reference not having tests on the benchmark.

—our OCR is greater than recent work by Saxena et al. [4], and our SAT times are far greater than K-Gate Locking [44], ProbLock [29], and SARLock [26].

Our method also withstands the AppSAT Attack, as shown in Table 8. We observe substantial variance in AppSAT-based OCR, indicating that the key produced by AppSAT is not fully accurate—an outcome attributable both to AppSAT’s approximate nature and to the inherent randomness introduced by the GSHE Reinstate Block. Despite this randomness, OCR remains strong across all polymorphic gates and compares favorably to prior work. For instance, Saxena et al. [4] report “Hybrid Shielding” OCR averages of 21.79% (sensitive nodes) and 31.06% (stable nodes), as illustrated in Table 11. In contrast, our GSHE Highest and Lowest Probability OCR averages are 41.02% and 40.70%, respectively. For users aiming to maximize OCR, the highest-probability strategy is preferable. As well as, for robust, holistic security, we recommend employing 45 GSHE Switches and our encryption scheme with highest-probability gate selection, which delivers strong resistance against both the SAT Tool and AppSAT while achieving OCR substantially superior to prior research. 45 polymorphic gates should be chosen as [4] demonstrates that OCR decreases as the number of polymorphic gates increase.

6. Conclusions

In this paper, we introduced a gate-selection algorithm paired with an encryption scheme for integrated circuits. By incorporating emerging devices, we demonstrated the substantial impact that polymorphic gates can achieve. Our experiments used standard ISCAS 1985 and 89 benchmarks. We showed that combining highest-probability selection with the GSHE Switch yields markedly stronger security and IC protection, along with improved OCR.