Design of a CMOS Self-Bootstrapping Rectifier with Latch-up Protection for Wireless Power Harvesting Systems
Round 1
Reviewer 1 Report
Comments and Suggestions for AuthorsThe paper presents a CMOS rectifier for inductive wireless power harvesting intended for implantable devices. The main idea is to use NMOS devices in the power rectification path to reduce latch-up risk, supported by a bootstrap gate-boosting scheme to overcome NMOS headroom limitations and a multi-input comparator to suppress reverse current in a cross-coupled rectifier.
The claim of an “all-NMOS” design needs clearer wording. While the main rectifying path uses NMOS devices, the bootstrap circuitry still includes PMOS transistors, as shown in the schematic.
Equation (1) describing total power transfer efficiency is incorrect as written. The efficiencies of cascaded stages should be combined multiplicatively, not additively. If the intention is to describe losses, this should be rewritten clearly, either as a loss budget or as a product of individual efficiencies with proper definitions.
Key performance metrics such as VCE and PCE are used throughout the paper but are never clearly defined. The manuscript should explicitly state how these metrics are calculated, including how the input voltage is defined (peak, RMS, or amplitude) and how AC input power is measured.
There is a significant inconsistency in the comparator operation description. The text and Table 1 state that certain transistors turn on when VC1 is below ground. But elsewhere VC1 and VC2 are described as conjugate waveforms ranging from 0 to 3.3 V, which means VC1 never goes below ground. As written, the comparator logic cannot operate as described. This is not a minor wording issue and directly affects the validity of the reverse-current suppression mechanism. The section should be rewritten so that node definitions, reference levels, and switching conditions are fully consistent.
The measurement section generally provides useful information, but the transmitter setup description is duplicated and should be cleaned up.
The reported chip area of 3.0096 mm² is relatively large for an implantable rectifier. A brief area breakdown would help the reader understand where the area is spent, such as power transistors, bootstrap capacitors, and comparator circuitry. The type and value of the bootstrap capacitor should also be specified.
The manuscript contains several typographical and grammatical errors that reduce clarity and credibility. Symbols and notation should be made consistent throughout, including ground naming, voltage symbols, and whether VC1 and VC2 are referenced to ground or treated as differential coil terminals.
Author Response
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Reviewer 2 Report
Comments and Suggestions for AuthorsThis paper presents the design of a boost-comparator-based rectifier for wireless energy harvesting. The all-NMOS power transistor topology is used to eliminate the risk of latch-up associated with parasitic P-N-P-N structures in standard CMOS processes. Fabricated in a 0.18 µm technology, the design achieves an output voltage of 2.94 V and can deliver a maximum operating current of 5 mA. The rectifier demonstrates high performance with a peak voltage conversion efficiency (VCE) of 89.02% at an 8 kΩ load and a peak power conversion efficiency (PCE) of 84.73% at a 500 Ω load. However, the manuscript contains quite a few technical and formatting issues that require attention:
(1) Regarding Equation (1), the derivation or theoretical basis is not provided. Furthermore, based on its formulation, if the efficiency of each component is relatively high, the calculated result could theoretically exceed 100%. The authors should explicitly justify the equation's validity and explain why such an outcome is not possible in practice.
(2) In the Introduction section, the paper fails to provide a detailed account of existing research by other scholars regarding the key innovative aspects of the authors' work, which makes it difficult to quantify and compare the novelty of their contributions.
(3) Based on the comparative results in Table 3, the overall advantages of the proposed work do not appear to be strongly pronounced relative to the cited state-of-the-art.
(4) The manuscript does not justify the selection of a 2 MHz signal for testing. The rationale for this specific frequency is unclear, and potential results or trade-offs at other (e.g., lower or higher) frequencies remain unexplored.
(5) In line 50, the sentence ", it can be applied aa Low-dropout...." contains the unclear term "aa." Is this a typographical error with a repeated letter 'a'? Please clarify and correct the intended word.
(6) Significant blank spaces appear at the bottom of pages 7 and 9. The authors should revise the manuscript layout to improve formatting and ensure optimal page utilization.
(7) For better readability and flow, Figure 3 should be relocated to appear later within its respective subsection. Similarly, Figures 5 and 6 should be placed separately rather than consecutively. Furthermore, within the text, Figure 6(b) is described before Figure 6(a). It is recommended to either adjust the description order or swap the positions of subfigures 6(a) and 6(b) for logical consistency.
(8) The analysis of the results in Table 3 should not be placed within the Conclusion section (Section 5). This discussion belongs in the Results or a dedicated Discussion section.
(9) The Conclusion would be strengthened by including a brief discussion on the limitations of the current work and suggesting potential directions for future research.
Author Response
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Reviewer 3 Report
Comments and Suggestions for AuthorsThe article discusses the design and verification of a CMOS rectifier for wireless power harvesting, intended primarily for implantable biomedical devices. The authors propose a boost-comparator rectifier architecture based exclusively on NMOS transistors, which aims to eliminate the latch-up phenomenon characteristic of mixed PMOS/NMOS structures. The use of a bootstrap circuit and a four-input comparator allows for an increase in both voltage conversion efficiency (VCE) and power conversion efficiency (PCE). The work includes theoretical analysis, post-layout simulations, and measurement results for a circuit manufactured in 0.18 µm CMOS technology, achieving, among other things, VCE ≈ 89% and PCE ≈ 85% at a frequency of 2 MHz.
Weaknesses and critical comments:
1. Linguistic quality: The text contains a noticeable number of grammatical errors, typos, and awkward phrasing (e.g., repetition of sentences in the measurement section, minor stylistic errors), which reduces the readability of the work.
2. Simulation-measurement discrepancy: The drop in VCE from ~97% (simulations) to ~89% (measurement) is quite significant. The explanation for this difference could be elaborated on (e.g., the influence of PCB parasitics, coil losses, impedance mismatch).
3. Chip area: The area of 3.0 mm² is relatively large for a CMOS rectifier; there is no discussion of the trade-off between current efficiency and scalability/miniaturization for implants with lower requirements.
4. Limited frequency range: The circuit is mainly optimized for 2 MHz. A broader discussion of stability and efficiency at a wider operating frequency range would be useful.
The article presents a valuable, well-founded technical solution and makes a significant contribution to the field of CMOS rectifiers for wirelessly powered implants. Despite minor editorial shortcomings and a few issues that require clarification, the work meets the publication standards of a technical journal.
Author Response
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Round 2
Reviewer 1 Report
Comments and Suggestions for AuthorsThe authors have addressed the main comments from the review. The technical issues have been corrected, and the explanations are now consistent with the results shown.
Any remaining issues are minor and editorial in nature and do not affect the validity of the work.
Author Response
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Reviewer 2 Report
Comments and Suggestions for AuthorsThe authors have addressed all my concerns appropriately. It is recommended that in the manuscript, figures should not be placed before text under subsection headings.
Author Response
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