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Article

Design and Realization of Dynamically Adjustable Multi-Pulse Real-Time Coherent Integration System

by
Jinrui Bi
,
Hongyu Zhang
,
Lihua Sun
* and
Qingchao Jiang
School of Information Science and Engineering, East China University of Science and Technology, Shanghai 200237, China
*
Author to whom correspondence should be addressed.
Electronics 2026, 15(2), 397; https://doi.org/10.3390/electronics15020397
Submission received: 8 December 2025 / Revised: 3 January 2026 / Accepted: 9 January 2026 / Published: 16 January 2026
(This article belongs to the Special Issue From Circuits to Systems: Embedded and FPGA-Based Applications)

Abstract

Radar signal coherent integration technology is a critical method to improve the performance of detection systems. However, existing techniques face challenges regarding real-time performance and the flexibility of multi-pulse coherent accumulation. In this paper, a dynamically configurable multi-pulse multi-frame real-time coherent integration system based on FPGA is designed and implemented, and the dynamic configuration of the number of pulses and the number of frames stored for each pulse is realized through the host computer. The experimental results show that the output signal delay of coherent integration is 33 microseconds at 40 pulses, and the energy gain reaches 16 dB at 40 pulses, which provides a dynamically configurable hardware platform and solution for real-time coherent integration of high-frame-count, multi-pulse radar signals.
Keywords: radar detection; coherent integration; FPGA; dynamic configuration radar detection; coherent integration; FPGA; dynamic configuration

Share and Cite

MDPI and ACS Style

Bi, J.; Zhang, H.; Sun, L.; Jiang, Q. Design and Realization of Dynamically Adjustable Multi-Pulse Real-Time Coherent Integration System. Electronics 2026, 15, 397. https://doi.org/10.3390/electronics15020397

AMA Style

Bi J, Zhang H, Sun L, Jiang Q. Design and Realization of Dynamically Adjustable Multi-Pulse Real-Time Coherent Integration System. Electronics. 2026; 15(2):397. https://doi.org/10.3390/electronics15020397

Chicago/Turabian Style

Bi, Jinrui, Hongyu Zhang, Lihua Sun, and Qingchao Jiang. 2026. "Design and Realization of Dynamically Adjustable Multi-Pulse Real-Time Coherent Integration System" Electronics 15, no. 2: 397. https://doi.org/10.3390/electronics15020397

APA Style

Bi, J., Zhang, H., Sun, L., & Jiang, Q. (2026). Design and Realization of Dynamically Adjustable Multi-Pulse Real-Time Coherent Integration System. Electronics, 15(2), 397. https://doi.org/10.3390/electronics15020397

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