A Capacitor-Less Low Dropout Regulator with Wide Input Range and High Power-Supply Rejection Ratio

Abstract

This paper presents a capacitor-less low-dropout regulator (LDO) with a wide input-voltage range and high power-supply rejection ratio (PSRR), designed and laid out in a 0.18 μm CMOS process. The design incorporates a pre-regulation circuit to suppress power-supply noise. The proposed LDO supports an input-voltage range from 3.3 V to 40 V while maintaining an output voltage of 3.3 V. The integrated output noise from 10 Hz to 100 kHz is 4.3 nV². The proposed LDO achieves a PSRR of $-109$ dB at 1 kHz under a maximum load current of 100 mA, representing a 20 dB improvement compared with the same LDO without the pre-regulation circuit.

1. Introduction

Low dropout regulators (LDOs) are widely used in automotive electronics due to their transient response, low noise and simple architecture [1]. Automotive electronic systems require LDOs with a wide input range, ensuring stable operation even under fluctuating power-supply conditions [2]. Given the high variability in supply voltage and significant noise in automotive environments, LDOs must have a wide input range and high power-supply rejection ratio (PSRR). Since input-voltage ripple may extend over a wide frequency range from $0.1$ Hz to 5 MHz, it is critical for an LDO to maintain high PSRR across this frequency range [3].

Various approaches have been proposed to improve PSRR. J. Guo et al. improved PSRR by applying feed-forward power-supply ripples to the gate of power transistor [4]. Similarly, U. Awais et al. used a replica circuit to track power-supply fluctuations by injecting reverse feed-forward current to minimize gate-source voltage errors [5]. Although these feed-forward technologies can effectively improve PSRR, they significantly increase circuit complexity. J. Zoche et al. used multi-stage power transistors in series to improve PSRR; however, their method incurs additional power consumption [6]. H. Gupta et al. proposed a high-gain amplifier with a folded cascode structure in the output stage of the amplifier, but its PSRR improvement is modest [7]. The voltage-reference circuit is also important for maintaining the output stability of an LDO. Azimi et al. proposed a two-stage subthreshold voltage reference using body-bias curvature compensation, achieving low power consumption and improved temperature stability [8]. More recently, Gagliardi et al. presented an NMOS-only self-cascode voltage reference using a decoupling pseudo-resistor to improve high-frequency PSR under ultra-low-voltage operation [9]. Compared with these low-voltage reference circuits, the voltage-reference structure adopted in this work requires a higher operating voltage but is more suitable for generating the stable internal 5 V supply required by the proposed high-voltage LDO.

In LDOs, PSRR is primarily determined by the error amplifier. If the PSRR of error amplifier is limited, the overall PSRR of the LDO will be constrained. Additionally, components like buffers and power stages can also introduce power noise that further degrades the PSRR of the LDO.

To address these issues, we propose a pre-regulation circuit that preprocesses the power-supply voltage, minimizing the ripples transmitted to the error amplifier, thereby enhancing PSRR. The proposed pre-regulation technology ensures a stable 5 V output in the input voltage range from 5 V to 40 V, and effectively optimizes the PSRR of the subsequent circuit stages. The design achieves a PSRR of $-109$ dB at 1 kHz, significantly improving the overall PSRR of the LDO.

The remainder of this paper is structured as follows: Section 2 introduces the proposed LDO architecture and transistor-level circuit. Section 3 presents the pre-layout and post-layout simulation results, and Section 4 concludes this work.

2. Circuit Design and Analysis

The employed 0.18 μm CMOS process provides high-voltage transistors rated to withstand 40 V. These high-voltage devices are used in the proposed circuit to support operation at input voltages up to 40 V.

Figure 1 illustrates the fundamental architecture of an LDO with a pre-regulation circuit. This architecture consists of a pre-regulation circuit (Pre-REG), an error amplifier (EA), a buffer, a pass element, two feedback resistors ($R_{\mathrm{f}1}$, $R_{\mathrm{f}2}$), and other essential modules. The pre-regulation circuit converts the high-voltage power to a low-voltage power for the error amplifier. The feedback resistors sample the output voltage and feed it back to one input of the error amplifier, while the other input is connected to the reference voltage ($V_{\mathrm{REF}}$). The output of the error amplifier drives the gate of the power transistor through the buffer, generating a stable output voltage, $V_{\mathrm{OUT}}$.

2.1. Pre-REG Design

The pre-regulation circuit design is shown in Figure 2. In this design, transistors $M_4$–$M_{11}$ form a reference current source that generates a reference current $I_{\mathrm{B}}$, independent of the supply voltage. This reference current $I_{\mathrm{B}}$ biases several diode-connected transistors and drives a source follower to produce the voltage N3VT, which powers the gate of LDMOS transistors $M_{31}$, $M_{34}$, $M_{35}$, providing high and low voltage isolation. Transistors $M_{29}$–$M_{37}$ create a circuit similar to the Brokaw bandgap reference voltage source. A cascode current mirror is adopted to enhance the PSRR of the internal power supply. The linearity of the internal power supply is improved by the feedback from the current introduced in the high-voltage start-up circuit.

The pre-regulation circuit ensures a stable 5 V output, independent of temperature and input voltage, within the voltage range of 5 V to 40 V:

$$\begin{array}{c}\hfill V_{\mathrm{DDA}}={\displaystyle \frac{R_{11}+R_{12}}{R_{12}}}·\left[2{\displaystyle \frac{R_{10}}{R_9}}{V}_{\mathrm{T}}+V_{\mathrm{BE}5}\right]\end{array}$$

(1)

where $V_{\mathrm{T}}$ is thermal voltage and N is the number ratio of transistors ${\mathrm{npn}}_4$ and ${\mathrm{npn}}_5$. The pre-regulation circuit effectively powers the error amplifier while mitigating power noise, significantly improving the LDO PSRR.

2.2. Proposed LDO Design

Figure 3 shows the transistor-level circuit of the LDO designed in this paper. To improve PSRR, the error amplifier uses a folded cascode two-stage operational amplifier structure, with a resistive load instead of a dynamic load at the output end of the amplifier [10]. The gain buffer stage adopts an N-type common-source amplifier (N-CS) with a current mirror load, while the power stage uses a PMOS transistor as the transmission device. The PSRR contribution path of the LDO is shown in Figure 1. The total PSRR is primarily determined by three components: the error amplifier, buffer, and power transistor. The total PSRR can be expressed as follows:

$$\begin{array}{c}\hfill {\mathrm{PSRR}}_{\mathrm{LDO}}={\mathrm{PSRR}}_1+{\displaystyle \frac{{\mathrm{PSRR}}_{\mathrm{Buffer}}}{\beta ·A_{\mathrm{EA}}·A_{\mathrm{Buffer}}}}+{\displaystyle \frac{{\mathrm{PSRR}}_{\mathrm{POW}}}{\beta ·A_{\mathrm{EA}}·A_{\mathrm{Buffer}}·A_{\mathrm{POW}}}}\end{array}$$

(2)

$$\begin{array}{c}\hfill {\mathrm{PSRR}}_1={\mathrm{PSRR}}_{\mathrm{Pre}-\mathrm{REG}}{\displaystyle \frac{{\mathrm{PSRR}}_{\mathrm{EA}}}{\beta ·A_{\mathrm{EA}}}}\end{array}$$

(3)

where $A_{\mathrm{EA}}$ is the amplification factor of the error amplifier, $A_{\mathrm{Buffer}}$ is the amplification factor of the buffer, $A_{\mathrm{POW}}$ is the amplification factor of the power transistor, and $\beta$ is the feedback coefficient of the feedback network. The expression for $\beta$ is:

$$\begin{array}{c}\hfill \beta ={\displaystyle \frac{R_{\mathrm{f}1}}{R_{\mathrm{f}1}+R_{\mathrm{f}2}}}\end{array}$$

(4)

Rewriting Formula (2):

$$\begin{array}{c}\hfill {\mathrm{PSRR}}_{\mathrm{LDO}}={\mathrm{PSRR}}_1+{\displaystyle \frac{\left|{\mathrm{PSRR}}_{\mathrm{POW}}\right|-\left|{\mathrm{PSRR}}_{\mathrm{Buffer}}·A_{\mathrm{POW}}\right|}{\beta ·A_{\mathrm{EA}}·A_{\mathrm{Buffer}}·A_{\mathrm{POW}}}}\end{array}$$

(5)

From Equation (5), it can be seen that improving LDO PSRR requires maximizing PSRR of the error amplifier and designing the circuit to ensure that power-supply noise from the buffer stage and power stage cancels each other out.

By calculating the PSRR of PMOS power transistor and the N-CS, the expressions are:

$$\begin{array}{c}\hfill {\mathrm{PSRR}}_{\mathrm{Buffer}}={\displaystyle \frac{A_{\mathrm{Buffer}}·g_{\mathrm{O},\mathrm{BL}}}{g_{\mathrm{O},\mathrm{BIN}}+A_{\mathrm{Buffer}}·g_{\mathrm{O},\mathrm{BL}}}}\end{array}$$

(6)

$$\begin{array}{cc}\hfill {\mathrm{PSRR}}_{\mathrm{POW}}& ={\displaystyle \frac{g_{\mathrm{m},\mathrm{POW}}+g_{\mathrm{O},\mathrm{POW}}}{g_{\mathrm{O},\mathrm{POW}}+g_{\mathrm{O},\mathrm{L}}}}\hfill \\ \hfill & =-A_{\mathrm{POW}}·\left(1+{\displaystyle \frac{g_{\mathrm{O},\mathrm{POW}}}{g_{\mathrm{m},\mathrm{POW}}}}\right)\hfill \end{array}$$

(7)

where $g_{\mathrm{O},\mathrm{BIN}}$ is the output transconductance of the buffer stage input transistor, $g_{\mathrm{O},\mathrm{BL}}$ is the output transconductance of the buffer stage load transistor, $g_{\mathrm{m},\mathrm{POW}}$ is the input transconductance of the power transistor, $g_{\mathrm{O},\mathrm{POW}}$ is the output transconductance of the power transistor, and $g_{\mathrm{O},\mathrm{L}}$ is the load transconductance.

Substituting Equations (6) and (7) into Equation (5):

$$\begin{array}{c}\hfill {\mathrm{PSRR}}_{\mathrm{LDO}}\approx {\mathrm{PSRR}}_1+{\displaystyle \frac{\frac{g_{\mathrm{O},\mathrm{BIN}}}{A_{\mathrm{Buffer}}·g_{\mathrm{O},\mathrm{BL}}}+\frac{1}{A_{\mathrm{POW}}}}{\beta ·A_{\mathrm{EA}}·\left|A_{\mathrm{Buffer}}\right|}}\end{array}$$

(8)

If the intrinsic gain of the cascode structure is close to the intrinsic gain of the power transistor, Equation (8) can be simplified to:

$$\begin{array}{c}\hfill {\mathrm{PSRR}}_{\mathrm{LDO}}={\mathrm{PSRR}}_1+{\displaystyle \frac{\frac{g_{\mathrm{O},\mathrm{BIN}}}{g_{\mathrm{O},\mathrm{BL}}}+1}{\beta ·A_{\mathrm{EA}}·\left|A_{\mathrm{Buffer}}\right|·A_{\mathrm{POW}}}}\end{array}$$

(9)

By comparing the symbols of the first and second terms in Equation (9), it can be found that the power-supply noise from the first stage amplifier accumulates with that from the second stage and the power stage. Thus, optimizing LDO PSRR requires simultaneously reducing both terms in Formula (9).

Furthermore, the denominator of the second term is significantly larger than that of the first term, indicating that the LDO PSRR is predominantly determined by the first term. As power noise from the buffer stage and power stage tends to cancel each other out, the noise from error amplifier becomes the primary source of LDO noise.

To enhance LDO PSRR, it is crucial to minimize the noise contribution from the error amplifier. This can be realized using a pre-regulation circuit by introducing a cascode two-stage operational amplifier for greater loop gain, with an N-type current mirror to absorb power-supply noise, thereby minimizing the effect of power-supply ripples on error amplifier.

For the capacitor-less LDO, there is no large load capacitance or bypass capacitance at the output, and the zero-pole distribution of the loop differs from that of traditional LDOs. In this design, nested Miller compensation was adopted which connects a Miller capacitor between the first stage of the error amplifier and the output. In the small-signal model, as shown in Figure 4, $R_i$ and $C_i$ represent the output resistance and output capacitance of stage i, $C_{\mathrm{C}}$ is the Miller compensation capacitor, $C_{\mathrm{gd}}$ is the parasitic capacitance of the power transistor, $R_{\mathrm{O}}$ is the load resistance of the power transistor, and $C_{\mathrm{O}}$ is the load capacitance of the power transistor.

$$\begin{array}{c}\hfill V_1\left({\displaystyle \frac{1}{R_1}}+s{C}_1+s{C}_{\mathrm{C}}\right)-s{C}_{\mathrm{C}}{V}_{\mathrm{OUT}}=-g_{\mathrm{m}1}{V}_{\mathrm{in}}\end{array}$$

(10)

$$\begin{array}{cc}\hfill V_2\left({\displaystyle \frac{1}{R_2}}+s{C}_2\right)+g_2{V}_1& =0\hfill \end{array}$$

(11)

$$\begin{array}{c}\hfill V_3\left({\displaystyle \frac{1}{R_3}}+s{C}_3+s{C}_{\mathrm{gd}}\right)-s{C}_{\mathrm{gd}}{V}_{\mathrm{OUT}}=-\left(g_{\mathrm{m}4}{V}_1-g_{\mathrm{m}3}{V}_2\right)\end{array}$$

(12)

$$\begin{array}{c}\hfill V_{\mathrm{OUT}}\left({\displaystyle \frac{1}{R_{\mathrm{O}}}}+s{C}_{\mathrm{O}}+s{C}_{\mathrm{C}}+s{C}_{\mathrm{gd}}\right)-s{C}_{\mathrm{C}}{V}_1-s{C}_{\mathrm{gd}}{V}_3=-g_{\mathrm{mp}}{V}_3\end{array}$$

(13)

$$\begin{array}{c}\hfill A\left(s\right)={\displaystyle \frac{g_{\mathrm{m}1}\left(g_{\mathrm{m}3}+g_{\mathrm{m}4}\right)g_{\mathrm{mp}}{R}_1{R}_3{R}_{\mathrm{O}}}{1+\left(g_{\mathrm{m}3}+g_{\mathrm{m}4}\right)g_{\mathrm{mp}}{R}_1{R}_3{R}_{\mathrm{O}}{C}_{\mathrm{C}}s}}\times {\displaystyle \frac{1-A_{0}s-A_1{s}^2}{1+B_{0}s+B_1{s}^2}}\end{array}$$

(14)

$$\begin{array}{c}\hfill A_0={\displaystyle \frac{\left(g_{\mathrm{m}3}+g_{\mathrm{m}4}\right)R_3{R}_{\mathrm{O}}{C}_{\mathrm{gd}}+R_{\mathrm{O}}{C}_{\mathrm{C}}}{\left(g_{\mathrm{m}3}+g_{\mathrm{m}4}\right)g_{\mathrm{mp}}{R}_3{R}_{\mathrm{O}}}}\end{array}$$

(15)

$$\begin{array}{c}\hfill A_1={\displaystyle \frac{C_{\mathrm{C}}\left(C_{\mathrm{gd}}+C_3\right)}{\left(g_{\mathrm{m}3}+g_{\mathrm{m}4}\right)g_{\mathrm{mp}}}}\end{array}$$

(16)

$$\begin{array}{cc}\hfill B_0& ={\displaystyle \frac{1}{\left(g_{\mathrm{m}3}+g_{\mathrm{m}4}\right)g_{\mathrm{mp}}}}\left[\left(C_{\mathrm{O}}+C_{\mathrm{gd}}\right)\left({\displaystyle \frac{C_{\mathrm{gd}}}{R_1{C}_{\mathrm{C}}}}+{\displaystyle \frac{1}{R_3}}\right)+{\displaystyle \frac{C_{\mathrm{gd}}}{R_{\mathrm{O}}}}\right]\hfill \end{array}$$

(17)

$$\begin{array}{c}\hfill B_1={\displaystyle \frac{C_{\mathrm{gd}}{C}_{\mathrm{O}}}{\left(g_{\mathrm{m}3}+g_{\mathrm{m}4}\right)g_{\mathrm{mp}}}}\end{array}$$

(18)

From Equation (14), the main pole of the LDO loop is located at the output of the first stage of the error amplifier:

$$\begin{array}{c}\hfill p_1=-{\displaystyle \frac{1}{\left(g_{\mathrm{m}3}+g_{\mathrm{m}4}\right)g_{\mathrm{mp}}{R}_1{R}_3{R}_{\mathrm{O}}{C}_{\mathrm{C}}}}\end{array}$$

(19)

Setting the numerator term in Equation (14) to zero to determine the zero location.

$$\begin{array}{c}\hfill 1-A_{0}s-A_1{s}^2=0\end{array}$$

(20)

$$\begin{array}{c}\hfill z_{1,2}\approx \pm \sqrt{{\displaystyle \frac{\left(g_{\mathrm{m}3}+g_{\mathrm{m}4}\right)g_{\mathrm{mp}}}{C_{\mathrm{C}}\left(C_{\mathrm{gd}}+C_3\right)}}}\end{array}$$

(21)

Two zeros of equal magnitude, located in the left and right half-planes, counteract the phase influence of the loop but introduce a gain change of 40 dB/dec at the zero point, which will affect the system stability. Therefore, placing these zeros at high frequency is crucial.

Setting the denominator of the second term in Formula (14) to zero and comparing it with the pole function of the second-order system to determine the additional poles:

$$\begin{array}{c}\hfill 1+B_{0}s+B_1{s}^2=0\end{array}$$

(22)

$$\begin{array}{c}\hfill N\left(s\right)=1+{\displaystyle \frac{2\zeta }{{\omega }_n}}s+{\left({\displaystyle \frac{s}{{\omega }_n}}\right)}^2\end{array}$$

(23)

By comparing Formulas (22) and (23), the expressions for $\zeta$ and ${\omega }_n$ are derived as follows:

$$\begin{array}{c}\hfill {\omega }_n=\sqrt{{\displaystyle \frac{\left(g_{\mathrm{m}3}+g_{\mathrm{m}4}\right)g_{\mathrm{mp}}}{C_{\mathrm{gd}}{C}_{\mathrm{O}}}}}\end{array}$$

(24)

$$\begin{array}{c}\hfill \zeta ={\displaystyle \frac{1}{2}}\sqrt{{\displaystyle \frac{C_{\mathrm{O}}}{\left(g_{\mathrm{m}3}+g_{\mathrm{m}4}\right)g_{\mathrm{mp}}{C}_{\mathrm{gd}}{R}_3^2}}}\end{array}$$

(25)

The conjugate complex poles $p_2$, $p_3$ are:

$$\begin{array}{c}\hfill p_{2,3}=-\zeta {\omega }_n\pm {\omega }_n\sqrt{\left|{\zeta }^2-1\right|}\end{array}$$

(26)

Generally, the second-order system works in an underdamped case by using 0 < $\zeta$ < 1, where $\zeta$ is generally selected between 0.4 and 0.8. The natural frequency ${\omega }_n$ should be maximized to ensure system stability.

3. Simulation Results

All circuit simulations were performed using Cadence Virtuoso 6.1.7 with the high-convergence accuracy setting.

As shown in Figure 5, under a 12 V power supply and 100 mA load, the loop gain reaches 109 dB, with a gain-bandwidth (GBW) of $1.09$ MHz, and a phase margin of 66 deg. Under no-load condition with the 12 V supply, the loop gain increases to 121 dB, the GBW to $1.27$ MHz and the phase margin to 69 deg, as presented in Figure 6. These alternating-current (AC) simulation results show that the capacitor-less LDO is stable across the entire load range. Figure 7 presents the simulation curves of the LDO PSRR. With a 100 mA load current and a 12 V power supply, the LDO PSRR with pre-regulation circuit reaches $-109$ dB at 1 kHz, improving the PSRR by 20 dB compared with the design without the pre-regulation circuit. This enhancement significantly optimizes the low-frequency LDO PSRR.

The performance evaluation of the proposed LDO compared to existing designs reveals several key advantages and trade-offs. As outlined in

Table 1. Performance summary and comparison.

Parameter	[10]	[12]	[11]	[13]	This Work
Technology (nm)	600	180	180	180	180
Result type	Measurement	Measurement	Measurement	Measurement	Post-layout simulation
$V_{\mathrm{IN}}$ (V)	2.2–5.5	1.8–2.5	NR	NR	3.3–40
$V_{\mathrm{OUT}}$ (V)	1.8–3.3	1.6–2.3	1	1.8	3.3
$V_{\mathrm{DO}}$ (mV)	105	200	200	100	170
$I_{\mathrm{OUT}}$ (mA)	0–150	0–200	0–50	0–1	0–100
Line regulation (μV/V)	NR	NR	NR	NR	7
Load-voltage variation (μV)	NR	NR	NR	NR	213
PSRR at 1 kHz (dB)	−71	−63	−80	−72	−109
PSRR at 10 kHz (dB)	−51	−62	−79	−55	−89
PSRR at 100 kHz (dB)	−41	−56	−62	−35	−54

NR: not reported.

, the proposed LDO demonstrates a significant PSRR enhancement, especially at lower frequencies. At 1 kHz, the proposed LDO achieves a PSRR of $-109$ dB, outperforming other designs, such as $-71$ dB in [10] and $-80$ dB in [11]. This significant improvement underscores the effectiveness of the novel pre-regulation circuit in mitigating power-supply noise and enhancing overall stability. The broad input voltage range of $3.3$ V to 40 V offered by the proposed LDO offers a substantial improvement over previous designs with narrower voltage ranges, making it versatile for applications such as automotive and industrial systems. The achieved dropout voltage of 170 mV is competitive compared to existing designs, such as 200 mV in [12]. A lower dropout voltage typically indicates a better performance. Our design strikes a balance between dropout voltage and other key parameters like PSRR and input voltage range.

The integrated output noise was calculated from the output-referred noise spectral density over the frequency range from 10 Hz to 100 kHz according to

$$\overline{V_{n,\mathrm{OUT}}^2}={\int }_{10\mathrm{Hz}}^{100\mathrm{kHz}}\overline{V_{n,\mathrm{EA}2}^2}\left(f\right)\mathrm{d}f.$$

(27)

where $\overline{V_{n,\mathrm{EA}2}^2}\left(f\right)$ represents the output-referred noise spectral density obtained through noise simulation. By numerically integrating the noise spectral density over the specified frequency range, an integrated output noise of 4.3 nV² was obtained.

The physical layout of the proposed LDO is shown in Figure 8. The layout dimensions are 472.315 μm × 774.465 μm, corresponding to an area of approximately 0.366 mm². Parasitic extraction was performed based on the completed layout.

The reported line regulation is 7 μV/V, and the output-voltage variation over the 0 mA–100 mA load-current sweep is 213 μV. Figure 9 presents the post-layout line-regulation and load-regulation characteristics under different process corners. The results confirm that the proposed LDO maintains stable output-voltage regulation after considering the extracted layout parasitics.

To further evaluate the robustness of the proposed LDO, additional simulations were performed across different process corners and over the temperature range from −40 °C to 125 °C at a load current of 50 mA. Figure 10a presents the stability simulation results, while Figure 10b shows the corresponding PSRR simulation results. The proposed LDO maintains stable operation and effective power-supply rejection under the investigated process-corner and temperature conditions.

It should be noted that the proposed LDO has not yet been experimentally measured. Although the results of this work are based on post-layout simulations including extracted parasitic effects, the results of the compared designs were obtained from measurements. Therefore, the comparison in Table 1 should be regarded as an indicative performance benchmark rather than a direct experimental comparison.

The proposed LDO excels in PSRR performance, particularly at lower frequencies, due to its innovative pre-regulation approach and optimized circuit design. The wide input voltage range adds significant flexibility, although there are trade-offs in dropout voltage and output current capabilities. These attributes make our LDO ideal for applications where noise rejection and voltage stability are crucial, while the output current and dropout voltage should be evaluated based on the specific application needs.

4. Conclusions

This paper presents a capacitor-less LDO with a wide input-voltage range and enhanced PSRR, designed and laid out in a 0.18 μm CMOS process. The proposed design employs an N-type common-source buffer to reduce the noise contribution of the pass transistor and a pre-regulation circuit to suppress the supply noise transmitted to the error amplifier.

Simulation results demonstrate an integrated output noise of 4.3 nV² over the frequency range from 10 Hz to 100 kHz. The achieved PSRR values are $-109$ dB, $-89$ dB, and $-54$ dB at 1 kHz, 10 kHz, and 100 kHz, respectively. The pre-regulation circuit improves the PSRR by 20 dB at 1 kHz compared with the same LDO without pre-regulation.