A 60 GHz Low-Phase-Error Current-Reuse Variable-Gain Amplifier in 65 nm CMOS

Response 1: We sincerely apologize for this oversight and greatly appreciate the reviewer for pointing this out. In strict accordance with the reviewer's recommendation, we have thoroughly carefully revised the manuscript to reduce the similarity score. Specifically, we have completely paraphrased the Introduction and Measurement sections. Furthermore, the extensive addition of new theoretical analysis (Section 2) and discussions (Section 4) has increased the proportion of original content. We are confident that the similarity score is now fully resolved. We have attached the updated similarity report for your reference as below, which is 6%.

We added and revised the sentences as follow:

We paraphrased the all sentences of Section 1. Introduction and the first two paragraphs of Section 3. Results.

Response 2: Thank you for pointing this out. We have removed the large consecutive citation blocks. Instead, we carefully selected the most relevant and recent papers to support our statements in the introduction [1-6], making the citations much more precise.

Response 3: We completely agree with the reviewer’s valuable feedback. To clarify how our variable gain amplifier (VGA) topology was designed and optimized, we have comprehensively expanded Section 2.4 (Impedance-Invariant Variable Gain Stage). Specifically, based on small-signal equivalent circuit model in Figure 5, we provided mathematical derivations to analyze the behavior of our impedance-invariant variable gain (IIVG) stage. First, we derived the full voltage gain transfer function in Equation (1) and the corresponding phase response in Equation (2). Second, we mathematically demonstrated that by keeping the parasitic gate-to-drain capacitances of the main and steering paths symmetric , the phase variation during gain tuning intrinsically becomes zero, as shown in Equation (3). Finally, we have added Equation (4) to show how the simplified voltage gain is directly determined by the transconductance difference  controlled by the differential gate biases V_GP and V_GN.

By complementarily adjusting the bias voltages V_GP and V_GN, we achieve a wide gain-tuning range while strictly keeping the total parasitic capacitance constant. This theoretical framework now clearly explains how our VGA topology achieves near-zero phase error and robust wideband matching under all gain settings.

We added and revised the sentences as follow:

Now, the gain of the IIVG stage under  is reduced to

According to (4), the voltage gain of the IIVG stage is solely determined by the effective transconductance difference, . Moreover, owing to the proposed transformer-based current-reuse scheme, this gain control is performed without additional DC power consumption, as the bias current is completely reused between the stacked stages. During operation, the gain is continuously tuned by complementarily adjusting the dc gate bias voltages, V_GP and V_GN in Figure 1. Because this complementary current-steering mechanism structurally keeps the sum of the parasitic capacitances constant across all nodes, the VGA can achieve significant gain attenuation without altering the input and output impedances. This unique characteristic ensures that the wideband impedance matching and the insertion phase remain completely invariant across the entire gain tuning range.

Based on this theoretical small-signal analysis, the parameter selection procedure was meticulously conducted to optimize both phase invariance and power efficiency. To mathematically eliminate the phase variation according to (2) and (3), it is strictly required to equalize the intrinsic parasitic gate-to-drain capacitances . Therefore, the main and steering transistors M₃–M₆ were selected to have identical widths of 39 μm. To optimize the gain, linearity, and power consumption, a quiescent current of 7.4 mA was selected.

Response 4: We apologize for this omission. The main caption for Figure 2 has been properly added in the revised manuscript.

We revised the caption as follow: Figure 2. Input and output stages: (a) Simulated MAG and stability factor of the common source amplifier with neutralization capacitor C_N and (b) Layout of amplifier core with neutralization capacitors and inductor L₁.

Response 5: Thank you for this valuable suggestion. We added Figures 3c, 3d, 4c, and 4d for inductances, quality factors (Q-factors), and coupling coefficients (k-factors) of the TF₁–TF₄. Furthermore, by confirming these extracted values over the entire 50–75 GHz range, we have fully validated the high-frequency performance of the proposed transformers.

We revised the Figures 3 and 4.

Response 6: We have added a detailed explanation for the discrepancy between the simulated and measured S22 in Section 3. The discrepancy between the measured and simulated S22 is mainly due to imperfect modeling of the parasitic capacitances in the output RF test pads and routing lines.

We added the sentence as follow: “The discrepancy between the measured and simulated S22 is mainly due to imperfect modeling of the parasitic capacitances in the output RF test pads and routing lines.”

Response 7: Following your advice, we removed several outdated references [5–9, 22] and added the most recent state-of-the-art studies such as: ref. 17. Wei, Q.; Yang, C.; Liu, X.; Wang, Y.; Jin, J.; Zhou, J. A Millimeter-Wave Two-Way Series-Doherty Power Amplifier With Transformer-Based Second-Order Output Network. IEEE Trans. Microw. Theory Techn. 2026, 74, 4296–4309.

Response 1: Thank you for pointing this out. We apologize for the typographical inconsistencies. We have thoroughly checked the entire manuscript and figures to ensure that all symbols, particularly the transistor designators (e.g., M₁, M₂), are perfectly consistent.

We added the Table 1 as follow:

Table 1. Transistor design parameter of the proposed VGA.

Table 1 summarize the transistor design parameters of the proposed VGA. All transistors employ a channel length of 65 nm. The total transistor width of the input stage (M₁-M₂), IIVG stage (M₃-M₆) and output stage (M₇-M₈) are 50 μm, 39 μm and 50 μm, respectively. The input and output stages are biased at 0.47 V and 0.42 V, respectively, while the IIVG stage employs a bias voltage ranging from 0.815 V to 1.0 V to achieve gain control through current steering. Owing to the current-reuse architecture, the input stage shares the same quiescent current of 7.4 mA with the IIVG stage. The output stage consumes a quiescent current of 7.6 mA.

Comments 2: The design techniques adopted in this work were commonly reported in the previously published works. The authors shall provide more theoretical analysis on the parameter selection to strengthen the contribution.

Comments 3: A small-signal modeling on the intrinsic parameters may help to improve the procedure of parameter selection.

Response 2 & 3: We highly appreciate the reviewer's constructive guidance. We agree that providing a detailed procedure of parameter selection based on small-signal modeling is essential to highlight the academic contribution and technical depth of our work.

In the revised manuscript, we have added a dedicated parameter selection procedure in Section 2.4 directly linked to our small-signal model and intrinsic parameters (such as  and ).

1. Unique Contribution Over Prior Arts: While impedance-invariant current steering and current-reuse are independently known, their co-design at millimeter-wave frequencies represents a significant contribution. Conventional IIVGAs inherently suffer from a severe trade-off; they either consume excessive DC power to achieve sufficient gain (e.g., 67.2 mW in [13] and 126 mW in [16]) or exhibit poor gain performance to maintain phase invariance.

To break this trade-off, our proposed design seamlessly integrates a transformer-based current-reuse scheme with the IIVG current-steering structure (newly highlighted in Section 2.1, Design Considerations). This co-design allows the input and variable gain stages to share the identical bias current, preventing gain degradation while maintaining power efficiency (15 mW).

2. Parameter Selection Procedure Based on Small-Signal Modeling: As explained in the newly added sentences in Section 2.4, we conducted a parameter selection procedure to optimize both phase invariance and power efficiency: Based on this theoretical small-signal analysis, the parameter selection procedure was meticulously conducted to optimize both phase invariance and power efficiency. To mathematically eliminate the phase variation according to (2) and (3), it is strictly required to equalize the intrinsic parasitic gate-to-drain capacitances . Therefore, the main and steering transistors M₃–M₆ were selected to have identical widths of 39 μm. To optimize the gain, linearity, and power consumption, a quiescent current of 7.4 mA was selected.

We have summarized these physical parameters clearly in the newly added Table 1. We believe these additions justify our design choices and significantly strengthen the overall contribution of our work.

We added and revised the sentences as follow:

2.1. Design Considerations

In 65-nm CMOS technology, designing at 60 GHz poses inherent challenges, such as a low intrinsic gain and significant parasitic capacitances that severely degrade both stability and gain. Furthermore, conductive substrate losses typically limit the efficiency of passive components. To overcome these limitations, we utilized the thick top metal layers provided by the 65-nm process to implement high-Q transformers and inductors, minimizing losses. Additionally, rather than cascading multiple stages to compensate for the low intrinsic gain, we adopted a transformer-based current-reuse technique combined with an impedance-invariant current-steering structure. These design choices prevent the gain degradation commonly found in traditional phase-invariant VGAs. Consequently, the proposed architecture enhances gain, stability, and power efficiency within a limited power budget, while maintaining a constant insertion phase during gain tuning.

2.3. Transformer-Based Current-Reuse Topology

At this dc current path, a bypass capacitor, C₂, is connected to the center tap of TF₂ to establish an ac ground. This ensures that the common source nodes of M₃–M₆ are effectively grounded at RF frequencies, allowing them to operate as common-source amplifiers.

2.4. Impedance-Invariant Variable Gain Stage

Furthermore, a current pathing through M₃–M₆ is reused for M₁ and M₂ and M₃–M₆ are operated as common source amplifiers.

Now, the gain of the IIVG stage under  is reduced to

According to (4), the voltage gain of the IIVG stage is solely determined by the effective transconductance difference, . Moreover, owing to the proposed transformer-based current-reuse scheme, this gain control is performed without additional DC power consumption, as the bias current is completely reused between the stacked stages. During operation, the gain is continuously tuned by complementarily adjusting the dc gate bias voltages, V_GP and V_GN in Figure 1. Because this complementary current-steering mechanism structurally keeps the sum of the parasitic capacitances constant across all nodes, the VGA can achieve significant gain attenuation without altering the input and output impedances. This unique characteristic ensures that the wideband impedance matching and the insertion phase remain completely invariant across the entire gain tuning range.

Based on this theoretical small-signal analysis, the parameter selection procedure was meticulously conducted to optimize both phase invariance and power efficiency. To mathematically eliminate the phase variation according to (2) and (3), it is strictly required to equalize the intrinsic parasitic gate-to-drain capacitances . Therefore, the main and steering transistors M₃–M₆ were selected to have identical widths of 39 μm. To optimize the gain, linearity, and power consumption, a quiescent current of 7.4 mA was selected.

Comments 4: It would be nice if the authors can include a figure-of-merit (FoM) in the comparison table. This will help to identify the major advantage of the proposed design as compared to the state-of-the-art works.

Response 4: Thank you for pointing this out. We have defined and included a Figure-of-Merit (FoM) in Table 1 (Table 2 in revised manuscript) that balances gain, phase error, tuning range, and power consumption. As shown in the updated table and detailed in the revised Section 4, the newly added FoM clearly demonstrates that our VGA achieves a superior overall balance—specifically a low RMS phase error and wide gain control range with minimal power consumption—compared to the state-of-the-art works.

We added the sentences as follow:

For the performance comparison of the VGAs, figure-of-merit (FoM) is defined as (5)

As a result, the proposed VGA demonstrates a highly competitive FoM compared to most prior arts, successfully combining a low RMS phase error, low power consumption, high forward gain, and a wide gain control range. Although other VGAs, such as those in [12] and [18], show numerically higher FoMs, their applicability is compromised; the design in [12] results in a negative gain of -3.8 dB, and the VGA in [18] exhibits limited power-handling capabilities.

Response 1: Thank you for pointing this out. We have added proper concrete references [Ref 8, 9] in Section 1 to robustly support the statement regarding the importance of VGAs in phased-array transceivers.

Comments 2: Section 2 - A table showing the transistor characteristics (W/L, bias, etc.) would be beneficial to further understanding the design of the VGA more.

Response 2: Thank you for pointing this out. Thank you for the suggestion. We have newly added Table 1 in Section 2, which clearly summarizes the key characteristics of all transistors, including their W/L ratios, bias voltages, and quiescent currents.

We added the Table 1 as follow:

Table 1. Transistor design parameter of the proposed VGA.

Table 1 summarize the transistor design parameters of the proposed VGA. All transistors employ a channel length of 65 nm. The total transistor width of the input stage (M₁-M₂), IIVG stage (M₃-M₆) and output stage (M₇-M₈) are 50 μm, 39 μm and 50 μm, respectively. The input and output stages are biased at 0.47 V and 0.42 V, respectively, while the IIVG stage employs a bias voltage ranging from 0.815 V to 1.0 V to achieve gain control through current steering. Owing to the current-reuse architecture, the input stage shares the same quiescent current of 7.4 mA with the IIVG stage. The output stage consumes a quiescent current of 7.6 mA.

Comments 3: Section 2.4 - small typo on line 2 of page 6 with Vin+ instead of Vout+

Response 3: Thank you for pointing this out. The typo has been corrected to "V_out".
We corrected sentence as follow: “The drains of M3 and M4 are tied together to drive the positive output node V_OUT⁺”. Thank you again for your valuable feedback.

Comments 4: Last paragraph in this section, the first sentence says "remains constantly zero". This phrasing is awkward and clumsy. Consider revising.

Response 4: Thank you for pointing this out. The awkward phrase "remains constantly zero" has been revised to "is maintained near zero" to improve readability.

Comments 5: Section 3 - Figure 9 should not be split across page 8 and 9. Put it side by side or move it down more.

Response 5: Thank you for pointing this out. We have adjusted the formatting and layout of the manuscript. Figure 9 is now placed side-by-side to optimize page space and prevent awkward page breaks.

Comments 6: Figure 10 could also be made to be side by side like Figure 9 to reduce wasted page space.

Response 6: Thank you for pointing this out. We have adjusted the formatting and layout of the manuscript. Figure 10 is now placed side-by-side to optimize page space and prevent awkward page breaks.

Comments 7: Section 4 - Table 1 would be better illustrated with this work's results being bolded for emphasis and easy visual comparison.  Some method to easily see which of the comparisons has the best results would be nice as well. Additionally, more discussion on the comparisons and what design choices made in this work give these results more meaningful properties than the other SOA would be beneficial.

Response 7: Thank you for pointing this out. In Table 1, our work's results have been bolded. Additionally, we have highlighted the best results in each row by bolding the values to allow readers to easily identify the superior performance metrics. Also, we added more discussion how our specific design choices overcome the critical limitations of prior arts. The proposed VGA demonstrates a highly competitive FoM compared to most prior arts, successfully combining a low RMS phase error, low power consumption, high forward gain, and a wide gain control range.

We added the sentences as follow:

For the performance comparison of the VGAs, figure-of-merit (FoM) is defined as (5)

As a result, the proposed VGA demonstrates a highly competitive FoM compared to most prior arts, successfully combining a low RMS phase error, low power consumption, high forward gain, and a wide gain control range. Although other VGAs, such as those in [12] and [18], show numerically higher FoMs, their applicability is compromised; the design in [12] results in a negative gain of -3.8 dB, and the VGA in [18] exhibits limited power-handling capabilities.

Comments 8: Overall, the paper is well put-together and flows nicely. Some minor tweaks would really finalize the paper. Section 2 feels a little lacking but not by much. It could use more details on how the design utilizes the properties of the CMOS process to its benefit or how/what integrated circuit technology choices were made to implement this design. Things like this would make it feel more fleshed out.

Response 8: Thank you for the comment. In the revised manuscript, we have expanded Section 2.1 (Design Considerations) to explicitly discuss the characteristics of the 65-nm CMOS process at 60 GHz and how our design strategically addresses its inherent limitations. Specifically, we added a new paragraph detailing two major technology-aware design choices: 1. To overcome conductive substrate losses, we actively utilized the thick top metal layers provided by the 65-nm process to implement high-Q transformers and inductors, thereby minimizing resistive losses. 2. To combat the low intrinsic gain and significant parasitic capacitances without increasing the power budget, we deliberately avoided cascading multiple power-hungry stages. Instead, we adopted the transformer-based current-reuse technique combined with an impedance-invariant current-steering structure.

We added the sentences as follow:

In 65-nm CMOS technology, designing at 60 GHz poses inherent challenges, such as a low intrinsic gain and significant parasitic capacitances that severely degrade both stability and gain. Furthermore, conductive substrate losses typically limit the efficiency of passive components. To overcome these limitations, we utilized the thick top metal layers provided by the 65-nm process to implement high-Q transformers and inductors, minimizing losses. Additionally, rather than cascading multiple stages to compensate for the low intrinsic gain, we adopted a transformer-based current-reuse technique combined with an impedance-invariant current-steering structure. These design choices prevent the gain degradation commonly found in traditional phase-invariant VGAs. Consequently, the proposed architecture enhances gain, stability, and power efficiency within a limited power budget, while maintaining a constant insertion phase during gain tuning.