Evolution of Stack Architecture and Interconnect Technology for Detector Array Chips

Abstract

The detector array chips can be used to capture the transient space-time signal of the pulse radiation field. It is mainly composed of a photoelectric array detector and a readout circuit. However, the metal leads used to connect the detector and the readout circuit have long spacing. This can easily introduce additional delays, resulting in a decrease in the response performance of the chip, which cannot meet the goal of simultaneous transmission of ultra-fast detection signals. In recent years, the rapid development of three-dimensional interconnect technology has enabled the chip to achieve shorter interconnect spacing, smaller parasitic parameters and smaller delay time, thereby improving system response performance. The integrated detector array chips composed of three-dimensional interconnects has the advantages of fast signal interconnection transmission speed, high bandwidth, process compatibility and functional expansion compared with the traditional planar architecture. At the same time, there are some limitations and challenges. Therefore, this paper mainly reviews the evolution characteristics of the stacked architecture of the detector array chips, the process development and the nanosecond-level transmission integration challenges. This paper effectively incorporates the three into a unified framework. This provides a solution for the realization of integrated nanosecond detector array chips. Furthermore, it promotes the application and expansion of the chip in the pulse radiation field diagnosis technology.

1. Introduction

The detector array chips can be used to capture the transient space-time signal of the pulse radiation field, which is mainly composed of a photoelectric array detector and a readout circuit. The response time accuracy of the photoelectric array detector is in the order of nanoseconds or even picoseconds. The signal transmission time accuracy of the readout circuit is usually in the order of nanoseconds. However, the interconnects that connect the two introduce additional delays due to the limitations of application scenarios and connection methods, which in turn leads to prolonged chip response time and decreased signal integrity. With the existing planar architecture schemes, it is generally difficult to achieve the time accuracy of ‘response–transmission–readout’ three-level transmission with nanoseconds, especially for the interconnection transmission of tens of nanoseconds. In order to break through the bottleneck of interconnection, three-dimensional stacking and integration technology has become the main solution. It makes it possible for the detector array chips to achieve faster time response accuracy of detectors, interconnects and readout circuits by stacking architecture and integration [1,2,3,4,5]. At present, the mainstream integration methods are mainly hybrid integration and monolithic integration. Monolithic integration belongs to the front process, which has the advantages of small chip area, small parasitic parameters and fast signal interconnection transmission speed. The disadvantage is that the overall design is complex, high-cost and time-consuming. Hybrid integration belongs to the post-chip process. Its advantages are its low cost, short cycle, process compatibility and high flexibility. The disadvantage is that the chip is bulky and the signal delay is high [6,7,8,9,10,11]. Although the integration of detector array chips is different, its architecture evolution trend is significantly similar to the processing method. Both of them rely on the CMOS—compatible process to realize the integration of the detector and the readout circuit, and optimize the interconnection line through three-dimensional stacking technology, thereby improving the signal interconnection transmission capacity of the chip [12,13]. Ultra-fast detection requires the readout and conversion of pixel signals in a very short time, and its spatial and temporal resolution is affected by many aspects such as power consumption and thermal management. The faster the readout and conversion speed, the higher the design requirements for the chip operating frequency and high-speed digital-to-analog converter, and there is a significant increase in power consumption.

Although existing research has verified the superiority of three-dimensional interconnects in inter-chip signal transmission and solved the problem of interconnect delay, a summary and comparison of the evolution characteristics of the integrated architecture, process development and nanosecond-level transmission challenges are still lacking. Although there have been reviews focusing on the development of integrated image sensors, they mostly focus on architecture and circuit design, and lack systematic investigation from the perspective of integrated process details and inter-chip nanosecond signal transmission synergy. In addition, there is still a lack of a unified solution framework for key issues such as process and loss of different integrated architectures under the requirements of nanosecond-level transmission. Therefore, this paper incorporates the evolution characteristics of stacked architecture, three-dimensional interconnection process and nanosecond signal transmission challenges into a unified framework to provide a technical route for high-spatial-temporal-resolution diagnostic systems. This paper mainly discusses the stack architecture evolution, process development and nanosecond-level transmission integration challenges of detector array chips. The structure of this paper is as follows: In the first section, the stack architecture evolution and characteristics of detector array chips are systematically investigated with image sensors and silicon photomultiplier (SiPM) detectors as representatives. The second section focuses on the analysis of the development status of three-dimensional interconnection technology and the application possibility of nanosecond-level transmission. The third section deeply analyzes the challenges of architecture comparison, theoretical calculation and collaborative design under nanosecond array detection targets. Finally, the fourth section summarizes the full text and looks forward to future research directions. The purpose of this paper is to fill a gap in the existing literature from the perspective of architecture evolution and signal transmission coordination, and to provide a technical route and process support for the realization of integrated nanosecond detector array chips.

2. Stacking Architecture Evolution of Detector Array Chips

With the growth of high spatial and temporal resolution, high data transmission capability and chip integration requirements, the interconnection bottleneck problem between the detection unit and the processing circuit of the detector array chips of the traditional planar integrated architecture has gradually become prominent. Timing response, pixel density, data readout rate and function expansion are gradually approaching the physical limit. In order to break through the above bottlenecks, three-dimensional stacking and integration technology has become the core development trend of the new generation of detector array chips due to its unique three-dimensional interconnection advantages. The technology vertically integrates photoelectric detection, a high-speed readout circuit, a storage unit and a logic processing unit through silicon via, bump and bonding processes, and innovates in terms of system integration, data bandwidth and energy efficiency ratio. Under this framework, the integrated detector array chips gradually realizes the logical and physical integration of the system with the ‘sensing–storage–processing’ collaborative architecture as the core, thereby achieving higher detection accuracy of the system [14,15,16]. The image sensor and SiPM detector are representative devices for obtaining the transient space-time signal of the pulse radiation field. Both of them are composed of array detectors and readout circuits, which can effectively compare the similarities and differences in their integrated architectures and processes. This has important reference significance for the research and application of nanosecond-level same-level transmission. Therefore, the following will focus on the evolution trend and key technologies of the integrated architecture for detector array chips. Figure 1 is an integrated schematic diagram of array detection. The left side is a two-dimensional plane integrated architecture, and each circuit module is arranged in the same plane according to the functional partition and spatial position. On the right side is the preliminary form of the three-dimensional stacked integrated architecture, in which the array detection module is located at the top layer, and the remaining functional modules are integrated at the bottom layer. The vertical electrical connection between the two is realized through the three-dimensional interconnection line. The three-dimensional structure not only effectively shortens the interconnection distance between modules and reduces the signal transmission delay and parasitic effect, but also significantly compresses the plane area of the chip, which is conducive to improving integration and system performance.

2.1. Evolution Trend of Hybrid Integrated Image Sensor Architecture

In recent years, the structural design of image sensors has undergone significant changes across front-illuminated, back-illuminated and three-dimensional integrated types. Because the incident light of the front-illuminated structure needs to pass through the metal interconnect layer and the microlens to reach the photodiode, the quantum efficiency and pixel size are limited [17]. In order to break through this limitation, the back-illuminated structure flips the chip and thins the substrate, so that the light is incident directly from the back to the photodiode. This significantly improves quantum efficiency and microlens design freedom [18]. However, because its pixel photodiode and logic circuit are in the same wafer layer, it is impossible to independently optimize the compatibility of pixel size and logic circuit energy efficiency. And the noise generated by the metal wiring coupled to the pixel layer is large. Therefore, in order to optimize the above problems, three-dimensional integrated image sensors came into being [19]. Among them, the CMOS image sensor (CIS) and the single-photon avalanche diode (SPAD) image sensor are the most representative devices.

The evolution process and corresponding process details of the CIS three-dimensional stacking architecture are shown in Figure 2. As shown on the left of Figure 2a, in 2013, Sony took the lead in using TSV technology to successfully realize the vertical stacking of pixel photosensitive layers and logic circuit layers in back-illuminated CISs [20]. The pixel layer of the chip is fabricated by a 90 nm CIS process. The logic layer is fabricated by a 65 nm process. The top layer (pixel layer) integrates the pixel array, source follower, line drive circuit and analog-to-digital conversion comparator. The bottom layer (logic layer) accommodates the remaining digital control and signal processing circuits. The high-speed interconnection between the top layer and the bottom layer is realized by the TSV located next to the row/column driver. Its number is similar to the number of row and column control signals. The chip has a size of 1/4 inch, a pixel size of 1.12 × 1.12 μm² and an effective pixel resolution of 8 million. It can achieve a real-time output of 30 fps at full resolution. The power consumption under typical working conditions is 185 mW. The architecture has the characteristics that the ADC is placed next to the pixel array, and the TSV effectively separates the logic layer and the pixel layer. This can effectively reduce the transmission distance of the analog signal and reduce the noise interference of the multi-layer metal wiring to the pixel layer. As shown in Figure 2a (left), in 2015, Sony developed a low-noise high-speed CIS that supports dynamic-static dual-mode output using a dual-column ADC architecture [21]. The ADC layer is embedded at the bottom of the chip using three-dimensional integration technology. The data throughput is significantly increased without changing the chip area. The chip size is 1/2.7 inch. It has a 1.43 × 1.43 μm² pixel size. It has a static effective pixel resolution of 16 million and a dynamic effective pixel resolution of 400 million at 60 fps. The architecture has the characteristics and trend that the pixel layer is separated from the top layer of the chip and the number of ADCs increases. This can effectively reduce the crosstalk and dark current of the substrate to the pixels, and improve the full well capacity (FWC) and readout speed. As shown in Figure 2a on the right, in 2016, Sony developed a new generation of back-illuminated CIS through the three-dimensional stacking process of TSV and Cu-Cu bonding [22]. The chip uses a 4 μm spacing Cu-Cu bonding interconnection and is implemented by a back-channel process. Its size is 1/2.6 inch. It has a pixel size of 1.0 × 1.0 μm² and a resolution of 22.5 million effective pixels. Its bonding interface contains 3 million Cu-Cu interconnect points and no interface defects. The architecture has the characteristics of Cu-Cu bonding to shorten the interconnection distance between pixel layer and logic layer signal interconnection transmission, and an integrated ISP circuit for image processing. It can effectively reduce the pixel size and improve the pixel resolution while expanding the CIS function. At this point, the CIS interconnection process is gradually transformed into Cu-Cu bonding, and the functional integration is gradually extended to “sensing-processing”. As shown in Figure 2a on the right, in 2017, Sony designed and implemented a three-layer stacked frame storage 3L-BI-CIS integrated storage DRAM. The sensor has the characteristics of high-speed readout of internal data and high-speed transmission of external accessible interfaces. It can achieve a high frame rate output of CIS [23]. The top layer of the chip (pixel array) uses a 90 nm CMOS process. The middle layer (DRAM) uses a 30 nm DRAM process. The logic substrate layer (data processing) is realized by a 40 nm logic process. The three functional layers have the same chip area, and the adjacent layers are interconnected by TSV. The chip size is 1/2.3 inch. It has a 1.22 × 1.22 μm² pixel size and 19 million effective pixel resolution, and the DRAM capacity is 1 Gb. It can realize the readout of 19 million pixels at the speed of 120 fps, and can realize the recording of slow-motion video at 960 fps. The three chip function layers of the architecture are clear, the area is equal, and the process is compatible. It can effectively achieve function expansion and frame rate improvement through TSV, and realize the “sensing-storage” of CIS.

The evolution process and corresponding process details of the CIS three-dimensional stacking architecture are shown in Figure 2. The process has the following trends: First, in the functional layer, the trend is multi-layer and the pixel layer is at the top. The second trend is an ADC parallel multi-list in circuit structure composition. The third is high-quality Cu-Cu multi-interconnection on interconnection lines. The fourth is the integration of sensing, storage and computing in function expansion. This feature of the trend has also been mutually verified in the literature [24,25].

The imaging principle of the SPAD image sensor is different from that of CIS based on the photoelectric effect of the photodiode array. It is based on single-photon avalanche diode array Geiger-mode photon counting imaging. It is often composed of a detector array, a quenching circuit and a readout circuit, which is more complex than the CIS structure. However, the integrated architecture evolution of the SPAD image sensor has similar characteristics to CIS. Both of them use bonding and other interconnection processes to integrate the SPAD photosensitive layer with the logic processing layer, thus breaking through the problems of the small fill factor, high dark count rate and low photon detection efficiency of traditional front-illuminated planar SPAD image sensors [26,27]. In 2015, Pavia J M et al. [28] realized a new stacked linear array SPAD image sensor using a CMOS 130 nm process. The SPAD array of the chip is located at the top, the logic circuit layer is located at the bottom, the interface layer is realized by direct bonding at a distance of 4 μm, and the middle is connected to the bottom by a TSV with a diameter of 1.2 μm. The overall pixel array is 1 × 400. The chip size is 0.77 × 5 mm², which is slightly larger than CIS. However, it has a high fill factor of 23.3% and a photon detection efficiency of 12%. The SPAD pixel size is positively correlated with the filling factor. The larger the size, the larger the filling factor, and the better the signal-to-noise ratio of the image. However, the size being too large will bring about a decrease in resolution and response speed. Therefore, the SPAD image sensor is gradually compromised based on the difference in application scenarios. It continues to grow in the direction of smaller pixel pitches and larger array sizes [29], and gradually integrates computing and other functions. In 2024, Wang Z et al. [30] of the Chinese Academy of Sciences designed and implemented a SPAD image sensor for low-light imaging using a three-dimensional stacked architecture and microlens technology. The top layer of the chip SPAD array is implemented in a 180 nm process, and the bottom layer of the pixel circuit and other modules is implemented in a 130 nm process. The two are vertically connected at the pixel level through Cu-Cu hybrid bonding, and the IO signal is output from the top layer through hybrid bonding and TSV. The overall pixel array is 64 × 128 and the size is 21 × 21 μm². The chip has a high fill factor of 38%, a high dark count rate of 41.5 cps, and excellent low-light imaging (6 × 10⁻⁴ lux) performance, fully realizing the advantages of integrated sensing, storage and computing. In short, the three-dimensional architecture evolution trend of the SPAD image sensor is essentially the same as CIS. They are mostly implemented in a hybrid integrated manner. This has the advantages of back-illuminated three-dimensional stacking and a bonding interconnection process, and the commonness of gradually decreasing pixel spacing and outstanding performance [31]. However, due to the differences in their principles and application scenarios, there are some differences in the technical details of the two. First, the front-illuminated structure of the SPAD image sensor is superior to the back-illuminated structure in terms of photoelectric detection efficiency and wavelength response. It has a two-pixel structure to improve its dynamic range [32]. Second, due to the area limitation of the detector array, the integrated size of the SPAD image sensor is larger than that of CIS [33]. This helps to achieve a single-photon detection array with high fill factor and low crosstalk, but its resolution is limited. The stack architecture and application of the SPAD image sensor are shown in Figure 3. The left of the diagram is the comparison of the evolution of the planar architecture to the stacked architecture of the SPAD image sensor. The two figures on the right are the circuit architecture, layout and physical test results of two SPAD image sensors designed and manufactured by stacking architecture. These fully verify the optimization of the SPAD sensor stack architecture for dark noise performance and imaging quality, especially in low-light imaging applications. As shown in Figure 3, the pixel area of the SPAD image sensor is larger than that of the other circuit structures. Therefore, in the actual design process, careful consideration must be given to the impact of its structural distribution on the response speed.

Hybrid integrated image sensors can be classified according to the differences between stacked architecture and interconnects. One is the separate stacking of detector and readout circuit. The detector and the readout circuit belong to different chips or wafers, using mixed processes such as TSV, RDL, bumps and bonding. Stacking is implemented according to the architecture of the top-level pixel array, the middle silicon intermediate layer, and the underlying logic processing chip, as shown in Figure 4a. The architecture can support high dynamic range and intelligent image processing, and is suitable for high-end mobile devices and machine vision systems such as Samsung ISOCELL HP series HP2-200MP [34,35]. The second is the Cu-Cu interconnection stacking of the detector and the readout circuit. The chip or wafer size is matched, and the interconnect lines are located around or in the middle of the chip and are mainly connected in a straight line. The interconnect size is about 1 μm. It can integrate the pixel layer, DRAM buffer layer and logic processing layer vertically based on processes such as Cu-Cu bonding, and achieve an ultra-high frame rate and intelligent image processing, as shown in Figure 4b; one example is the Sony Exmor RS series sensor IMX989-50.3MP [36,37]. Thirdly, the detector is grown on the readout circuit chip. This method does not require processes such as TSV and bonding interconnection, and can directly grow MoS₂ photodetectors above CMOS readout circuits, as shown in Figure 4c. It has broadband optical response characteristics and supports flexible ultra-thin imaging systems [38,39]. The schematic diagram and details of the CIS stacking structure classification are shown in Figure 4.

2.2. Evolution Trend of Monolithic Integrated Photodetector Architecture

The basic detection unit of SiPM is also SPAD, but it is different from the structure and signal readout method of the SPAD image sensor. It is a macro pixel composed of multiple SPAD units in parallel. The output current of all the micro-elements is directly summed internally and the signal is output from the same port. Different from the hybrid integrated image sensor, the detection array and readout circuit of SiPM benefit from the same process and material to achieve chip design and processing in a monolithic integrated manner [40]. In 2014, E. Charbon et al. [41] reported the world’s first three-dimensional integrated back-illuminated SiPM. The chip is fabricated in a two-layer CMOS 130 nm process. The top layer is a double 4 × 200 linear SPAD array, the bottom layer is a 2 × 100 time-to-digital converter (TDC), and the middle is realized by Cu-Cu bonding and TSV. The chip size is 47 × 64 mm². It has a photon detection efficiency of 11% at 725 nm and a dark count rate of 1 kHz at room temperature. The design effectively divides the discrete devices into parts and realizes a monolithic integrated photodetector with a small area, small parasitic parameters and fast response. With the development of detectors and three-dimensional interconnection processes, monolithic integrated photodetectors have shown unique advantages in terms of low latency, high response, and fast transmission. They can achieve shorter interconnection lines than hybrid integration, but their architecture evolution trend still follows the rules of layered stacking and inter-chip interconnection. According to the design requirements, only the interconnect wire is changed from the through via interconnect wire to the layout metal wire. In 2024, Li M et al. [42] adopted a complementary bipolar standard process to integrate detectors and signal processing circuits. The pre-stage unit is a SPAD array, and the post-stage is an amplifier and a logic processing circuit. The peak response of the chip is 0.462 A/W, the transmission delay is less than 41.8 ns, and the data output rate is up to 12 Mbd. The chip uses monolithic integration to integrate each functional module into a process design. This effectively solves the problems of high compatibility requirements between photodetectors and standard processes, and the difficulty of monolithic integration and process technology integration. A comparison of several integrated detector array chips is shown in

Table 1. Comparison of several integrated detector array chips.

Ref.	Chip Size	Pixel Size	3D Types	fps	Integration Types	Q	Chip Types
[20]	1/4 inch	1.12 × 1.12 μm2	Only TSV	30	CoW	/	CIS
[21]	1/2.7 inch	1.43 × 1.43 μm2	Only TSV	60	CoW	/	CIS
[22]	1/2.6 inch	1.0 × 1.0 μm2	TSV, Cu-Cu	/	WoW	/	CIS
[23]	1/2.3 inch	1.22 × 1.22 μm2	Only TSV	960	CoW	/	CIS
[28]	0.77 × 5 mm2	/	TSV, Cu-Cu	/	CoC	23.3%	SPAD
[30]	/	21 × 21 μm2	TSV, Cu-Cu	/	CoC	38%	SPAD
[41]	47 × 64 mm2	/	TSV, Cu-Cu	/	/	/	SiPM

.

2.3. Integrated Structural Features and Challenges

Both image sensors and SiPM detectors can achieve performance breakthroughs using a layered three-dimensional stacked architecture. However, CIS effectively improves quantum efficiency and dynamic range by stacking inverted pixel layers and readout circuits. The aim is the optimization of the planar architecture, mainly to achieve high-density interconnection such as TSV. The SPAD image sensor is vertically stacked by the array layer and the logic circuit to improve the fill factor and detection efficiency. The aim is architecture reconstruction, mainly to achieve high-density connections by use of bonding. The SiPM detector effectively improves responsivity through layered stacking or logical cascade of modules. It is mainly connected by Cu-Cu bonding, TSV and layout metal wire. The actual architecture design will be effectively mapped according to the difference between application scenarios and manufacturing processes. However, its unit interconnection cost is high. In contrast, monolithic integration requires collaboration with multi-material systems, power networks, and thermal budgets. Its manufacturing complexity is high and its scalability is weak, so it is difficult to upgrade a functional module independently. The overall integration is limited by defect density and thermal stress accumulation, and its typical yield is lower than that of hybrid integration. However, monolithic integration has advantages in unit area cost. Therefore, hybrid integration is suitable for scenarios that are cost-sensitive and require fast iteration. Monolithic integration is suitable for advanced applications that pursue extreme integration and low power consumption [43,44,45,46]. Against the background of the existing front-end detection arrays and back-end readout circuit chips, the integration of discrete detector array chips needs to comprehensively consider various factors such as detector structure, interconnection process method, process feasibility and performance testability.

3. Interconnection Process Development of Array Detection Imaging

Three-dimensional interconnect technology is a key technology to break through the bottleneck of high computing power, high bandwidth, low power consumption and low delay of high-end chips, and it is also one of the significant features of the post-Moore era of integrated circuit development. It improves the transmission performance of signal interconnection by shortening the interconnection scale and reducing the chip volume. In turn, the function integration, performance improvement, cost reduction and efficiency increase of the chip under multi-material and multi-process configurations are realized [47]. According to the position of the three-dimensional interconnection process on the process scale, it can be divided into three directions: vertical, horizontal and interface. The vertical direction is mainly through via, including through Si via (TSV), through glass via (TGV) and so on. The horizontal direction is mainly the redistribution layer (RDL) and the bridge. The interface direction is mainly bump and bonding, etc. [48,49]. Figure 5 shows the schematic diagram of the three-dimensional interconnection and through via process. The position and function of the three-dimensional interconnection process are shown in the left subfigure of Figure 5. For example, TSV is a vertical interconnection line, which can optimize the IO position through RDL to achieve close integration of the chip. Most of the existing integrated chips are implemented using a variety of three-dimensional interconnection processes.

3.1. Vertical Through via

TSV and TGV are the two most common through via structures, which are formed by etching the silicon/glass interlayer to form through vias and depositing interconnect metals such as copper in the vias to achieve vertical interconnection. The key parameter depth–width ratio is mainly limited by the process method, through via structure and morphology. It can directly affect the density and electrical properties of chip integration. The through via structure mainly includes a single-ended structure, a coaxial structure, a differential structure and a shielded differential structure, as shown in the right diagram of Figure 5. The signal interconnection transmission of the single-ended structure depends on the common return path. It is easy to produce electromagnetic radiation. It is generally suitable for low-frequency and low-speed scenes and is the most common through via structure. The coaxial structure has low emission radiation, small parasitic inductance and good impedance matching, which is suitable for high-frequency electromagnetic interference-sensitive scenarios. The differential structure has small common-mode noise and large layout area, which is suitable for high-speed digital signal interconnection transmission. The signal interconnection transmission performance of the shielded differential structure is the best. However, it has large parasitic capacitance and a large layout area, which is suitable for ultra-high-speed signal interconnection transmission and three-dimensional high-density interconnection. The through via morphology mainly includes cylindrical, quadrilateral, hourglass-shaped and conical types. Among them, cylindrical through vias dominate the TSV implementation, and conical through vias are widely used in TGV [50,51,52,53,54,55].

At present, the conventional depth-width ratio of TSV ranges from 1:1 to 20:1. Among them, 10:1 is the industrial baseline. through vias with smaller apertures and higher aspect ratios are often used in high-bandwidth memory chips and cores that require higher interconnect density. With the stringent requirements of AI and high-performance computing for higher current and better heat dissipation, TSV technology is shifting from a “higher aspect ratio” to a “larger diameter” paradigm [56,57]. In order to realize the further development and application of TSV, various research units focus on the realization of high-quality defect-free HAR-TSV process in process and structure. Among them, Xiong Z et al. [58] successfully prepared a TSV array with a depth-to-width ratio of 10:1 and a diameter of 1 μm by the pre-wetting optimization method. This helps to achieve non-porous super-filling of small TSVs. Li K et al. [59] successfully prepared a non-porous filled TSV based on a new electroplating method of DMP-II. Its size is 3.0 μm × 45 μm, and the aspect ratio is 15:1. This method is helpful to realize non-porous filling TSV with ultra-high aspect ratio. Ni Z et al. [60] successfully prepared a 4 μm × 50 μm defect-free TSV by a metallized filling wet process. This verifies the advantages of the wet process in defect-free filling. Jiao B et al. [61] prepared a TSV with a hollow tungsten structure with a size of 5.32 μm × 108.2 μm, an aspect ratio of 20.3:1, and an array size of 640 × 512, which can effectively improve the thermal stress. Jiang H et al. [62] prepared a TSV with a diameter of 150 nm and an aspect ratio of 9.25:1 by electron beam induced deposition. Fukushima T et al. [63] realized nanoarrays with a diameter of 0.8 μm and a depth of 15 μm, and the results effectively demonstrated the arrival of nanopore scale. At present, similar processes are only limited to laboratory research and development, and have not been put into the market on a large scale. However, Wang J et al. [64] predicted that the diameter and spacing of TSVs are expected to be smaller by 2030 as the nano-process nodes advance. When the through via size gradually overlaps with the process size, the new production design method is innovated. Figure 6 shows the corresponding characterization of three-dimensional interconnection and through via process.

TGV can achieve a larger aspect ratio than TSV due to its unique advantages of a low thermal expansion coefficient and good chemical stability. Andriukaitis D et al. [65] formed a TGV with an aperture less than 1 μm and an aspect ratio greater than 500:1 by combining a femtosecond laser GHz pulse and a beam. The Xiamen Yuntian Semiconductor [66] used ultra-fast laser to form a TGV with a depth of 520 μm and a diameter of 7 μm, corresponding to a depth-to-width ratio of 520:7 or 70:1. However, the glass is brittle and prone to cracks. Stpak et al. [67] used ultra-fast laser to prepare a TGV with pore size less than 50 μm and an aspect ratio of 24:1. The repetitive pulse process proposed by them can achieve 0.95 mm large depth, a small defect blind via and no cracks. This makes it possible to achieve crack-free, higher-aspect-ratio and smaller through vias in the later stage. In

Table 2. Comparison of depth-to-width ratio data for TSV/TGV.

Ref.	Via	HAR	Diameter/μm	Depth/μm	Year	Institute
[62]	TSV	9.25:1	0.15	1.39	2026	Fudan University
[63]	TSV	/	0.8	15	2021	GINTI, NICHe
[58]	TSV	10:1	1	10	2025	City University of Hong Kong
[60]	TSV	25:2	4	50	2025	Fudan University
[59]	TSV	15:1	3.0	45	2025	Xiamen University
[61]	TSV	20.3:1	5.32	108.2	2024	Institute of Microelectronics
[65]	TGV	>500:1	<1	500	2025	Ekspla
[66]	TGV	520:7	7	520	2024	Xiamen Yuntian Semiconductor
[67]	TGV	24:1	20	450	2025	Poland
[62]	TSV	9.25:1	0.15	1.39	2026	Fudan University

, the aspect ratio data of TSV/TGV are compared.

The reliability and signal integrity of through via structures are highly dependent on high-quality metal filling. Although Cu and Sn are widely used as traditional filling materials, they still face challenges such as filling defects, thermomechanical stress and high-frequency loss. To this end, researchers are committed to improving the filling quality through process optimization and the introduction of new composite materials in order to achieve the goal of low porosity, high thermal conductivity/conductivity and low transmission loss [68,69]. Vandana Boora et al. [70] used the composite structure of multi-walled carbon nanotubes (MWCNTs) and copper as the inner and outer filling layers of coaxial vias to reduce the signal insertion loss, which provides a new idea for high-density interconnection design.

3.2. Horizontal Rewiring Layer and Bridging

The RDL is a key interconnection technology that uses a metal wiring layer to redistribute the chip input/output (I/O) pad position from the original area to a specified position on the chip surface. This technology provides flexibility for chip re-layout and interconnection between different chips by changing the pad layout. Its implementation strategies mainly include the Damason method and the semi-addition method. The key parameter of the RDL structure is its line width/line spacing (L/S). At present, the mainstream process size is on the order of microns (about 2 μm), and it shows a trend of continuous miniaturization. In advanced packaging applications, the L/S of RDL has entered the submicron level and is gradually approaching the feature size of the wafer fabrication process [45,71,72,73,74]. Pinho N et al. [75] realized RDL stacking with L/S = 1000 nm by the full-function semi-addition method, and superimposed L/S = 1600 nm. When RDL is separated from the functional layer structure to achieve multi-layer superposition, it is generally described as “RDL intermediary layer”. It includes two parts: an RDL wiring layer and an insulating dielectric layer. It is a physical intermediate layer substrate with the core function of providing high-performance RDL, which is mainly used for high-performance computing. The backside BS-RDL and the column suspension bridge PSB are two RDL-based structures that are updated and iterated as the application scenario upgrades. BS-RDL [76] is the layout of the redistribution layer on the back of the structure. It is mainly used in the scene of enhanced heat dissipation on the back to increase the effective heat dissipation and high reliability of the overall system. The column suspension bridge PSB is a laminated RDL structure developed by Japan Chiplet Integrated Platform Alliance based on RDL. This scalable structure is a powerful solution to meet the inter-chip high-channel data transmission capability, which can achieve a transmission rate of no less than 10 Gb/s. Because the RDL structure is prone to chip warping due to thermomechanical stress in multi-layer stacking applications, electromigration or stress migration is induced. This directly affects the reliability of interconnection and the transmission characteristics of signal interconnection. In order to optimize the RDL design and avoid the above risks, researchers have developed collaborative optimization algorithms or used the process design suite PDK for parameter prediction. Xu J et al. [77] developed a special PDK process. By comparing the simulation results with the experimental test data, the reliability of the PDK in predicting RDL performance is verified. At the same time, it is shown that reducing the thickness of the dielectric layer between the signal layer and the silicon substrate will increase the substrate loss, and increasing the thickness of the dielectric layer above the signal layer will increase the parasitic capacitance. Fan J et al. [78] realized the aided design of RDL based on ACO BPNN and NSGA-II genetic algorithm. The system has good applicability and can significantly reduce the design cost and time. The best RDL size can be displayed in the heat dissipation and other functions of the SiC MOSFET module. Such application algorithms can effectively assist the routing design of RDL.

Bridge is a miniaturized and localized interconnection intermediary layer. Compared with the traditional intermediate layer substrate, it has significant area and cost advantages. It constructs a short-distance high-speed interconnection channel by embedding underneath adjacent high-density interconnection chips. This provides ultra-high density interconnection, high transmission bandwidth and low communication delay for high-bandwidth demand scenarios such as high-performance computing chips and AI chips. Embedded Multi-die Interconnect Bridge (EMIB) developed by Intel is a typical representative of this technology. It has excellent signal integrity and low transmission loss performance. At present, the minimum metal line width/line spacing/thickness(L/S/H) commonly used in the market is 2 μm, the length of the bridging path is between 2 mm and 8 mm, the thickness of the dielectric layer is 2 μm, and the number of layers of the overall wiring of the system is usually ≤4 layers of RDL redistribution layer [79,80,81]. In order to further improve the interconnection efficiency, EMIB-TSV [82], an ultra-high-speed interconnect technology with TSV based on EMIB, realizes ultra-high-speed data transmission between chips through vertical through via structure, which can be effectively applied to high computing power scenarios. In summary, both the RDL-based interlayer and the silicon interlayer can significantly increase the number of I/O and interconnect density of the package. The process and intelligent processing of RDL are shown in Figure 7.

3.3. Interface Bumps and Bonding

Bump and direct bonding are two core technologies of chip interface interconnection. The core difference is reflected in the interconnection density and structure size. The bump realizes electrical connection through diameter, spacing and structural design. Technological evolution moved from the early Solder Ball to Cu Pillar to SLID. With the continuous reduction in diameter and spacing, the interface interconnection density is significantly improved. The diameter and spacing of the current mainstream copper column structure are about 10 μm. The most advanced copper column process size has approached the interface state of direct bonding. However, the latter can still achieve a smaller feature size (submicron) [83,84]. In the bump structure, mechanical stress is a key factor affecting the reliability of the interface. Through the establishment of the copper column bonding model and electrical performance test, the existing research proposes a method to improve the overall performance by adjusting the orientation of copper grains to optimize the interface warping behavior [85]. The evolution path from solder bump to copper pillar and then to bump-free technology is essentially to continuously break through the physical limits of interconnect density and reliability through structural innovation and process miniaturization. In 2025, Sony Tamura S et al. [86] proposed a new type of wafer back copper interconnect integrated chip. The micro bump height is less than 1 μm, the rewiring layer spacing is 0.36 μm, the line space ratio is 0.18/0.18 μm, and the electrical performance is well connected. This fully verifies its development trend and application. Figure 8 shows the development trend of bump size.

Direct bonding technology has significant advantages over three-dimensional interconnection processes such as bumps. It can achieve lower interface resistance, longer electromigration life and lower thermomechanical stress. However, it has high requirements for surface cleanliness and can easily cause interface defects. The current mainstream bonding structures include Cu-Cu bonding, SiO₂-SiO₂ bonding and Cu-SiO₂ mixed bonding. Hot pressing bonding (the bonding and annealing temperature is about 400 °C) and surface activation bonding (a room temperature process) are mainly used. The former can easily induce interface stress and warpage due to high temperature. The latter relies on plasma activation, but there is a risk of copper ion short circuiting [87,88,89,90]. In order to break through the above limitations, Kim W et al. proposed a plasma-free self-assembly bonding technology [91]. By spontaneously forming an ordered molecular layer on the surface of the medium to achieve activation, the interfacial bonding strength is significantly improved. At present, the characteristic size of the bonding interface layer has been advanced from the conventional 5 μm to the submicron level, and wafer-level direct bonding has been successfully achieved [92,93]. Figure 9 shows the bonding process and interface. However, the Cu-Cu bonding interface still faces reliability problems such as voids, electromigration and thermomechanical fatigue. First of all, voids are nanoscale voids caused by uneven roughness of bonding interface and different distribution of bonding pressure. Their existence will lead to the degradation of electrical and thermal properties at the interface, which is manifested in the increase in interface resistance and thermal resistance. In order to reduce the formation of voids, plasma activation pretreatment and a thermal annealing process are often used. However, this method has extremely high requirements for surface cleanliness and flatness. And if the annealing temperature is too high, it can easily introduce thermal stress damage. Secondly, electromigration originates from the directional diffusion of atoms at the bonding interface at high current density. The process is controlled by current density, temperature, microstructure and stress state. The smaller the interconnect size, the more significant the size effect and the more obvious the interface diffusion. At present, grain orientation is often regulated by the electroplating process or a diffusion barrier layer is introduced to inhibit electromigration. However, this can easily introduce additional process steps, and it is difficult to achieve uniform control in large-area bonding. In addition, the thermomechanical fatigue is mainly caused by the thermal stress caused by the mismatch of the thermal expansion coefficient of the interface material, which promotes the initiation and propagation of cracks at the interface under the action of temperature cycles. In order to alleviate the thermal stress, the method of adding a buffer layer or optimizing the thickness of bonding layer is often used. However, the introduction of the buffer layer will reduce the thermal conductivity and electrical conductivity. In a word, the above influencing factors are coupled and synergistic in Cu-Cu bonding, and jointly restrict the improvement of high reliability performance [94].

3.4. Interconnects and Advanced Packaging

According to the size level of the interconnection object, the integration can be divided into three types: Chip on Chip (CoC), Chip on Wafer (CoW) and Wafer on Wafer (WoW). The actual selection method is effectively divided according to the product stage, process maturity and application scenario. The effective combination of the above interconnection processes leads to the current market-oriented advanced packaging products, such as TSMC’s SOIC, Intel’s EMIB and 3D Foveros, and Samsung’s X-Cube. At present, the advanced packaging industry ecology is mainly dominated by leading enterprises at home and abroad. Representative enterprises include ASE, TSMC, JCET, Amkor, Samsung, Intel, Sony and so on. Through the layout of differentiated technical routes, enterprises have jointly constructed an advanced packaging industry map of multi-technology collaboration. According to the Yole Group’s advanced packaging technology roadmap, the three-dimensional stacked WOW spacing is synchronized into the submicron level, and the I/O spacing and RDL size of the bumps are synchronized to begin to shrink [95,96,97,98,99,100]. The scale of the global advanced packaging market will reach USD 80 billion in 2030 under the demand growth driven by artificial intelligence. The core growth areas are concentrated in the fields of advanced substrate, small-chip (chiplet) and panel-level packaging [95]. This provides a high reliability technical route for laboratory chip stacking and wafer bonding.

3.5. Comparative Analysis of Applications

For the integration of single-chip nanosecond-level transmission detector array chips, commonly used interconnection processes are mainly combinations of TSV, TGV, RDL, microbumps and Cu-Cu bonding, whereas bridging is more suitable for multi-chip integration. First of all, the through via has low requirements on the matching accuracy of the IO array of the detector and the readout circuit, and the design is flexible. Among them, TSV has high compatibility with the CMOS process, a mature manufacturing system and low cost. However, its loss and delay at high frequency are relatively large. It is suitable for scenarios with high requirements for process maturity and mass production stability. The dielectric constant and loss tangent of TGV are lower. Under the same size, the transmission delay of TGV is smaller than that of TSV, and the insertion loss is lower. It is suitable for scenarios with high frequency performance requirements. Cu-Cu bonding requires extremely high matching accuracy of the IO array. It can achieve submicron alignment accuracy and extremely short interconnect spacing, lower parasitic resistance and capacitance, lower latency and higher bandwidth density. The process selection of actual detector array chips integration needs to weigh the comprehensive requirements of delay, bandwidth, cost and IO matching accuracy. The relationship between interconnects and time accuracy is shown in

Table 3. The relationship between interconnects and time accuracy.

Types	Wire	TSV	TGV	RDL	Cu-Cu
Scale (min)	mm	nm–μm	μm	μm	nm–μm
Parasitic	High	Low–Medium	Low–Medium	Low–Medium	Low
Delay	High	Low	Low–Medium	Medium	Very low
Noise	High	Low	Low	Medium	Very low
Loss (S21)	High	Low–Medium	Low–Medium	Medium	Low
Process Complexity	Low	High–Medium	Medium	Medium	High
Reliability	Medium	High	High	High	Very high
Advantage	Flexibility	Short interconnects	Low frequency loss	Design flexibility	Lower parasitic
Limit	High parasitic capacitance	vias and crack	vias and cracks	ETC mismatch	Interfacial failure
Application	Traditional electronic unit	Ultra-high speed	High frequency	High density packaging	Chiplet heterogeneous integration

. The delay of the transmission line is proportional to the interconnection length. The delay of TSV is about two orders of magnitude less than that of the lead under the same size. The parasitic parameters are related to the interconnect geometry. The short length and small diameter of the through via make its parasitic capacitance far less than that of the lead. Generally, the parasitic capacitance of the lead is in the pico level, and the parasitic capacitance of the through via is in the fly level. The time response of the detector array chips is affected by factors such as signal delay, rise time and noise jitter. Therefore, the stacking interconnection can reduce the delay and parasitic capacitance by shortening the spacing, so that the time deviation is reduced, the rise time accuracy is improved, and the time jitter is reduced. In turn, the time accuracy of its chip is improved to nanoseconds or even hundred picoseconds.

4. Discussion

In the context of the demand for high time accuracy of array detection, the integrated design and verification of the experimental stage are generally based on CoC. Therefore, the following analysis and challenges are mainly based on the above considerations. In order to achieve the core goal of nanosecond peer-to-peer transmission, the current integrated architecture mainly includes three implementation methods. One is the separated stacking hybrid integration with the intermediary layer as the core. The second is the hybrid integration of interconnection stacking with bonding as the core. The third is monolithic integration. Among them, the separate stacked hybrid integration realizes the independent manufacturing and electrical interconnection of the detector chip and the readout circuit chip through the silicon intermediate layer or the organic intermediate layer. Its manufacturing feasibility is the highest. It benefits from the mature mass production experience and absolute process compatibility of 2.5D integration technology, and can achieve flexible design and cost-controllable chips without previous I/O size matching. Bonded interconnection stacked hybrid integration uses Cu-Cu bonding and other processes to achieve direct vertical stacking between chips or wafers. It has low parasitic parameters and is suitable for high-performance multi-functional integrated systems. But its manufacturing feasibility is medium. It requires the chip I/O to complete the size matching in the early stage of the design, and the bonding interface has a very high level of smoothness and cleanliness. Otherwise, the interface is easy to introduce thermal stress and interface defects. Monolithic integration realizes the detector and the readout circuit on the same substrate through the same process or heterogeneous epitaxy, which has the highest integration in theory. But in fact, its manufacturing feasibility is the lowest because detectors usually require special processes such as high pressure and deep depletion layers. This is very different from the standard CMOS process, with high cost, a long cycle and poor design flexibility. Therefore, in the typical application scenario where the process parameters of the detector and the readout circuit are greatly different and incompatible, the separated stacked hybrid integration has become the main technical path to achieve nanosecond-level transmission at this stage due to its advantages of process decoupling, mature equipment, flexible design and controllable cost.

Although the hybrid integration of array detection has cost and process advantages, there are still the following difficulties in the actual research process. One is the layout and intelligent optimization of the inter-chip signal interconnection transmission path. The signal interconnection transmission between the detector and the readout circuit chip is the core to realize the hybrid integrated interconnection function. It includes the input and output signal interconnection transmission structure, the path, interconnect parameters and intelligent wiring. The interconnection line is an integrated system with high reliability, short interconnection spacing and small parasitic parameters through adaptive customization design based on chip performance indicators. There is no unified reference path model. Therefore, in order to achieve the optimal target parameters of the chip, researchers combine intelligent routing to construct the optimal interconnection path and layout. At the same time, an artificial intelligence algorithm is introduced to realize the model construction, analysis and target-constrained optimal parameter recommendation of the interconnection path and layout. How to realize the interconnection path layout and intelligent optimization of integrated chips with nanosecond-level transmission as the goal needs to be effectively studied in combination with signal interconnection transmission theory and calculation, process parameter correlation and algorithm iteration.

The second is the theoretical calculation and correction of the transmission characteristics of inter-chip signal interconnection. The equivalent circuit model is the core tool to characterize the electrical and signal interconnection transmission characteristics of interconnection structures. In particular, it is widely used in the simulation of electrical parameters of three-dimensional through vias. It can be simplified into sub-models such as single through via, adjacent through via or through via network according to position and array size to analyze S parameters and insertion loss. The array signal characteristics, coupling and boundary of the detector array chips interact with each other. Based on the theoretical calculation of the adaptation model, the analysis of the overall characteristics of the array can avoid defects or compensate the performance deviation by modifying the boundary. These require comprehensive calculation, simulation, comparison and experimental verification to improve the reliability of the overall system. How to combine theoretical calculations with technical goals to give corresponding data relationships and support is a systematic project that requires comprehensive analysis and judgment by researchers.

The third difficulty involves the process integration reliability test and integrated chip performance testability. The reliability of integrated chips includes two parts: interconnection process reliability and chip performance reliability. The reliability of the interconnect process is to measure the process of through via and rewiring layer according to morphology, probe and other characterization methods, and verify whether it meets the design specifications. Second, it is necessary to test the response time, delay time, insertion loss, S parameters and other functional indicators of the integrated chip and verify whether it has ideal index parameters. This leads to the testability problem of chip performance. The difference between the integrated chip and the single chip is that the input and output of the single chip have ports, and the function is modular and easy to split, which can effectively test the functional indicators. However, it is difficult for the integration process in the integrated chip and the resulting functional indicators to correspond to ports and modules, and split them up and test them separately. The correlation directivity is not strong, so designing and implementing the performance testability and index correlation of integrated chips is very difficult.

5. Conclusions

The three-dimensional interconnection process has obvious advantages in the development of the post-Moore era. Especially when it is applied to the field of array detection, it is bound to achieve a two-way improvement in signal interconnection transmission quality and time performance. At the same time, the challenges of interconnection path layout and intelligent optimization, multi-physics theoretical calculation and correction, and reliability testing brought by volume reduction, integration improvement, and effective expansion of functions also follow. How to complete the integrated design optimization and testing in various challenges is the goal of our research, and it is also the only way to realize the integration of the same-level transmission detector array chips. As the process scale of three-dimensional interconnects gradually enters the nanometer scale, it tends to converge with the feature size of tape-out processing. In the future, chip design is expected to be deeply integrated with integrated design, so as to further shorten the interconnection distance between chips and expand chip functions and application scenarios. At the same time, under the impetus of optical co-packaging technology, the development of detector array chips is bound to move towards optoelectronic integration. This will significantly enhance its applicability in special environments. Based on the above trends, a potential research direction is the optoelectronic integrated intelligent detection chip for special environments. Its core is to realize the deep integration of detectors, readout circuits, signal processing and optical communication modules through three-dimensional heterogeneous integration and photonic interconnection technology. This direction is expected to break through the bottleneck of the current detector array chips in the trade-off between speed, power consumption and environmental adaptability.