Design and Development of a 150 kV High-Voltage Direct Current Power Supply Based on Digital Control

Abstract

To address the issues of low voltage levels and insufficient reliability in dynamic regulation and voltage stabilization in existing high-voltage power supplies for electron-curtain accelerators, this paper presents a 150 kV/30 kW DC high-voltage power supply specifically designed for electron-curtain accelerators. The main circuit employs an LC high-frequency resonant topology and a step-up transformer with eight secondary windings, utilizing a parallel step-up and series output architecture to increase the output voltage level. During the charging phase, a dual-closed-loop frequency conversion scheme combined with duty cycle feedforward is employed to accelerate charging speed, while the voltage stabilization phase utilizes hysteresis burst control to improve accuracy. Simulation results indicate that the system can charge to 155 kV in 102 ms, with a voltage ripple less than 0.1%, a linear regulation of 0.01%, and a load regulation of 0.5%. Tests on a low-voltage prototype confirmed that the power devices can achieve zero-current soft switching, with a resonant current peak of 40 A and overall efficiency reaching 96%. The accompanying filament power supply can stably output 24 V/20 A, and the closed-loop voltage regulation is stable and reliable, providing technical support for the engineering application of high-voltage power supplies in high-power electron beam accelerators.

1. Introduction

An electron curtain accelerator uses an electric field to accelerate electrons to high energies and irradiate materials with an electron beam [1]. It offers low energy consumption, high efficiency, easy control, and environmental friendliness, and is widely used in material modification, radiation curing, exhaust gas treatment, and food sterilization [2]. The accelerating power supply, as the core component of the system, determines the overall reliability and stability. Therefore, designing a high-power, high-voltage electron curtain accelerating power supply with superior performance is crucial to the development of industrialization and academic research on electron curtain accelerators [3].

Since the 1980s, high-voltage DC power supplies have primarily relied on power line frequency (PLF) power supplies, which step up low-voltage PLF AC power to high-voltage DC. While PLF power supplies offer a relatively simple circuit structure and control, their low operating frequency results in low power density, significant voltage ripple, and poor dynamic performance, limiting their application and development in high-precision fields. With the advancement of switching devices, high-frequency high-voltage DC power supplies have gradually replaced traditional medium- and low-frequency power supplies. High-frequency high-voltage power supplies employ high-frequency inverter circuits, raising the switching frequency to several thousand hertz or several hundred kilohertz. This effectively increases the power density, reduces size and weight, and broadens applicability. However, practical applications still face numerous bottlenecks: prominent insulation and electromagnetic compatibility issues in the high-frequency boost stage, high system control complexity, insufficient dynamic performance, as well as defects in power devices, such as stress concentration and relatively low reliability. These factors collectively constrain development toward higher frequencies, miniaturization, higher precision, and widespread engineering adoption [4,5,6].

To address these issues, this paper presents a digital-control DC high-voltage power supply system. Our core objective is to further optimize the control system, minimize costs, and ensure that the output voltage meets the requirements of electron curtain accelerators. We first designed the main circuit topology, employing a three-phase rectifier and an LC-type high-frequency converter charging circuit. The DC high-voltage output is generated through a high-frequency step-up followed by rectification. Next, we optimized the circuit at the control level. We implemented a closed-loop control and protection system using FPGA-based digital control. During the charging phase, we employed dual-closed-loop voltage–current frequency-conversion control combined with duty-cycle feedforward to accelerate charging, while in the voltage-regulation phase, a hysteresis burst control strategy is adopted to improve voltage accuracy. Building on this foundation, we completed the optimized design of the supporting filament power supply. To address the shortcomings of traditional LLC resonant converters—namely, slow PI control response and insufficient high-frequency noise suppression—we introduced a lead-lag compensation network. We derived the gain curve based on the resonant characteristics of the main circuit, modeled the LLC resonant converter using the extended description function method, and identified the transfer function via MATLAB sweep analysis. We tuned the compensation network through pole-zero matching. Subsequently, we built system simulation models using PSIM 2023.0 and MATLAB/Simulink 2023a to analyze key characteristics, including resonant voltage, resonant current, charging duration, and output ripple. During system development and testing, we performed performance verification separately for the main high-voltage power supply and the filament power supply. Experiments were carried out on the existing hardware platform, focusing on verifying resonance charging behavior, soft-switching operation characteristics, and the effectiveness of the digital closed-loop control algorithm. Results show that the system exhibits fast dynamic response, high voltage regulation accuracy, and stable, reliable operation. The measured output voltage of the filament power supply was 24 V, with an average output current of 20 A, and the output current and voltage were in phase, meeting the design requirements. A systematic comparison was conducted with several research results in the same field, including the 100 kV/25 mA low-ripple power supply proposed by Zhang Baoqing et al. [7], the 120 kV/100 mA compact power supply developed by Lorenz et al. [8], and the 100 kV electrostatic dust accelerator power supply from the latest 2025 study by Kalaeva et al. [9]. The comparison is shown in

Table 1. Comparison of the proposed high-voltage power supply with existing representative systems.

Parameter	This Work	Ref. [1]	Ref. [2]	Ref. [3]
Voltage Level	150 kV rated (50–150 kV adjustable); Sim: 155 kV; Exp: 24 kV (low-voltage platform)	100 kV rated (200 kV design target); Exp: 100 kV (full-voltage operation)	120 kV rated (0–120 kV adjustable, scalable to 500 kV); prototype validated	50–200 kV adjustable; Exp: 100 kV (simulation verification)
Efficiency	Peak efficiency: 96% at 24 kV/9.6 kW; design target: ≥90%	Multiplier efficiency: 93%; overall efficiency not reported	No efficiency data reported; SiC MOSFETs and ZVS adopted for high theoretical efficiency	Not reported
Output Ripple	Sim: 0.02% (31 V at 155 kV); Exp: 0.1% (25 V at 24 kV)	Exp: 0.056% (56 V at 100 kV/25 mA)	Not reported	Sim: 0.5–5% (varies with multiplier capacitance); no experimental validation
Main Topology	Three-phase SPWM rectifier + LC series resonant converter + multi-winding transformer (no voltage multiplier)	Three-phase rectifier + DC regulator + full-bridge inverter + 9-stage bipolar C-W multiplier	Buck converter + full-bridge inverter + LC resonant converter + CTT insulated transformer + voltage multiplier	Vacuum-tube resonant oscillator + multi-stage C-W multiplier
Switching Frequency	10–30 kHz continuously adjustable; Exp: 15 kHz; resonant frequency: 40 kHz (DCM-ZCS)	Fixed 25 kHz (non-adjustable)	Fixed 100 kHz (CTT topology constraint)	Fixed 20 kHz (non-adjustable)
Control Strategy	FPGA-based hybrid digital control: variable-frequency regulation, burst-mode stabilization, adaptive PLL-PFC, LLC filament control	Analog-based fixed-frequency PWM + front-end DC regulation	FPGA-based cascaded control (outer voltage loop, inner current loop)	Analog-dominant control; ESP32 for voltage monitoring only, no closed-loop regulation

.

Comparative results show that the proposed scheme offers comprehensive advantages in terms of core performance: it features a high power rating capable of meeting the high-power continuous operation requirements of industrial-grade electron beam accelerators; by employing a phased hybrid strategy combining digital control and variable-frequency regulation, it balances charging speed with voltage stabilization accuracy, achieving an overall efficiency of 96%; and the multi-winding series structure without voltage-doubling rectification avoids issues such as multi-stage voltage drops and excessive energy storage, resulting in a more uniform insulation gradient.

2. Materials and Methods

2.1. Basic Characteristics of LC Resonant Converters

Figure 1a illustrates the operating principle of an LC series resonant charging circuit. When the operating frequency f_s of the inverter switches is less than 0.5f_r, the resonant current i_Lr operates in discontinuous conduction mode (DCM). Enabling the IGBTs to achieve zero-current switching (ZCS) thereby effectively reduces the switching losses.

In discontinuous conduction mode (DCM), there are six operational phases in one switching cycle. The resonant current waveforms during these six phases are shown in Figure 1b.

In this mode, the average charging current to the equivalent load capacitance remains approximately constant over each resonant cycle, meaning that the system exhibits a constant-current charging characteristic [10].

According to the analysis, the number of high-frequency switching cycles m required to complete charging can be estimated as:

$$m={\displaystyle \frac{C_r+C_{O^{\prime }}}{8C_r}}={\displaystyle \frac{C_r+n^2{C}_O}{8C_r}}$$

(1)

Here, n is the transformer turns ratio, C_o is the output capacitance, and C_r is the resonant capacitance.

$$I_{\max }(m_4)={\displaystyle \frac{(8m-3)C_r+C_{O^{\prime }}}{(C_r+C_{O^{\prime }})Z}}{U}_{in}$$

(2)

Based on the above characteristics, the following sections present the design of the main circuit parameters for the high-voltage power supply, the control strategy for the front-end PFC, and the composite control scheme for the rear-end resonant converter (Section 2.2, Section 2.3 and Section 2.4). A detailed step-by-step derivation of the current-interrupted mode is provided in Appendix A.

According to the input–output characteristics of the LC resonant converter, the gain curve of the converter is derived and plotted. The gain expression of the FHA equivalent circuit for the LC resonant converter can be expressed as follows:

$$H(j\omega )={\displaystyle \frac{V_{p1}(j\omega )}{V_{in1}(j\omega )}}={\displaystyle \frac{R_{eq}}{j\omega L_r+\frac{1}{j\omega C_r}+R_{eq}}}$$

(3)

After simplification and normalization, the DC voltage gain expression can be obtained as:

$$M={\displaystyle \frac{j{\omega }_n}{\frac{{\pi }^2}{8}\cdot Q\cdot \left(1-{\omega }_n^2\right)+j{\omega }_n}}$$

(4)

Figure 2 shows the gain characteristics of the LC series resonant converter.

Based on the above equations and gain curves, it can be observed that the output charging voltage is closely related to the converter voltage gain, while the load resistance affects the gain characteristics through the quality factor (Q). As the load becomes lighter, the quality factor gradually decreases, and the system gain approaches unity, which is consistent with the actual operating condition of the proposed high-voltage power supply.

When the gain (M < 1), part of the input energy is dissipated by the load, resulting in a reduction in the output voltage that can be established at the output terminal. In addition, when the operating point deviates from the resonant point, namely under ZVS or ZCS operating conditions, additional reactive power circulation is introduced to reduce switching losses and achieve soft-switching operation.

Therefore, in the proposed power-supply design, the operating point is selected as much as possible in the left-side region of the gain curve. Based on this consideration, the transformer turns ratio can be appropriately increased to ensure that the required output voltage can still be obtained under low-input-voltage or heavy-load conditions.

2.2. Acceleration Power Supply Design

The primary function of a high-voltage acceleration power supply is to establish an extremely stable, precisely controllable DC high-voltage electric field between the cathode and anode of the electron gun, which accelerates electrons to the desired energy level.

In industrial settings, electron guns must operate continuously 24 h a day, 7 days a week, maintaining high power levels for extended periods. This necessitates high stability and conversion efficiency from the power supply, as well as a certain degree of immunity to interference. The technical specifications of this power supply are shown in

Table 2. Technical specifications of the acceleration power supply.

Design Specifications	Target Parameters
Input Voltage	AC 380 V ± 10%
Rated Output Power	30 kW
Rated Output Voltage	−150 kV
Output Voltage Ripple Factor	≤0.1%
Rated Efficiency	≥90%
High Voltage Range	50–150 kV (Adjustable)
Switching Frequency	10–30 kHz (Adjustable)
Relative Load Regulation	≤1% (from No-Load to Rated Load)
Relative Line Regulation	≤0.1% (for ±10% Input Voltage Variation)

.

2.2.1. Acceleration Power Supply Structure Design

The key part of the system is the acceleration power supply. Its block diagram appears in Figure 3. The main circuit comprises the following stages: three-phase rectification, resonant inversion, high-frequency transformer step-up, high-voltage rectification, and energy-storage capacitors. These work together to provide a stable, high-voltage acceleration supply to the electron gun. The control section uses an FPGA-based control circuit and includes IGBT driver circuits, voltage and current-sampling circuits, fault-detection and protection circuits, and a touchscreen interface. These elements provide drive control, status monitoring, regulation, and safety functions.

2.2.2. Technical Characteristics of the Main Circuit

Figure 4 shows the main circuit topology of the high-voltage acceleration power supply, which generates high-voltage DC using a three-phase mains rectifier, an inverter, a high-frequency high-voltage transformer, and a high-voltage silicon stack rectifier.

First, a three-phase SPWM active rectifier uses fully controlled power devices to modulate the three-phase input current. The DC bus then supplies stable power to the next stage, under low current stress and high power factor conditions. The downstream inverter section uses a full-bridge inverter topology to regulate output power at a fixed switching frequency. It utilizes the transformer’s leakage inductance and an external inductor to enable zero-voltage turn-on of the power switching devices. A high-frequency step-up transformer replaces the traditional power-frequency step-up device. The eight secondary windings are distributed throughout the actual hardware. The rectifier and filter units connect in series to form a high-voltage output terminal. The voltage gradient increases stepwise along the series direction. This series-connected DC boost configuration uses multiple secondary windings to achieve a stable 150 kV-class DC high-voltage output without a voltage-doubling rectifier and provides a reliable high-voltage power supply for the electron curtain accelerator.

The power supply employs a dual-closed-loop control scheme with an inner current loop and an outer voltage loop. This effectively mitigates the impact of grid voltage fluctuations and load variations on the DC bus voltage. Soft-switching reduces the rate of change of voltage and current across power devices. In turn, this minimizes electromagnetic interference and thermal stress on the devices. These features enhance the stability and reliability of the power supply during long-term, high-power operation. The specific control methods are detailed in Section 2.3 and Section 2.4.

2.2.3. Step-Up Transformer Design

In the power supply system for the electron curtain accelerator, the step-up transformer serves as a key energy conversion component, providing electromagnetic energy transfer, voltage step-up, and electrical isolation between the primary and secondary sides. The high-frequency AC generated by the resonant inverter is applied to the primary winding, and the required high-voltage DC output is obtained through magnetic coupling and rectification on the secondary side.

The main design specifications of the transformer are as follows:

(1)

Operating frequency: 40 kHz; input square-wave voltage amplitude: 800 V;

(2)

Output voltage amplitude (after filter capacitor): 150 kV; rated output power: 30 kW;

(3)

Transformer turns ratio: 1:192; leakage inductance: less than 1 μH; distributed capacitance: as low as possible.

• Area-Product (AP) Design Method

The design of high-frequency transformers typically employs the area-product (AP) method. In this design, the LC resonant converter has an input voltage of 800 V, an output voltage of 150 kV, a rated power of 30 kW, an operating frequency of 40 kHz, a magnetic flux density B_m of 0.3 T, a winding current density J of 300 A/cm², a core window utilization factor K_u of 0.1, and a waveform factor K_f of 4 for a square wave [11]. The required AP value is then calculated as:

$$A_{\mathrm{P}}={\displaystyle \frac{2P\cdot {10}^4}{B_{\mathrm{m}}\cdot K_{\mathrm{f}}\cdot K_{\mathrm{u}}\cdot J\cdot f}}=357{\mathrm{cm}}^4$$

(5)

The CD60×60×400-175 ultra-fine-grained iron core was selected. This material offers advantages such as high saturation magnetic flux density, high magnetic permeability, low loss, and low cost. The core has a rectangular structure. Its effective cross-sectional area, A_e, is 2520 mm². Its window area, A_w, is 70,000 mm². Since the product of these two values exceeds the AP value in Equation (5), the core structure and material selection meet the requirements.

2.

Winding Design and Electrical Parameter

To ensure sufficient winding space on the core with a generous margin, the number of primary turns, N₁, can be calculated as:

$$N_1={\displaystyle \frac{V_{AB}}{B_{\mathrm{m}}\cdot K_{\mathrm{f}}\cdot f\cdot A_e}}\approx 7$$

(6)

The secondary winding consists of 1344 turns, divided into 8 groups of 168 turns each. High-voltage insulation is provided for every secondary winding, and insulation material is added to each winding section. The cross-sectional area of the primary winding conductor is:

$$S_{\mathrm{p}}={\displaystyle \frac{I_{\mathrm{p}}}{J}}=12.8{\mathrm{mm}}^2$$

(7)

The primary winding consists of 4 parallel strands of 0.1 mm × 700-strand high-frequency Litz wire, providing an effective cross-sectional area of 21.98 mm². The secondary winding conductor is:

$$S_{\mathrm{s}}={\displaystyle \frac{I_{\mathrm{s}}}{J}}=0.07{\mathrm{mm}}^2$$

(8)

The secondary winding adopts 0.4 mm triple-insulated wire, with an effective conductor area of 0.13 mm². A copper tape shielding layer (0.2 mm × 330 mm) is inserted between primary and secondary windings to suppress common-mode coupling and reduce electromagnetic interference.

3.

Insulation Structure and Engineering Considerations for Multi-Winding Series Output

To ensure reliable operation under 150 kV high-voltage conditions, both insulation coordination and multi-winding series effects are carefully addressed.

For conventional high-frequency transformers with multiple AC secondary windings, parasitic capacitances to ground may form a capacitive voltage divider, leading to uneven transient voltage distribution. To eliminate this effect, a ‘rectification-before-series-connection’ architecture is adopted. Each secondary winding is equipped with an independent high-voltage rectifier and filter stage, and the outputs are then connected in series on the DC side. This structure effectively blocks high-frequency AC propagation between stages and prevents parasitic capacitances from participating in transient voltage division, thereby ensuring stable voltage sharing.

4.

Insulation Coordination and Partial Discharge Mitigation

Dividing the secondary winding into eight identical modules greatly alleviates the voltage stress borne by each winding and improves the overall insulation reliability. The secondary windings are fabricated using 0.4 mm-diameter triple-insulated wire, while the interlayer insulation is implemented with polyimide film and DM-F composite film, and alkali-free glass cloth tape is adopted for structural reinforcement; these integrated measures effectively mitigate local electric field concentration and enhance the overall dielectric strength. For the final 150 kV engineering prototype, oil-immersed insulation with degassed mineral transformer oil is adopted to eliminate internal air voids inside the winding structure. This suppresses the initiation of partial discharge and guarantees long-term insulation stability during continuous high-voltage operation [12,13].

2.3. Front-End PFC Control Strategy Design

To maintain a stable DC bus voltage in the high-voltage power supply under varying grid and load conditions while ensuring a high power factor and low input current harmonics, this paper presents a digitally implemented voltage–current dual-loop PFC control scheme for the front-end rectifier. The proposed method integrates bus voltage regulation, grid phase synchronization, accurate current tracking, and feedforward compensation. This composite control strategy enhances system dynamic response and stability during high-power, high-voltage charging, ensuring a reliable DC input for the subsequent LC resonant inverter. The loop architecture is illustrated in Figure 5.

2.3.1. Voltage Outer Loop and Anti-Windup PI Regulation

The voltage outer loop stabilizes the DC bus voltage during startup, load transients, and high-voltage charging. Conventional PI controllers often suffer from integral saturation in high-inertia systems, leading to voltage overshoot and slow recovery. To address this, an anti-windup PI control algorithm is used, limiting output and correcting integral accumulation to improve system stability and response. The algorithm works as follows:

$$U(n)=K_p\cdot e(n)+I_n(n-1)$$

(9)

$$I_n(n)=I_n(n-1)+K_i\cdot e(n)+K_{sat}\cdot e_{pi}$$

(10)

$$e_{pi}=U_s-U(n)$$

(11)

Among these,

$$\left\{\begin{array}{l}U(n)\ge U_{\max },U_s=U_{\max }\\ U(n)\le U_{\max },U_s=U_{\min }\end{array}\right.$$

(12)

In the equation, U_s is the anti-saturation PI controller output. U(n) is the current PI controller output. K_p and K_i are the proportional and integral gains. K_sat is the anti-saturation coefficient. I_n(n) is the current integral sum. U_max and U_min are the maximum and minimum PI controller output values.

The voltage loop takes as its input the error between the setpoint and the measured DC bus voltage. This error then passes through an anti-saturation PI controller, producing a power amplitude reference signal. This signal, representing the required input power magnitude for the system, serves as a reference for the inner loop, enabling dynamic power regulation and precise stabilization of the DC bus voltage.

2.3.2. Design of Digital Phase-Locked Loop Based on Adaptive Look-Up Table Method

To achieve unity power factor operation, the input current must remain in phase and at the same frequency as the grid voltage; therefore, grid phase synchronization is a critical aspect of PFC control. This paper uses a table-lookup-based digital phase-locked loop (PLL) to achieve phase tracking [14].

To address issues caused by rounding in a decimal table-lookup step size, this paper presents an adaptive step-size correction mechanism, as shown in Figure 6. A PI controller calculates phase error in real-time and dynamically corrects the table-lookup step size. This enables the PLL to lock quickly and track without steady-state error, even during grid frequency drift and voltage distortion. The PLL’s standard sinusoidal phase signal is used to generate a current-reference waveform that remains in phase with the grid voltage. This is central to achieving high-power-factor operation.

However, in the industrial environments where high-power accelerators are located, the mains voltage is almost never an ideal pure sine wave; two types of severe interference are commonly present:

(1)

High total harmonic distortion (THD): The mains voltage contains a large amount of odd-order harmonics, such as 3rd, 5th, and 7th harmonics;

(2)

Zero-crossing noise: Interference such as spikes and jitter occurs near the voltage zero-crossing points.

If the grid voltage exhibits the severe distortions described above, it will feed a large number of false phase error signals into the PI controller, causing the controller—which is responsible for calculating the look-up table step size—to produce a continuously fluctuating output that cannot stabilize.

To verify the performance of the PLL algorithm proposed in this paper under distorted grid conditions, we conducted simulation tests of the PLL under various THD conditions. The test conditions included a clean fundamental wave, grids with 5% and 10% THD, and a three-phase imbalance of ±5%.

Table 3. Performance of the PLL algorithm under various operating conditions.

Test Condition	THD (%)	Convergence Time (ms)	Steady-State Phase Error (°)	Phase Jitter (°)
Pure fundamental	0	15	0.2	0.1
Slight harmonics	5	18	0.5	0.3
Moderate harmonics	10	22	1.2	0.6
Three-phase imbalance	5	20	0.8	0.4

summarizes the PLL’s convergence time, steady-state phase error, and steady-state jitter amplitude under each operating condition.

The results show that the proposed PLL algorithm can maintain a small steady-state phase error (≤0.5°) and low jitter even in a power grid with 5% THD, thereby meeting the practical application requirements. Although the dynamic response increases slightly, it remains within an acceptable range, demonstrating the algorithm’s robustness under non-ideal grid conditions.

2.3.3. Compound Control of Inner Current Loop and Feedforward Compensation

The inner current loop tracks the reference current precisely to ensure a sinusoidal input current waveform with low harmonic content. However, the limited bandwidth of digital control systems hinders the ideal tracking performance of traditional PI control using error feedback. To address this, this paper uses a composite control strategy that combines feedforward compensation with PI feedback.

The voltage outer loop measures the bus voltage and performs a closed-loop calculation with the reference value; its output serves as the amplitude reference for the current loop. This is then combined with the phase-synchronization signal from the phase-locked loop and the rms value of the input voltage to form the current-loop reference. The complete calculation formula is as follows:

$$I_{ref}={\displaystyle \frac{U_{vout}\cdot \sin \left({\theta }_{PLL}\right)}{U_{in,rms}^2}}$$

(13)

In the equation, U_vout represents the output of the voltage outer loop, which characterizes the required power amplitude of the system; sin (θ_PLL) represents the synchronous phase signal output by the phase-locked loop; U_in,rms represents the root-mean-square value of the input voltage, which is used to compensate for grid fluctuations.

Due to the influence of the FPGA clock frequency, sampling and transmission delays, and loop computation delays, the bandwidth of the current loop in digital control systems is typically low. Relying solely on closed-loop PI control makes it difficult to precisely track the inductor current phase with the grid voltage phase. To address this, steady-state feedforward compensation control is introduced. By combining the input grid voltage, bus voltage, and the operating principles of SPWM modulation, the duty cycle during steady-state operation is calculated in advance and used as a feedforward control input to directly influence the duty cycle output.

In this case, the current-loop PI controller does not need to handle the entire control task; it only needs to make minor corrections around the steady-state operating point provided by the feedforward control. This significantly reduces the control range, effectively compensating for the current loop’s limited bandwidth and making the inductor current waveform closer to an ideal sine wave. The final duty cycle is generated by superimposing the feedforward term and the PI control term, thereby controlling the switching device’s operation. This approach achieves control objectives of low bus voltage fluctuations, fast dynamic response, a near-unity power factor, and low input current harmonics across a wide range of operating conditions.

2.4. Design of Control Strategy for Downstream LC Resonant Converter

Traditional continuous PI control continuously outputs PWM pulses during the voltage stabilization phase, forcing a reduction in switching frequency under light load conditions, which results in high output ripple, waveform jitter, and high switching losses. To address the requirements for fast charging and high-precision voltage regulation in 150 kV high-voltage power supplies, this paper proposes a hybrid control scheme for the downstream LC resonant converter that combines variable-frequency fixed-duty-cycle PWM control with hysteresis burst regulation, ensuring excellent dynamic response and output stability across a wide range of operating conditions.

2.4.1. PWM Control and Synchronous Sampling

The LC resonant converter employs a variable-frequency fixed-duty-cycle control strategy, in which the duty cycle of the switch drive signal is fixed at 50%, and the output voltage is continuously adjusted by varying the switching frequency [15]. To prevent shoot-through, a configurable dead time is incorporated into the drive signal. Additionally, to mitigate the impact of switching noise on sampling accuracy, the ADC sampling trigger is synchronized with the midpoint of the PWM period, as shown in Figure S1, ensuring that sampling occurs within a range where current and voltage are relatively stable, thereby effectively enhancing the stability and accuracy of the control loop.

2.4.2. Hysteresis Burst Voltage Control

Once the output voltage reaches the set value and enters the voltage regulation phase, the system switches to hysteresis burst control mode. By continuously comparing the output voltage with the reference voltage, the system generates PWM pulses to replenish power when the voltage falls below the lower hysteresis limit, and shuts off the pulses when the voltage exceeds the upper hysteresis limit. This intermittent operating mode significantly reduces switching losses at light loads while minimizing steady-state output voltage ripple, enabling the system to achieve both high efficiency and stability during long-term voltage regulation [11].

2.5. System Loss Analysis

To evaluate the efficiency of the proposed 30 kW high-voltage power supply system, a system-level loss analysis was conducted under rated operating conditions. The total losses were decomposed into the main power conversion stages, including the front-end rectifier, LC resonant inverter, resonant tank, high-frequency transformer, and high-voltage rectifier. The analysis was based on device datasheet parameters and standard engineering assumptions, considering the main non-ideal effects in high-frequency power conversion systems.

The loss distribution of each subsystem is summarized as follows. The front-end three-phase SPWM rectifier contributed approximately 611 W, including conduction and switching losses under hard-switching operation. The LC resonant inverter contributed approximately 851 W, where switching losses were significantly reduced due to ZCS operation, while remaining conduction and residual switching losses were considered. The resonant tank introduced approximately 100 W loss due to inductor winding loss and capacitor dielectric loss at 40 kHz. The high-frequency transformer contributed approximately 457 W, where both core loss (Steinmetz model) and copper loss (including high-frequency effects such as skin and proximity effects) were considered [16]. The high-voltage rectifier stage contributed approximately 22 W, owing to low conduction loss and reduced reverse recovery under near zero-current switching conditions.

The total system loss was approximately 2.04 kW, corresponding to an overall efficiency of approximately 93.2% under rated 30 kW output conditions.

It should be noted that the efficiency was obtained based on analytical modeling and datasheet-based parameters under standard engineering assumptions. The result provides a system-level performance estimation for design evaluation. The calculated efficiency is consistent with the measured performance trend of the low-voltage experimental prototype, verifying the validity of the proposed loss estimation method.

2.6. Filament Power Supply Design and Control

2.6.1. Power Supply Overview

In the high-voltage power supply system of an electron beam accelerator, the filament power supply heats the electron gun cathode, raising its temperature to enable stable thermionic emission. In practice, soft-start and constant-current ramp-up methods gradually stabilize the filament temperature.

The filament power supply uses an LLC resonant topology, which provides superior soft-switching performance compared to phase-shifted full-bridge topologies and is ideal for high-frequency switching power supplies [17,18]. However, traditional LLC topologies lack dynamic response and stability under load changes and high currents, making it difficult to meet filament power supply requirements [19]. In this paper, a lead-lag compensator replaces the PI compensator, adding two zeros and three poles to the system transfer function to improve dynamic response and noise immunity, optimize output, and ensure stable electron beam emission [20]. The technical specifications of the filament power supply are shown in

Table 4. Technical specifications of filament power supply.

Output Specifications	Target Parameters
Output Voltage	24–26 V
Output Current	0–20 A
Output Full-Load Power	500 W
Resonant Operating Frequency	50 kHz

.

2.6.2. Overall Topology of the Circuit

The power supply hardware consists of three major components: the EMI section, the PFC section, and the LLC section, as shown in Figure 7. First, the input AC power passes through the EMI filter before reaching the PFC circuit input. The PFC circuit then regulates the power to maintain an undistorted grid current and keeps the high-voltage output bus at 380 V, supplying the downstream DC–DC circuit. Next, the DC–DC stage uses a full-bridge resonant LLC converter to ensure electrical isolation between the input and output while regulating the output voltage and current to the target values.

2.6.3. Control Strategy Analysis

To realize closed-loop control with high precision and high stability of the filament power supply output voltage, and to address insufficient loop gain and limited dynamic response in the open-loop LLC resonant converter system, this paper presents a detailed small-signal model, precise open-loop frequency response analysis, and targeted compensator optimization [21]. These steps establish a robust voltage closed-loop control system, as illustrated in Figure 8.

This architecture is centered on output-voltage feedback; it drives the compensator with the error signal between the reference voltage and the actual output, thereby achieving precise closed-loop control of the LLC resonant converter. Here, H(s) represents the designed active lead-lag compensator, and G_p(s) represents the small-signal transfer function of the LLC resonant converter.

• Small-Signal Modeling and Open-Loop Analysis of LLC Converters

To achieve precise closed-loop control of the filament power supply, a small-signal model of the LLC resonant converter is first established. It is assumed that (1) the amplitude of the small-signal disturbance is very small; (2) both capacitors and inductors are ideal components, and additional losses are modeled as resistive. Draw the small-signal equivalent circuit as shown in Figure 9:

Selecting the four state variables $v_{cr}$, $i_p$, $v_{co}$, and $i_m$, we use Kirchhoff’s laws to derive the state equations:

$$\left\{\begin{array}{l}{v}_g=i_p{r}_s+v_{cr}+L_r{\displaystyle \frac{d{i}_p}{dt}}+v_r\\ i_d=\left(1+{\displaystyle \frac{r_c}{R}}\right)C_o{\displaystyle \frac{d{v}_{co}}{dt}}+{\displaystyle \frac{v_{co}}{R}}\\ i_p=C_r{\displaystyle \frac{d{v}_{cr}}{dt}}\\ Nsgn\left(i_T\right)v_o=L_m{\displaystyle \frac{d{i}_m}{dt}}\end{array}\right.$$

(14)

Set the system operating point to $(V_m,D,{\Omega }_s)$, using Fourier decomposition, harmonic balancing, and the small-signal perturbation method. Steady-state equations are derived and substituted with the operating point to establish a 7th-order state-space model:

$$\left\{\begin{array}{l}{\displaystyle \frac{d\widehat{x}}{dt}}=A\widehat{x}+B\widehat{u}\\ \widehat{y}=C\widehat{x}+D\widehat{u}\end{array}\right.$$

(15)

In particular, $\widehat{x}={({\widehat{i}}_{ps},{\widehat{i}}_{pc},{\widehat{V}}_{C_{r}s},{\widehat{V}}_{C_{r}c},{\widehat{i}}_{ms},{\widehat{i}}_{mc},{\widehat{v}}_{C_o})}^T,\widehat{u}={\widehat{\omega }}_s,\widehat{y}={\widehat{v}}_o$.

The closed-loop transfer function is:

$$G_{cl}\left(s\right)={\displaystyle \frac{{\widehat{v}}_o\left(s\right)}{{\widehat{\omega }}_s\left(s\right)}}=C{\left(sI-A\right)}^{-1}B+D$$

(16)

To simplify the controller design, a third-order simplified open-loop transfer function was obtained through frequency-sweep fitting in MATLAB:

$${\mathrm{G}}_{\mathrm{p}}\left(\mathrm{s}\right)={\displaystyle \frac{-0.9445{\mathrm{s}}^2-8857\mathrm{s}+1.667\times {10}^{10}}{{\mathrm{s}}^3+3339{\mathrm{s}}^2+4.076\times {10}^6\mathrm{s}-1.055\times {10}^{10}}}$$

(17)

The open-loop Bode plot and pole-zero values are shown in Figure 10a,b. As shown in the Bode plot, the system’s overall open-loop gain was low, with a margin of −55 dB, and there is no effective crossover frequency. Additionally, the system has poles and zeros in the right-half plane, resulting in pronounced non-minimum-phase behavior. Consequently, both the dynamic performance and stability fell short of the system requirements, necessitating further closed-loop compensation optimization.

2.

Design of Lead-Lag Compensators and Pole-Zero Placement

To address the stability issues in open-loop systems, an active lead-lag compensation network has been designed [22], with its circuit topology shown in Figure S2.

The transfer function of the compensation network is:

$${\displaystyle \frac{V_{OUT}\left(s\right)}{V_{IN}\left(s\right)}}={\displaystyle \frac{\left(1+s{R}_2{C}_1\right)\left[1+s\left(R_1+R_3\right)C_3\right]}{\left[s{R}_1\left(C_1+C_2\right)\right]\left(1+s\frac{R_2{C}_1{C}_2}{C_1+C_2}\right)\left(1+s{R}_3{C}_3\right)}}$$

(18)

Here, V_IN(s) represents the compensation input, which is the difference between the control system’s input and output voltages, while V_OUT(s) represents the compensation output.

This transfer function contains two zeros and three poles. The system performance is optimized through intentional zero-pole placement:

Placing the two zeros at half the switching frequency provides a large lead at the target crossover frequency, thereby mitigating the additional phase lag introduced by the right-half-plane zero and increasing the system’s phase margin, ensuring stable operation near the target crossover frequency.

The system crossover frequency is set to 10 kHz, which is significantly lower than the frequency of the right-half-plane zero. This avoids the frequency band where the non-minimum-phase effects of the right-half-plane zero are significantly amplified, while also ensuring the rapid dynamic response required by the filament power supply.

The three poles are configured as follows: one pole is placed at the origin to ensure the system has no static error, and the other two poles are located at the switching frequency to attenuate high-frequency switching noise.

The system’s closed-loop transfer function after compensation by the compensator obtained from the sweep test is:

$${\mathrm{G}}_{\mathrm{cl}}\left(\mathrm{s}\right)={\displaystyle \frac{260.1{\mathrm{s}}^2+3.514\times {10}^7\mathrm{s}-1.444\times {10}^{11}}{{\mathrm{s}}^3+3270{\mathrm{s}}^2+2.424\times {10}^7\mathrm{s}-1.486\times {10}^{11}}}$$

(19)

The Bode plot of the compensated system is shown in Figure 11. It can be seen that the low-frequency gain of the compensated system is effectively boosted by the two zeros and crosses the 0 dB line at 10 kHz with a slope of −20 dB/decade. At the same time, the gain in the high-frequency range is effectively attenuated by the poles of the compensator, thereby enhancing the system’s high-frequency noise suppression capability.

Furthermore, the compensated system achieves sufficient phase margin and gain margin. The non-minimum-phase effects caused by the zero in the right-half plane are significantly mitigated, and both the system stability and dynamic response performance are effectively improved.

In practical high-voltage, high-frequency LLC resonant converter systems, non-ideal factors such as transformer stray capacitance, diode reverse recovery, and inductor and capacitor nonlinearities can affect system performance, potentially leading to discrepancies between analytical models and experimental results. To address this, this paper conducted a qualitative analysis of the primary non-ideal effects and implements targeted engineering optimization measures, as shown in

Table 5. Influence of non-ideal factors and corresponding mitigation methods.

Non-Ideal Factor	Effect on System Performance	Mitigation Strategy
Transformer stray capacitance	Resonant frequency deviation and waveform distortion	Increasing interlayer insulation using insulating tape and insulated conductors
Diode reverse recovery	Current spikes, switching losses, and EMI	Using Schottky diodes together with dead-time optimization
Component nonlinearity	Resonance shift and steady-state variation	Selecting oversized components operating within the linear region

.

3. Results

3.1. Simulation Analysis

To verify the operating characteristics of the high-voltage power supply for the electron curtain accelerator, a simulation model of the high-voltage charging power supply system was established using PSIM and MATLAB/Simulink. The simulation parameters were configured as follows: three-phase input voltage of 380 V, switching frequency of 15 kHz, resonant inductance of 52.8 μH, resonant capacitance of 0.3 μF, and resonant frequency of 40 kHz. These parameters satisfy the soft-switching condition, i.e., f_s ≤ 0.5f_r. The transformer turns ratio is 1:192, the load capacitance is 0.1 μF, and the simulation duration is 500 ms.

The number of switching cycles (m) at the end of charging can be obtained by substituting the above parameters into Equation (1):

$$m={\displaystyle \frac{C_r+C_{O^{\prime }}}{8C_r}}={\displaystyle \frac{C_r+n^2{C}_O}{8C_r}}=1536$$

(20)

With m = 1536, substituting into Equation (2) gives the maximum resonant current:

$$I_{\max }(m_4)={\displaystyle \frac{(8m-3)C_r+C_{O^{\prime }}}{(C_r+C_{O^{\prime }})Z}}{U}_{in}=120.3A$$

(21)

The voltage envelope waveform across the resonant capacitor is shown in Figure 12a and is consistent with the theoretical calculations. The resonant current envelope waveform is shown in Figure 12b, with a peak value of approximately 118.75 A, which is close to the theoretical value.

Upon magnifying and examining the resonant current waveform, the charging process revealed two sequential phases: a linear phase followed by a nonlinear phase. Initially, as shown in Figure 13a, the system is in the linear charging stage, during which the peak resonant current increases linearly while the average value remains constant. In this stage, the current is discontinuous, and the inverter bridge operates in soft-switching mode. As the peak current is reached, the charging process transitions smoothly into the nonlinear stage, as shown in Figure 13b, where the resonant current gradually decays and the current through the freewheeling diodes drops to zero.

The load voltage waveform is shown in Figure 14a. As shown in the figure, the charging voltage increases linearly, while the charging current remains essentially constant. At a switching frequency of 15 kHz, the charging time is approximately 102.4 ms, and the output voltage stabilizes at around 155.7 kV. As shown in Figure 14b, under rated load conditions, the output voltage ripple is approximately 24 V, with a ripple rate of about 0.01%, meeting the design specifications.

The PFC control system designed in this paper comprises three components: dual-loop voltage and current control, an adaptive lookup table-based digital phase-locked loop, and grid voltage feedforward compensation. Each component has been optimized to address the shortcomings of conventional control schemes. To verify the dynamic performance of the control system designed in this paper, a simulation platform was established to compare three control schemes: open-loop control, conventional single-voltage-loop PI control, and the complete PFC control system described herein. The simulation was set up to simulate a light-load startup with sudden load changes; the load variation conditions are shown in Figure 15a. During the system startup phase, the voltage overshoot in the open-loop state was approximately 0.9 kV; under conventional PI control, the overshoot was suppressed to 0.6 kV, while under the control scheme proposed in this paper, the overshoot was only 0.3 kV, and the voltage quickly stabilized near the rated value. At 0.3 s, a sudden load increase disturbance was applied, switching the load from light load to rated load. At this point, the voltage drop under open-loop control reaches 1.3 kV, and due to the lack of closed-loop regulation capability, the voltage cannot recover to its original steady-state value; under conventional PI control, the voltage drop is 1.1 kV, and it returns to the steady-state approximately 80 ms later. The voltage drop under the control method described in this paper was the smallest, at only 1.0 kV, and the recovery speed was the fastest, returning to the steady-state value in approximately 50 ms, with a relative load regulation rate of about 0.65%. At t = 0.4 s, the load was further increased to an overloaded state; the voltage under open-loop control dropped significantly further, and the steady-state voltage remained persistently low. Conventional PI control exhibited a voltage drop of 0.7 kV with a slower recovery rate; the control method described in this paper resulted in a voltage drop of only 0.6 kV and reached a new steady state in approximately 40 ms, maintaining good regulation capability even under overload conditions and avoiding severe voltage fluctuations. This demonstrates that the control system designed in this paper possesses excellent voltage stability and disturbance rejection capability under load disturbances, meeting the system’s dynamic design requirements.

Assume that the grid voltage fluctuates within ±10%. Observe whether the SPWM rectified output voltage stays near 800 V. Figure 15b shows that when the grid voltage drops by 10%, the output DC voltage briefly overshoots, then quickly stabilizes at about 800 V. The closed-loop feedback remains effective, with relative line regulation of about 0.01%, meeting the requirements.

Building on the simulation of the main circuit’s electrical characteristics, this paper further conducted three-dimensional electrostatic field simulations of the transformer and simulations of the high-voltage system. It quantitatively verified the core performance of the system at a rated voltage of 150 kV, providing comprehensive theoretical support for the engineering feasibility of the design scheme.

First, an electrostatic field analysis of the transformer was performed using COMSOL Multiphysics 6.2 software to verify its insulation performance under 150 kV operating conditions.

Figure 16a,b respectively shows the overall electric field cloud map and the electric potential contour map of the transformer under 150 kV operating conditions.

Simulation results indicate that the maximum electric field strength is approximately 9.87 kV/mm, primarily concentrated at the edges of the windings and in areas with high local curvature. Since the system employs an oil-immersed insulation structure with a breakdown field strength exceeding 15 kV/mm, the current maximum field strength remains below the dielectric strength limit of the insulation medium. The results demonstrate that the designed structure is feasible for high-voltage insulation.

The parasitic parameters between the transformer windings were extracted using the Maxwell capacitance matrix, as shown in

Table 6. Inter-turn parasitic parameters.

Parameter	Value (pF)
C11	5.15
C12	96.9
C21	139.0
C22	80.1

.

In this context, C11 and C22 represent the parasitic capacitance of each winding to ground, while C12 and C21 represent the mutual parasitic capacitance between windings, reflecting the electric field coupling between the series-connected secondary windings.

Lower mutual capacitance helps reduce dynamic voltage coupling between high-voltage windings, thereby improving the voltage balancing performance of series windings and reducing the risk of local voltage overshoot. Meanwhile, an accurate assessment of parasitic capacitance to ground provides a direct basis for high-voltage insulation design and winding arrangement optimization, effectively controlling parasitic current paths and reducing the risk of leakage current and partial discharge.

In addition, the magnetic coupling characteristics of the transformer were analyzed using the COMSOL magnetic field module. The simulation results indicate that the proposed multi-winding structure exhibits good magnetic coupling behavior with limited leakage flux distribution.

Under high-voltage pulse operating conditions, no significant voltage oscillation or local overvoltage phenomenon was observed in the simulation results, indicating that the influence of transformer leakage inductance is effectively suppressed within the designed operating range.

At the same time, typical operating conditions were simulated using PSIM software to extract the output voltages of the eight secondary rectifier units and calculate the voltage unevenness coefficient.

The voltages of the eight windings are shown in Figure 17.

The results show that the voltages across the windings stabilized between 18.3 and 19.1 kV, the unevenness coefficient decreased to 1.02, and the deviation was kept within 3%, meeting the design requirements. This indicates that the proposed structure possesses good high-voltage equalization capabilities and can effectively reduce the risk of local winding overvoltage.

3.2. High-Voltage Power Supply Testing

A low-voltage proof-of-concept experimental platform was established to test the operational performance of the power supply prototype, as shown in Figure 18a,b. This platform uses high-frequency transformers already available in the laboratory for testing. The experiment verified resonance charging behavior, soft-switching operation, and the closed-loop control algorithm. The dedicated 150 kV high-voltage transformer designed in this paper was not included in the experiment due to manufacturing and assembly lead times.

The key component parameters of the experimental platform are summarized in

Table 7. Key components of the low-voltage experimental platform.

Device Category	Device Name	Parameters/Model
Input Filter	3-phase 4-wire EMI filter	HRL-30A, 440 VAC
Power Stage	Dual IGBT	Infineon FF600R12ME4, 1200 V, 600 A
Protection	Thermal protector	KSD9700, 70 °C trip temperature
Resonant Tank	Resonant inductor (Lr)	52.8 μH, 1200 V
	Resonant capacitor (Cr)	0.3 μF, 1200 V
Transformer	Step-up transformer	1:30 ratio, Lleak = 4 μH, Lm = 115 mH
Control	FPGA	Intel Cyclone IV-E EP4CE10F17C8
Load	HV capacitor	3 × 2 μF/30 kV
	Current-limiting resistor	60 kΩ
Measurement	Current transformer	1:60
	HV probe	1:5000
	Oscilloscope	Tektronix MDO3024/Yokogawa

. The system consists of an AC input EMI filtering stage, a high-power switching stage based on IGBTs, an LC resonant energy conversion stage, a step-up transformer, a high-voltage rectifier load, and a digital control unit implemented by an FPGA.

To ensure safe and reliable operation, thermal protection is applied to major heat-generating components. The load and measurement systems are configured to emulate practical high-voltage operating conditions and ensure accurate waveform acquisition.

With the DC input voltage set to 800 V and the switching frequency to 15 kHz, a no-load charging test was conducted. The results are shown in Figure 19. The platform achieved a maximum output voltage of 24 kV, with a charging time of approximately 50 ms. The slope of the load voltage rise was stable, indicating that the charging current was approximately constant; thus, this can be considered constant-current charging.

Load tests were conducted using a 60 kΩ load to observe the resonant current waveform. Figure 20a below shows the waveform during the early stage of resonant charging, while Figure 20b shows the waveform during the late stage of resonant charging. During the early charging stage, the current exhibits discontinuities, and the inverter bridge operates in soft-switching mode. Due to the transformer’s distributed capacitance, the current waveform shows slight oscillations compared to the simulation, but the resonant period generally matches the switching period. As charging nears completion and the output voltage gradually increases, the amplitude of the resonant current decreases. The inverter bridge continues to operate in soft-switching mode without hard-switching transients; minor high-frequency oscillations caused by parasitic parameters on the load side do not affect system stability. Test results show a peak resonant current of approximately 40 A and a load current of approximately 0.4 A, corresponding to an output power of approximately 9.6 kW. The calculated power supply efficiency is 96%, meeting the design specifications.

Closed-loop voltage regulation tests were conducted on the prototype. Charging voltage waveforms at 5 kV, 10 kV, 15 kV, and 20 kV are shown in Figure 21a–d. The load voltage rises smoothly. The charging current remains stable. The charging time is nearly proportional to the set voltage. The closed-loop system continuously monitors output voltage and adjusts the switching frequency to maintain the set value. This validates the effectiveness of the feedback loop.

Table 8. Voltage rise slopes under different target voltages.

Set Target Voltage ${\mathit{U}}_{\mathit{s}\mathit{e}\mathit{t}}$ (kV)	Voltage Rise Slope ΔU/Δt (ms)	Relative Slope Deviation	Charging Phase Status Evaluation
5	623.9	−0.2%	Constant
10	616.2	−1.4%	Constant
15	621.1	−0.6%	Constant
20	629.7	+0.7%	Constant

shows the slope of the voltage rise at different charging voltages.

As shown in the table, under operating conditions with different target voltages, the system’s voltage rise rate remains stable at approximately 625 V/ms, with relative fluctuations strictly limited to within ±1.5%. This indicates that the digital closed-loop control system is capable of precisely maintaining a constant average charging current during the initial phase across different charging targets. Toward the end of the charging process, as the voltage approaches the setpoint, the current naturally enters a nonlinear decay phase due to the physical characteristics of the topology; however, the constant-current performance during the core charging interval is fully supported by cross-condition validation.

Figure 22 shows the waveform diagram of the output ripple and the hysteresis control flag. Specifically, the output ripple is approximately 25 V, while the burst control flag fluctuates around the set trigger voltage of 24 kV. As a result, voltage accuracy is maintained at around 0.1%. The hysteresis control circuit thereby stabilizes fluctuations near the set voltage, helping maintain a steady output and enabling the system to meet the accuracy requirements of high-voltage charging power supplies.

3.3. Filament Power Supply Testing

Testing began with powering the test prototype using a 220 V AC source and connecting its output to an electronic load. Initial observations included monitoring the primary-side resonant current waveform with a 10 A/1 V current transformer. The electronic load was then set to transient test mode to verify step responses under changing loads. After confirming basic operation, the next test phase focused on validating the PFC section.

After verifying the initial setup, testing transitioned to the PFC section. Figure 23a displays the input voltage and the sinusoidal voltage waveform generated by the phase-locked loop. Figure 23b displays the sinusoidal voltage and the output current waveform. The output current is in phase with the voltage, indicating accurate tracking and successful power factor correction.

Figure 24a shows the verification waveform of the primary-side resonant current. In this figure, the sequence begins with the switching transistors employing a complementary output strategy, enabling zero-current switching (ZCS) of the resonant current during the dead time. Following this, when the output voltage is set to 24 V, the peak secondary-side current reaches approximately 30 A, and the average output current is close to 20 A, meeting the power supply’s design specifications.

As shown in Figure 24b, a load step test was conducted by switching the output load between no-load and full-load. The experimental results show that the current rapidly fluctuates between 0 A and 20 A. However, the output voltage remains stable at about 24 V, with virtually no fluctuation. This demonstrates that the proposed system exhibits excellent dynamic response performance.

4. Discussion

All experiments in this study were conducted using low-voltage prototype units. Due to limitations in the development of high-voltage transformers, full-voltage-range experiments at 150 kV have not yet been conducted. Consequently, the performance analysis under 150 kV operating conditions is primarily based on theoretical and simulation results, which were validated in conjunction with experiments on low-voltage prototypes; this constitutes the main limitation of this study. Full-voltage-range experimental validation will be conducted once the development of the high-voltage transformer is complete.

4.1. High-Voltage Insulation Characteristics and Partial Discharge Risk Analysis

The multi-winding series high-voltage transformer structure designed in this paper is prone to localized electric field distortion under 150 kV high-voltage operating conditions. Based on the electric field simulation results, high-field-strength regions in the system are primarily concentrated at the edges of the transformer windings and structural sharp corners. Such areas are highly prone to inducing localized electric field concentration, which in turn leads to partial discharge. Long-term operation can cause insulation medium aging and the degradation of insulation performance, posing a serious threat to the operational reliability of the high-voltage power supply system. This represents a critical risk point that requires strict control in high-voltage series winding structures.

To effectively suppress partial discharge and optimize high-voltage insulation performance, this paper implements multiple electric field optimization and insulation reinforcement measures tailored to the structural characteristics of the high-voltage system. By rounding structural sharp corners and increasing the radius of curvature of high-voltage components, local electric field distortion is effectively mitigated; a layered insulation structure design was adopted to balance the voltage distribution between windings and reduce the electric field strength between sections; simultaneously, by combining transformer oil potting and electric field equalization optimization processes, the causes of partial discharge were further mitigated, comprehensively enhancing the system’s high-voltage insulation margin. Simulation verification results indicate that the maximum electric field strength of the system does not exceed the breakdown threshold of the insulating medium, demonstrating that the current structural design possesses good feasibility for high-voltage insulation.

Due to limitations imposed by the experimental site and high-voltage testing conditions, this paper verifies the topological principles, drive synchronization, and pulse formation mechanisms using a low-voltage prototype platform. Based on simulation analyses of electric field distribution, parasitic parameters, leakage inductance characteristics, and winding voltage balancing characteristics, the paper thoroughly demonstrates the operational feasibility of the system under 150 kV high-voltage conditions. Subsequent testing, including full-voltage-range tests, partial discharge detection, and long-term insulation reliability aging tests, can further verify the long-term stable operation capability of the high-voltage system.

4.2. Analysis of System EMI Characteristics and Suppression Strategies

Under high-frequency, high-voltage inverter operating conditions, the high-speed switching of power devices triggers severe dv/dt and di/dt transients. Combined with the amplified effects of parasitic capacitance and stray inductance in high-voltage environments, this can easily lead to high-frequency oscillations as well as common-mode, conducted, and radiated electromagnetic interference. Interference signals can easily couple into control and sampling loops, causing signal distortion, reduced control accuracy, and even triggering false protection trips, thereby threatening the stable operation of the system. To address this, this paper proposes mitigation strategies in three areas: suppression of interference sources, blocking of coupling paths, and enhancement of equipment immunity.

At the source level, an LC series resonant soft-switching topology is adopted to reduce voltage and current spikes during switching, thereby fundamentally reducing the intensity of interference generation. On the circuit side, an EMI filter network is installed at the AC input to block bidirectional conducted interference between the equipment and the power grid. Regarding layout and grounding, the power unit and control unit are physically separated to reduce the loop area of power traces. Combined with zoned grounding and shielding structures to cut off interference propagation paths, this comprehensively enhances the system’s electromagnetic immunity, meeting the electromagnetic compatibility requirements for high-voltage operating conditions.

4.3. Thermal Design and Operational Reliability Analysis of High-Voltage Power Supply Enclosures

The 3D model of the high-voltage power supply enclosure designed in this paper is shown in Figure S3. To ensure stable system operation under high-power conditions, thermal loss analysis, power device temperature evaluation, and cooling performance assessment were conducted on the entire unit.

The system has a rated output power of 30 kW, with the primary thermal losses originating from the IGBT inverter modules, the LC resonant circuit, and the high-voltage rectifier unit, resulting in a total thermal loss of approximately 2.2 kW. The enclosure employs a cooling structure that combines forced air cooling with aluminum heat sinks and directional air ducts. With concentrated heat sources and a clear heat dissipation path, the optimized design ensures that the temperature of the power devices remains below 90 °C during full-load operation, while the heat sink temperature does not exceed 85 °C. This cooling performance meets the long-term operational requirements of a 30 kW high-voltage power supply [23].

Additionally, this paper incorporates a hardware over-temperature protection device into the low-voltage test platform. When the detected temperature exceeds 50 °C, the circuit is automatically disconnected, providing safety assurance for system debugging and operation. The entire system employs a derated component design to ensure controllable temperature rise, adequate heat dissipation, and reliable insulation.

Due to limitations imposed by 150 kV high-voltage insulation conditions, full-system high-voltage load testing was not conducted in this study. However, through thermal design analysis, thermal structure optimization, and reliability verification, the system is guaranteed to meet the thermal safety and stability requirements for engineering applications.

4.4. Future Improvements and Research Directions

Prototype testing and engineering requirements indicate further optimization in four technical areas: output performance, topology, control strategies, and engineering integration.

• The prototype does not achieve full-scale output. To improve output performance, design a high-frequency, high-voltage transformer with optimized insulation, a winding configuration that minimizes leakage inductance, and distributed capacitance that is minimized. This will decrease voltage ripple and enhance the stability and precision of the output.
• For topological and structural optimization, the current multi-stage series arrangement is bulky. Compact rectification and packing technologies can reduce system size and increase power density, provided that insulation safety is maintained and stray parameter effects are minimized through an optimized physical layout.
• Regarding control strategy refinement, further improve voltage regulation under light-load to reduce switching frequency and electromagnetic noise. Integrate arc detection and condition monitoring for enhanced system protection and reliability [24].
• Conduct research on innovative structures and control methods for filament power supplies, overcome the limitations of traditional LLC topologies, explore new topologies and advanced control algorithms, and enhance the dynamic performance and system innovation of filament power supplies.
• For engineering integration, fully integrate the main and auxiliary power supplies with the control circuits. Add communication interfaces and remote monitoring to improve automation and adaptability, allowing electron beam accelerators to meet industrial demands.

5. Conclusions

This paper presents a 150 kV/30 kW digitally controlled DC high-voltage power supply for electron curtain accelerators, which adopts an LC series resonant topology and an eight-winding step-up transformer structure with a digital hybrid control strategy to enhance system performance. The feasibility and superiority of the proposed scheme were verified through simulations and low-voltage platform experiments.

Simulation results show that the system can charge to 155 kV within 102 ms, with an output voltage ripple of less than 0.1%, a rated operating efficiency of up to 93.2%, and achieves zero-current soft switching (ZCS) for IGBTs. Verification on the low-voltage experimental platform shows that the system achieves an efficiency of 96% at 24 kV output, with a peak resonant current of 40 A and a ripple of 0.1%. The constant-current charging characteristics are stable, and the closed-loop control is reliable. The supporting filament power supply can stably output 24 V/20 A, and its dynamic response and power factor meet the power supply requirements of electron curtain accelerators.

The experiments described in this paper have so far been limited to low-voltage prototype models; full-voltage-range tests at 150 kV have not yet been conducted. The analysis of relevant high-voltage operating conditions is primarily based on theoretical and simulation results. Full-scale experiments will be conducted in the future to further refine and validate the findings.

This design is primarily tailored to meet the requirements of electron beam accelerators. Based on a standardized core architecture, it can also be adapted for use in other high-voltage direct current systems following parameter optimization.