Modular Multilevel Converter Control Strategy for AC Fault Current Maximization and Grid Code Compliance

Abstract

This paper proposes a dynamic current limit for modular multilevel converters (MMCs) that maximizes the injection of current during grid faults in order to mitigate the voltage dip, reduce voltage imbalances in case of an asymmetrical fault, and ensure the proper operation of protective relays. The reduced short-circuit capacity of MMCs, and power converters in general, is one of their main limitations. In the event of a fault, the converter’s current is significantly lower than that of the synchronous generators, which may impact both the performance of power system protective relays and the mitigation of voltage drops during faults. Usually, to protect the MMCs themselves, their output current is limited by their control. However, the current flowing through the power semiconductors is the arm current, not the output current, and this consists of an AC and a DC component. A new current saturation strategy aiming at maximizing fault current injection, in compliance with the most recent grid codes, is proposed. This strategy limits the arm currents by dynamically adjusting the output current limit while injecting reactive currents (both positive- and negative-sequence) and active current according to the grid codes, the fault type, and voltage sag level. A theoretical analysis is carried out to determine the maximum current injection that will not exceed the arm limits, and this is then validated through detailed PSCAD simulations. With the proposed strategy, the supplied current can be increased by approximately 40%.

1. Introduction

Power systems are experiencing an increase in the number of high-voltage direct current (HVDC) links and the renewable power plants they contain, which are interfaced with the AC grid through power electronic converters (PECs), which are based on voltage source converters (VSCs). However, PECs present some challenges for the protective relays of AC power systems because their response differs significantly from that of synchronous generators (SGs). While SGs can provide fault currents of up to 6 times their rated current, PECs have a very limited overcurrent capability of about 1.2 times their rated current. Moreover, in cases of asymmetrical faults, SGs naturally behave as a voltage source, injecting both positive- and negative-sequence currents into the system. Conversely, PECs behave during faults like a controlled current source; hence, the injection of negative-sequence currents depends on the PEC’s control [1].

A declining short-circuit level (SCL) may negatively impact power systems, as identified by National Grid ESO, the British system operator [2]. As the SCL declines, the voltage waveform will become more distorted during faults and the retained voltage will be lower [3]. In the case of grid-following converters, which rely on a Phase-Locked Loop (PLL) to determine the voltage angle, low SCLs can cause the PLL to malfunction, potentially leading to the disconnection of a converter from the network. Thus, the source of the risk is twofold: the declining SCLs and the growing number of PLL-based converters. High SCLs, therefore, are required to maintain a stable voltage during a fault and limit the extent of voltage sags.

On the other hand, with low SCLs—and, consequently, low fault currents—protective relays could take longer to operate or not operate as designed, which could result in longer faults in the system, posing a safety risk to people, damaging equipment, and leading to instability [2]. Moreover, although an increasing number of distributed generation facilities are being connected to distribution networks, the contribution of fault current from the distribution networks towards transmission grid faults is expected to increase only slightly [4].

Several countermeasures have been proposed to mitigate the impact of fault level shortfall, such as increasing the k-factor, increasing the converter’s power rating, and installing synchronous condensers [5]. Increasing the k-factor (i.e., the gain that connects the reactive current injection to the voltage deviation during a fault) allows for an increase in fault currents. However, its effectiveness is limited due to the current constraints of the power converters. Thus, for deep voltage sags, the effect of a high k-factor may be negligible [6]. Increasing the converter’s rated power results in higher costs that are roughly proportional to the power increment [7]. Finally, synchronous condensers, which provide a boost to system inertia and an increase in the system fault level, could facilitate the operation of the protection system in future scenarios [8].

In response to an expected drop in fault levels in Scotland as a result of the closure of large SGs, National Grid ESO launched the Stability Pathfinder (SPf) Phase 2 project to seek new sources of fault current, inertia provision and dynamic voltage regulation that could be added to the system services [9]. During the Expression of Interest (EOI) phase, more than 50% of the proposals from participants included synchronous condensers [10]. Ultimately, several synchronous condensers were selected for use in the Stability Pathfinder Project [11,12]. Similarly, the Spanish TSO Red Eléctrica de España (REE) will install three synchronous condensers in the Canary Islands and another one in the Balearic Islands [13].

Many protective relays, such as directional relays, fault-type-identification algorithms, and distance relays, use negative-sequence currents for fault detection [14]. Consequently, some transmission system operators (TSOs) require PECs to inject both positive- and negative-sequence reactive currents based on the magnitudes of the positive and negative voltages in the system, respectively, to emulate the behavior of SGs [15,16]. However, the limited overload capability of PECs can hinder fault detection, as the values of the fault currents are similar to the PECs’ rated current. For this reason, in addition to injecting reactive positive- and negative-sequence currents, TSOs also require the maximization of the injected current to within the limits of the power converter [17].

In recent years, differential protection has become the most secure and reliable method used by TSOs [18], with distance protection widely used as the back-up protection on new lines and the primary protection on legacy transmission lines. It is, in fact, in distance protection where the impact of PECs can pose a risk to the behavior of the protection algorithms, leading to under- or overreach events [19]. Moreover, voltage drops during short-circuits in networks with a high penetration of PECs are significantly larger than those in systems dominated by synchronous generation. This can introduce voltage measurement errors when using a self-polarized mho algorithm for distance calculations. Additionally, the impact of the pre-fault load flow and fault resistance can further distort impedance calculations, potentially leading to false trips for out-of-zone faults and no tripping for in-zone faults [20]. This effect becomes even more pronounced as the SCLs’ difference at both ends of the line increases, which is common in lines ending at HVDC links connected to offshore wind power plants.

Modular Multilevel Converters (MMCs), which are usually connected to transmission grids, have become the preferred converter topology for high-power and high-voltage applications. Moreover, a growing number of this kind of converter is expected in transmission grids. In the North Sea, several offshore wind power plants are already connected to the AC grid through MMC-HVDC links [21]. Germany plans to build 35 HVDC lines to connect 70 GW of offshore wind power plants to the onshore grid by 2045, according to the Network Development Plan 2023–2037/2045 published by its Federal Network Agency (Bundesnetzagentur) [22]. MMC-HVDC links are also utilized in places with technical or environmental constraints, such as the INELFE interconnection between Spain and France [23]. Therefore, their use is clearly increasing in power systems.

To overcome the limited capability of power converters to inject fault currents, ref. [24] proposes controlling the phase of the injected currents to a specific value that avoids the incorrect operation of differential relays. An algorithm for the calculation of the optimal current reference is proposed in [25]; however, it is based on an optimization algorithm that uses 72 system variables and 72 linear and non-linear equations, which may be challenging to apply in real time. For power systems with MMC-HVDC links, ref. [26] analyses a new distance relay scheme for zone 1 that facilitates an accurate calculation of the distance to the fault point.

To protect the MMCs, their output current is typically limited by their control. However, the current that flows through the power semiconductors is the arm current, not the output current, which consists of an AC and a DC component. In the event of a fault, the active power that is exchanged with the AC grid is significantly reduced. This fact, in turn, decreases the DC current that flows through the arms and allows for an increase in the AC current. This paper proposes a new current saturation strategy that is aimed at maximizing fault current injection in compliance with the most recent grid codes. This strategy helps to mitigate the voltage dip, reduce voltage imbalances in cases of asymmetrical faults, and ensure the proper operation of protective relays. This strategy saturates the arm currents by dynamically adjusting the output current limit while injecting reactive currents (both positive- and negative-sequence) and active current according to the grid codes, the fault type, and voltage sag level. A theoretical analysis is carried out to determine the maximum current injection that will not exceed the arm limits, and this is then validated through detailed PSCAD simulations.

The paper is structured as follows. Section 2 describes the main requirements imposed by some European grid codes about fast fault current injection and fault-ride-through capability of HVDC systems and power park modules. The structure of the MMC, its parameters, and its control are detailed in Section 3. Section 4 describes the proposed saturation algorithm that allows for an increase in fault current injection. The new saturation strategy is validated through detailed PSCAD simulations in Section 5. Finally, Section 6 encapsulates the concluding remarks.

2. Grid Codes

According to ENTSO-E [27], an HVDC converter must meet several requirements to provide voltage support and fault ride-through:

• Capability of staying connected to the network within given ranges of the network voltage.
• Capability to provide fast fault current injection at the connection point in case of a symmetrical fault (in coordination with the relevant TSO).
• Asymmetrical current injection in case of an asymmetrical fault (in coordination with the relevant TSO).
• Fault-ride-through capability.

These requirements may be further detailed in national grid codes. For example, in Spain [15], fast fault current requirements for power park modules are defined as follows:

• Power park modules must be capable of managing the rapid injection of fault current through a continuous control system.
• They shall have the capability to inject apparent current per phase that is at least equal to their nominal current.
• For the positive-sequence current, power park modules must inject or absorb, depending on the positive-sequence voltage error $\Delta U_1$, a reactive current $\Delta I_{1r}$ (pu) through a continuous proportional control (see Figure 1). The default value for the limit of this current is $\pm 0.9$ pu.
• In addition to the total reactive current component $I_{1r}$, power park modules must inject an active current component.
• For the negative sequence current, power park modules must inject or absorb, depending on the negative sequence voltage error $\Delta U_2$, a negative sequence current $\Delta I_{2r}$ through a continuous proportional control (see Figure 1).

The IEEE Std. 2800-2022 [28] also establishes the requirements for the injection of fault currents by inverter-based resources (IBRs) during the fault-ride-through mode:

• For balanced faults, IBR units shall inject reactive current dependent on the terminal voltage of the IBR unit. The difference between the reactive current during a fault and the pre-fault reactive current is the incremental positive-sequence reactive current $(\Delta I_{1r})$. During a fault condition, priority shall be given to reactive current injection with any residual capacity being supplied as active current unless the IBR unit is specified to operate in active current priority mode by the TSO.
• For unbalanced faults, in addition to increasing positive-sequence reactive current, the IBR unit shall inject negative-sequence current $(\Delta I_{2r})$, dependent on IBR unit terminal negative-sequence voltage. If the IBR unit’s total current limit is reached, either $\Delta I_{1r}$ or $\Delta I_{2r}$, or both may be reduced with a preference of equal reduction in both currents.
• This standard intentionally does not specify magnitude of incremental positive- and negative-sequence reactive current injection during a fault condition. The TSO should consider specifying the required magnitudes.

These network codes aim at minimizing the voltage drop during faults and enhancing the fault-ride-through capability of the converters connected to the grid. As established, the grid codes prioritize the injection of reactive current over active current to mitigate the voltage drop in the power system. In the case of an unbalanced fault, the grid codes also require the injection of negative-sequence current to emulate the behavior of synchronous generators and improve the performance of the protective relays [15,16,28]. Maximizing the AC-side current during faults improves these capabilities. The key question is how to determine the value of each current component during the fault that will not exceed the converter’s capacity while simultaneously optimizing the performance of the protection system.

3. System and Control Description

Figure 2 shows the structure of a modular multilevel converter. This consists of three phases and each phase has an upper and a lower arm. Each arm is formed by N cascaded submodules. The parameters of the MMC are presented in

Table 1. Parameters of the MMC.

Description	Parameter	Value
Rated apparent power	$S_{MMC}$	435 MVA
Rated active power	$P_{MMC}$	400 MW
Arm inductance	$L_m$	76.16 mH
Cells per arm	N	315 (HB-SMs)
Submodule capacitor	$C_{SM}$	6000 $\mathsf{\mu }$F
Line-to-line grid voltage	$V_g$	260 kV
Angular frequency	$\omega$	$2\pi 50$ rad/s
Pole-to-ground dc voltage	$V_{dc}$	$\pm 250$ kV

.

The positive and negative sequences of the currents that are injected by the MMC into the grid are independently controlled in two synchronous reference frames (SRFs), one for each sequence, as shown in Figure 3. A Second Order Generalized Integrator (SOGI) is used to extract the positive and negative sequences of the grid voltage ($v_{1abc}$ and $v_{2abc}$, respectively). Next, two Phase Locked Loops (PLLs) determine the voltage angles of the positive and negative sequences (${\theta }_1$ and ${\theta }_2$, respectively), aligning the d-axis of each frame with the grid voltage [29]. This ensures that the voltages $V_{1q}$ and $V_{2q}$ are zero. Using the SOGI and the Park transform with the voltage angles of each sequence, the d- and q-axis components of the positive- and negative-sequence voltages ($V_{1dq}$ and $V_{2dq}$, respectively) and currents ($I_{1dq}$ and $I_{2dq}$, respectively) are computed in their respective reference frames [30]. Finally, two independent control loops with two PI regulators each along with the feedforward terms determine the voltage to be generated by the MMC. The energy control of the MMC consists of three parts [31]: (i) a loop for the inner positive-sequence circulating current that is used to transfer energy from the top to the bottom arms, (ii) a loop for the inner negative-sequence circulating current that transfers energy among the three legs, (iii) a loop for the inner DC circulating current that controls the total energy of each leg. Further details can be found in Appendix A.

To protect the MMC from overcurrents that could damage their power semiconductor devices, their output currents $I_x$ (where x stands for phase x = a, b, c) are limited to the maximum allowed current ($I_{lim}$). The current through each phase is:

$$I_a=\sqrt{I_1^2+I_2^2+2I_1{I}_{2}cos(\theta )}$$

(1)

$$I_b=\sqrt{I_1^2+I_2^2+2I_1{I}_{2}cos\left(\theta -{\displaystyle \frac{2\pi }{3}}\right)}$$

(2)

$$I_c=\sqrt{I_1^2+I_2^2+2I_1{I}_{2}cos\left(\theta +{\displaystyle \frac{2\pi }{3}}\right)}$$

(3)

where $I_1$ ($I_1=\sqrt{I_{1d}^2+I_{1q}^2}$) and $I_2$ ($I_2=\sqrt{I_{2d}^2+I_{2q}^2}$) are the magnitudes of the positive- and negative-sequence currents, respectively, and $\theta ={\theta }_2+{\theta }_{2i}-{\theta }_1-{\theta }_{1i}$. $I_{1d}$ and $I_{1q}$ are the positive-sequence active and reactive currents, respectively. $I_{2d}$ and $I_{2q}$ are the negative-sequence active and reactive currents, respectively. ${\theta }_1$ and ${\theta }_2$ are the space vector angles of the positive and negative SRFs, respectively. ${\theta }_{1i}$ and ${\theta }_{2i}$ are the angles of the positive- and negative-sequence currents, respectively, in their own reference frames (see Figure 4).

In case of a grid unbalance, the current through each phase is different. The phase with the highest current is:

$$I_{max}=max(I_a,I_b,I_c)$$

(4)

Expression (4) can also be written as:

$$\begin{array}{c}\hfill I_{max}=\sqrt{I_1^2+I_2^2+2I_1{I}_{2}cos{\left(\theta \right)}_{max}}\end{array}$$

(5)

where $cos{(\theta )}_{max}=max(cos(\theta ),cos(\theta -2\pi /3),cos(\theta +2\pi /3))$.

In case of an overcurrent, different limits can be applied depending on the sequence that is prioritized.

$$\mathrm{L}1:\{\begin{array}{}\mathrm{(6)}& I_1^{*}=min\left(I_1^{ref},I_{1lim}\right)\hfill \mathrm{(7)}& I_2^{*}=min\left(I_2^{ref},{\displaystyle \frac{-2I_1^{*}cos{(\theta )}_{max}+\sqrt{{(2I_1^{*}cos{(\theta )}_{max})}^2-4(I_1^{*2}-I_{lim}^2)})}{2}}\right)\hfill \end{array}$$

$$\mathrm{L}2:\{\begin{array}{}\mathrm{(8)}& I_2^{*}=min\left(I_2^{ref},I_{2lim}\right)\hfill \mathrm{(9)}& I_1^{*}=min\left(I_1^{ref},{\displaystyle \frac{-2I_2^{*}cos{(\theta )}_{max}+\sqrt{{(2I_2^{*}cos{(\theta )}_{max})}^2-4(I_2^{*2}-I_{lim}^2)})}{2}}\right)\hfill \end{array}$$

$$\mathrm{L}3:\{\begin{array}{}\mathrm{(10)}& I_1^{*}=min\left(I_1^{ref},{\displaystyle \frac{I_{lim}}{\sqrt{I_1^2+I_2^2+2I_1{I}_{2}cos{\left(\theta \right)}_{max}}}}{I}_1^{ref}\right)\hfill \mathrm{(11)}& I_2^{*}=min\left(I_2^{ref},{\displaystyle \frac{I_{lim}}{\sqrt{I_1^2+I_2^2+2I_1{I}_{2}cos{\left(\theta \right)}_{max}}}}{I}_2^{ref}\right)\hfill \end{array}$$

where $I_1^{ref}$ and $I_2^{ref}$ are the current references before applying the saturation (hereinafter, they are referred to as non-saturated current references). $I_1^{*}$ and $I_2^{*}$ are the current references after applying the saturation if needed (hereinafter, they are referred to as saturated current references). $I_{1lim}$ and $I_{2lim}$ are the limits for the positive- and negative-sequence currents, respectively, and $I_{lim}$ is the limit for the total current. These limits may be equal or different depending on whether both sequences are required to be injected or not (subject to $I_{1lim}\le I_{lim}$ and $I_{2lim}\le I_{lim}$). For instance, for the limit L1, if $I_{1lim}=I_{lim}$, when the positive-sequence current reaches the saturation value, $I_1=I_{lim}$ according to Equation (6) and no negative-sequence current can be injected as per Equation (7). However, if $I_{1lim}<I_{lim}$, even if $I_1$ saturates, there is some margin for injecting negative-sequence current.

Note that in cases of unbalanced currents, these limits must be applied to the phase with the highest current, which is determined through the term $cos{(\theta )}_{max}$. L1 prioritizes the injection of positive-sequence current, L2 prioritizes the injection of negative-sequence current, and L3 limits both sequences in the same proportion.

The d- and q-axis current references of the positive sequence are obtained as:

$$\mathrm{L}4:\{\begin{array}{}\mathrm{(12)}& I_{1d}^{*}=min\left(I_{1d}^{ref},I_{1dlim}\right)\hfill \mathrm{(13)}& I_{1q}^{*}=min\left(I_{1q}^{ref},\sqrt{I_{1lim}^2-I_{1d}^{*2}}\right)\hfill \end{array}$$

$$\mathrm{L}5:\{\begin{array}{}\mathrm{(14)}& I_{1q}^{*}=min\left(I_{1q}^{ref},I_{1qlim}\right)\hfill \mathrm{(15)}& I_{1d}^{*}=min\left(I_{1d}^{ref},\sqrt{I_{1lim}^2-I_{1q}^{*2}}\right)\hfill \end{array}$$

$$\mathrm{L}6:\{\begin{array}{}\mathrm{(16)}& I_{1d}^{*}=min\left(I_{1d}^{ref},{\displaystyle \frac{I_{1lim}}{\sqrt{{\left(I_{1d}^{ref}\right)}^2+{\left(I_{1q}^{ref}\right)}^2}}}{I}_{1d}^{ref}\right)\hfill \mathrm{(17)}& I_{1q}^{*}=min\left(I_{1q}^{ref},{\displaystyle \frac{I_{1lim}}{\sqrt{{\left(I_{1d}^{ref}\right)}^2+{\left(I_{1q}^{ref}\right)}^2}}}{I}_{1q}^{ref}\right)\hfill \end{array}$$

where $I_{1d}^{ref}$ and $I_{1q}^{ref}$ are the non-saturated current references for the d- and q-axis, respectively. $I_{1d}^{*}$ and $I_{1q}^{*}$ are the saturated current references for the d- and q-axis, respectively. $I_{1dlim}$ and $I_{1qlim}$ are the limits for the positive-sequence active and reactive currents, respectively, subject to $I_{1dlim}\le I_{1lim}$ and $I_{1qlim}\le I_{1lim}$. $I_{1lim}$ is the limit for the total current. L4 prioritizes the injection of active power (positive-sequence), L5 prioritizes the injection of reactive power (positive-sequence), and L6 limits both components in the same proportion.

Similar expressions are used to compute the d- and q-axis current references of the negative-sequence current:

$$\mathrm{L}7:\{\begin{array}{}\mathrm{(18)}& I_{2d}^{*}=min\left(I_{2d}^{ref},I_{2dlim}\right)\hfill \mathrm{(19)}& I_{2q}^{*}=min\left(I_{2q}^{ref},\sqrt{I_{2lim}^2-I_{2d}^{*2}}\right)\hfill \end{array}$$

$$\mathrm{L}8:\{\begin{array}{}\mathrm{(20)}& I_{2q}^{*}=min\left(I_{2q}^{ref},I_{2qlim}\right)\hfill \mathrm{(21)}& I_{2d}^{*}=min\left(I_{2d}^{ref},\sqrt{I_{2lim}^2-I_{2q}^{*2}}\right)\hfill \end{array}$$

$$\mathrm{L}9:\{\begin{array}{}\mathrm{(22)}& I_{2d}^{*}=min\left(I_{2d}^{ref},{\displaystyle \frac{I_{2lim}}{\sqrt{{\left(I_{2d}^{ref}\right)}^2+{\left(I_{2q}^{ref}\right)}^2}}}{I}_{2d}^{ref}\right)\hfill \mathrm{(23)}& I_{2q}^{*}=min\left(I_{2q}^{ref},{\displaystyle \frac{I_{2lim}}{\sqrt{{\left(I_{2d}^{ref}\right)}^2+{\left(I_{2q}^{ref}\right)}^2}}}{I}_{2q}^{ref}\right)\hfill \end{array}$$

where $I_{2d}^{ref}$ and $I_{2q}^{ref}$ are the non-saturated current references for the d- and q- axis, respectively. $I_{1d}^{*}$ and $I_{1q}^{*}$ are the saturated current references for the d- and q-axis, respectively. $I_{2dlim}$ and $I_{2qlim}$ are the limits for the negative-sequence active and reactive currents, respectively, subject to $I_{2dlim}\le I_{2lim}$ and $I_{2qlim}\le I_{2lim}$. $I_{2lim}$ is the limit for total current. L7 prioritizes the injection of active power (negative-sequence), L8 prioritizes the injection of reactive power (negative-sequence), and L9 limits both components in the same proportion.

In normal operation and considering balanced grid voltages, the current references for the positive sequence ($I_{1d}^{ref}$ and $I_{1q}^{ref}$) are computed from the active and reactive power references ($P_1^{ref}$ and $Q_1^{ref}$, respectively) while the negative-sequence currents ($I_{2d}^{ref}$ and $I_{2q}^{ref}$) are set to zero.

$$I_{1d}^{ref}={\displaystyle \frac{P_1^{ref}}{3V_{1d}}}$$

(24)

$$I_{1q}^{ref}=-{\displaystyle \frac{Q_1^{ref}}{3V_{1d}}}$$

(25)

$$I_{2d}^{ref}=0$$

(26)

$$I_{2q}^{ref}=0$$

(27)

In case of a fault, the reactive current references are computed according to the Spanish Grid Code (see Figure 1, [15]):

$$I_{1q}^{ref}=I_{1qi}-K_1(V_{1i}-V_1)$$

(28)

$$I_{2q}^{ref}=I_{2qi}-K_2(V_{2i}-V_2)$$

(29)

where $I_{1qi}$ and $I_{2qi}$ are the pre-fault positive and negative q-axis (reactive) currents, respectively, in per-unit terms. Similarly, $V_{1i}$ and $V_{2i}$ are the pre-fault positive- and negative-sequence voltages in per-unit terms. $K_1$ and $K_2$ are the proportional gains (also called k-factor in the literature), which can be set in the range $2\le K_{1,2}\le 6$. If the TSO does not specify any value, they are set to 3.5.

The Spanish Grid Code also states that the sign of the reactive current must be such that the MMC behaves like a synchronous generator. In the event of a fault, synchronous generators inject positive-sequence reactive current ($Q_1>0$), which helps to minimize voltage drops, and absorb negative-sequence reactive current ($Q_2<0$), which helps to reduce voltage imbalances in case of an asymmetrical fault. For the MMC, with the SRFs aligned with the d-axis, the reactive power can be computed as $Q=-3V_d{I}_q$. To inject positive-sequence reactive power, the value of $I_{1q}$ must be negative. Conversely, to absorb negative-sequence reactive power, the value of $I_{2q}$ must be positive. Thus, considering positive values for the gains $K_1$ and $K_2$, the sign before these constants must be negative.

The grid code, therefore, defines the reactive current increments in order to minimize voltage sags (positive-sequence reactive current) and voltage imbalances (negative-sequence reactive current). It prioritizes the injection of positive-sequence reactive current up to a value of 0.9 pu, while the remaining current capability is used for the injection of negative-sequence reactive current and positive-sequence active current.

4. Current Saturation Strategies

4.1. Output Current Saturation with Fixed Limits: Saturation Algorithm 1 (sat1)

Fixed saturation limits for the output currents are usually employed; however, these do not guarantee that the maximum current is injected. For instance, consider the following saturation logic. The positive-sequence reactive current is prioritized up to the limit $I_{1qlim}=0.9$ pu as per Equation (14). Then, positive-sequence active current is injected according to Equation (15) up to the limit $I_{1lim}=0.92$ pu. Finally, the remaining current capacity is used for injecting negative-sequence reactive current according to Equation (7).

Consider that the power generated by the MMC is P = 1 pu ($I_{1ai}=0.92$ pu) and Q = 0 pu ($I_{1ri}=0$ pu). If a three-phase voltage sag of 0.5 pu takes place, the non-saturated references for the positive- and negative-sequence reactive currents, according to Equations (28) and (29), are $I_{1q}^{ref}=0-3.5(1-0.5)=-1.75$ pu and $I_{2q}^{ref}=0-3.5(0-0)=0$ pu. The non-saturated reference of the positive-sequence active current will double because the voltage is halved ($I_{1a}=1.84$ pu).

The positive-sequence reactive current will be limited to 0.9 pu and the active current to 0.19 pu ($\sqrt{0.{92}^2-0.9^2}$). The remaining current capability of the converter is kept for the negative-sequence current. However, in this case, the negative-sequence current is zero; hence, the current injection is not maximized.

4.2. Output Current Saturation with Dynamic Limits: Saturation Algorithm 2 (sat2)

To overcome the aforementioned problem, if any of the currents $I_{1r}$, $I_{1a}$, or $I_{2r}$ are saturated while the output current $I$ is not, their limits can be increased until either the output current limit is reached or the currents are no longer saturated. The currents that saturate depend on the fault type, the voltage drop and the pre-fault active power. Therefore, a saturation scheme that dynamically adjusts the limits is proposed.

Figure 5 shows the algorithm that is used to maximize the current that is injected by the MMC when the saturation is applied to the output AC current. This consists of the following steps:

• Step 1: Define the limits of the output current ($I_{lim}$) and the positive-sequence current ($I_{1lim}$). In the figure, these limits are set to $I_{lim}=1.2$ pu (assuming a 20% overload capability) and $I_{1lim}=0.92r$ pu (with $r=1$), but other values could be used. To maximize the injected current, the positive sequence current limit is adjusted through an iterative process that modifies the variable r. Initially, this variable is set to 1. For subsequent iterations, an updated value of r is computed using its value in the two previous iterations, which are denoted as $r_1$ and $r_2$, respectively. Since there are no prior values of r for the second iteration, the initial values of 0.8 and 1.35 are assigned to $r_1$ and $r_2$, respectively.
• Step 2: Compute the positive- and negative-sequence voltages ($V_{1d}$ and $V_{2d}$) and their angles (${\theta }_1$ and ${\theta }_2$) from the grid measurements by using the SOGI and the PLL (see Figure 3).
• Step 3: Compute the non-saturated positive-sequence reactive current reference ($I_{1q}^{ref}$) according to the grid code (Equation (28)) and the non-saturated positive-sequence active current reference ($I_{1d}^{ref}$) from the active power reference (Equation (24)).
• Step 4: Obtain the saturated current references $I_{1d}^{*}$ and $I_{1q}^{*}$ of the positive-sequence according to Equations (15) and (14), respectively. Note that the injection of the reactive current is prioritized. The limit $I_{1qlim}$ is set at 0.9 according to the Spanish Grid Code.
• Step 5: Compute the magnitude ($I_1^{*}$) and the angle (${\theta }_{1i}$) of the saturated positive-sequence current.
• Step 6: Compute the non-saturated reference of the negative-sequence reactive current ($I_{2q}^{ref}$) according to the grid code (Equation (29)).
• Step 7: Compute the magnitude ($I_2^{ref}$) and the angle (${\theta }_{2i}$) of the negative-sequence current.
• Step 8: Compute $cos{(\theta )}_{max}$ to determine the phase with the highest current. Note that it is necessary to know the angles ${\theta }_1$, ${\theta }_2$, ${\theta }_{1i}$ and ${\theta }_{2i}$. The first three angles were already calculated in steps 2 and 5. ${\theta }_{2i}$ depends on the values of the active and reactive currents. However, given that the negative-sequence active current is always set to zero, ${\theta }_{2i}$ is always ${90}^{\circ }$, regardless of the saturation.
• Step 9: The maximum negative-sequence current is calculated using $I_1^{*}$ and the output current limit according to Equation (5). Using Equation (7), the saturated negative-sequence current reference ($I_{2q}^{*}$) is calculated (note that $I_2^{*}=I_{2q}^{*}$ given that $I_{2d}^{ref}=0$).
• Step 10: Using the saturated currents $I_1^{*}$ and $I_2^{*}$, and $cos{(\theta )}_{max}$, the output current of the phase with the highest value is computed using Equation (5).
• Step 11: Four cases may occur:

  −

  $I_1^{*}<I_{1lim}$ and $I_{max}<I_{lim}$: None of the currents saturate; hence, the MMC tracks its current references and the loop ends.

  −

  $I_1^{*}=I_{1lim}$ and $I_{max}=I_{lim}$: Both currents are saturated; hence, the MMC injects its maximum current according to the grid code. The loop ends.

  −

  $I_1^{*}=I_{1lim}$ and $I_{max}<I_{lim}$: The positive-sequence current reaches its limit but the output current does not (for instance, for a three-phase short-circuit that does not require injecting negative-sequence current). In this case, the loop returns to the first step and increases the limit of the positive-sequence current. This is achieved by means of the variable r, which is modified in each iteration to search for the current limits.

  −

  $I_1^{*}<I_{1lim}$ and $I_{max}=I_{lim}$: The MMC tracks the positive-current reference because $I_1^{*}$ is not saturated. The remaining margin is assigned to the negative-sequence current up to the output current limit. The loop ends because the output current reaches its limit.

4.3. Arm Current Saturation with Dynamic Limits: Saturation Algorithm 3 (sat3)

The current flowing through the upper ($i_u$) and lower ($i_l$) arms is:

$$i_u={\displaystyle \frac{I_{dc}}{3}}+{\displaystyle \frac{1}{2}}i$$

(30)

$$i_l={\displaystyle \frac{I_{dc}}{3}}-{\displaystyle \frac{1}{2}}i$$

(31)

where $I_{dc}$ is the pole DC current and $i$ is the output AC current of the MMC.

In case of a fault, the active power injected into (or absorbed from) the grid is reduced because of the voltage drop and the prioritization of the reactive current according to the grid codes. Consequently, the term $I_{dc}/3$ is small. On the other hand, applying the limits presented in Section 4.1 and Section 4.2 to the output AC current, the maximum value of $i/2$ remains unchanged regardless of the active power that is transmitted. Thus, since the current through the MMC arms consists of both a DC and an AC component, during a fault, the DC component decreases while the maximum value of the AC component remains unchanged. As a result, the current through the arms of the MMC is below its limits.

The rated output current of the MMC is:

$$\begin{array}{c}\hfill I_{1,rated}={\displaystyle \frac{S_{MMC}}{3V_{1,rated}}}={\displaystyle \frac{P_{MMC}}{3V_{1,rated}cos({\varphi }_{1,rated})}}\end{array}$$

(32)

The relation between the DC and the AC currents is:

$$\begin{array}{c}\hfill I_{dc}={\displaystyle \frac{3I_1{V}_{1}cos({\varphi }_1)}{2V_{dc}}}\end{array}$$

(33)

where $V_1$ is the positive-sequence rms value of the output AC voltage (line-to-ground voltage), $I_1$ is the positive-sequence rms value of the output AC current, $I_{dc}$ and $V_{dc}$ are the DC current and the pole-to-ground DC voltage, respectively, and $cos({\varphi }_1)$ is the power factor of the positive sequence.

The rated peak current of the upper and the lower arms of the MMC is:

$$\begin{array}{c}\hfill {\widehat{I}}_{u,l,rated}={\displaystyle \frac{I_{1,rated}{V}_{1,rated}cos({\varphi }_{1,rated})}{2V_{dc}}}+{\displaystyle \frac{\sqrt{2}}{2}}{I}_{1,rated}\end{array}$$

(34)

If the power factor decreases because the active power is reduced; the first term on the right-hand side of Equation (34) decreases and the second term can be increased without exceeding the arm limits.

$$\begin{array}{c}\hfill {\displaystyle \frac{I_1{V}_{1,rated}cos(\varphi )}{2V_{dc}}}+{\displaystyle \frac{\sqrt{2}}{2}}{I}_1={\displaystyle \frac{I_{1,rated}{V}_{1,rated}cos({\varphi }_{1,rated})}{2V_{dc}}}+{\displaystyle \frac{\sqrt{2}}{2}}{I}_{1,rated}\end{array}$$

(35)

From Equation (35), the maximum rms output current is:

$$\begin{array}{c}\hfill I_1={\displaystyle \frac{\frac{V_{1,rated}cos({\varphi }_{1,rated})}{V_{dc}}+\sqrt{2}}{\frac{V_{1,rated}cos({\varphi }_1)}{V_{dc}}+\sqrt{2}}}{I}_{1,rated}\end{array}$$

(36)

The AC and DC voltages are related by the modulation factor:

$$\begin{array}{c}\hfill V_1=m{\displaystyle \frac{V_{dc}}{\sqrt{2}}}\end{array}$$

(37)

Replacing Equation (37) in Equation (36):

$$\begin{array}{c}\hfill I_1={\displaystyle \frac{m·cos({\varphi }_{1,rated})+2}{m·cos({\varphi }_1)+2}}{I}_{1,rated}\end{array}$$

(38)

Note that as the value of $cos({\varphi }_1)$ decreases, the current $I_1$ increases. In case of a fault, the grid codes prioritize the injection of reactive current; hence, the term $cos({\varphi }_1)$ is small. The maximum value of the output current that does not exceed the arm limit occurs when the DC current is zero, that is, when $cos(\varphi )=0$.

$$\begin{array}{c}\hfill I_{max}=\left(1+{\displaystyle \frac{m}{2}}cos({\varphi }_{1,rated})\right)I_{1,rated}\end{array}$$

(39)

With the parameters provided in Table 1, the term inside the parentheses in Equation (39) is 1.39. Hence, the output current can be increased by 39% with respect to the rated output current without exceeding the arm current limit. This is a theoretical value that is only achieved when the active power drops to zero. However, in the event of a voltage sag, the injection of reactive power should be prioritized to ensure the voltage stability. Moreover, a reduced AC voltage also limits the active power that can be exchanged with the ac grid. Thus, despite the injection of active power, the current increase does not change considerably. On the other hand, in power converters, the most critical components are the semiconductor devices. Other components, such as transformers, disconnectors, and cables can typically withstand much higher currents than IGBTs for short periods. All these components are also used in conventional power plants that are based on synchronous generators, which can inject fault currents of up to approximately 6 times their rated current. Therefore, increasing the output current by 39% should not pose significant issues.

To maximize the current injected by the MMC, the current limit has to be applied to the arm current according to the flow chart shown in Figure 6. The algorithm is the same as that explained in Section 4.2 except for the last two steps, which are as follows:

• Step 10: Using the saturated currents $I_1^{*}$ and $I_2^{*}$, and $cos{(\theta )}_{max}$, the output current of the phase with the highest value ($I_{max}$) is computed using Equation (5). Additionally, the DC current $I_{dc}$ is calculated using Equation (33).
• Step 11: Using the phase with the highest output current and the DC current, the arm with the highest current is computed (Equation (34)). Note that the grid voltage $V_{1d}$, obtained in step 2, the output current $I_{max}$, and the DC current $I_{dc}$, calculated in step 10, are used instead of the rated values in Equation (34).
• Step 12: Three cases may occur:

  −

  $I_{1q}^{*}<I_{1r}^{ref}$ and $I_{1d}^{*}<I_{1d}^{ref}$ and $I_{2q}^{*}<I_{2q}^{ref}$: Since none of the currents reach saturation, the MMC is able to track the current references, and the control loop terminates.

  −

  $I_{1q}^{*}=I_{1q}^{ref}$ or $I_{1d}^{*}=I_{1d}^{ref}$: The positive-sequence current saturates.

  ∘

  $I_{arm}^{*}<I_{arm,lim}$: The arm current does not saturate; hence, the negative-sequence component does not saturate either. Therefore, there is still some margin to increase the positive-sequence current. In this case, the loop returns to the initial step and increases both the output current limit and the positive-sequence current limit. This is achieved through the variable r, which is modified in each iteration to search for the current limits.

  ∘

  $I_{arm}^{*}=I_{arm,lim}$: The arm current saturates and the loop ends.

5. Results

The saturation algorithms presented in Section 4.2 and Section 4.3 are compared for seven types of voltage dips (see Figure 7). In this figure, E is the pre-fault voltage, which is considered to be 1 pu, and V is the retained voltage in the phase or phases affected by the fault. Although all types of fault (three-phase, two-phase, phase-to-ground, and phase-to-phase-to-ground faults) may happen, the most common fault is, by far, the phase-to-ground fault (70–80% of the cases). Three-phase faults represent only 2–3% of the cases while phase-to-phase-to-ground faults account for 10–17% and phase-to-phase faults account for 8–10% of the cases [32]. Apart from the voltage (magnitude) imbalance caused by asymmetrical faults, the transformer connection may also cause phase imbalances.

Figure 8 shows the theoretical results for voltage dips ranging from 0 pu to 1 pu:

• Top-left graph: It shows the output AC current considering the saturation algorithms described in Section 4.2 (red line) and Section 4.3 (blue line). In both cases, the phase with the highest current is plotted.
• Bottom-left graph: The ratio of the output current with saturation strategy 3 to the output current with saturation strategy 2 is plotted.
• Top-center graph: It shows the output positive-sequence reactive current ($I_{1r}=I_{1q}$), the positive-sequence active current ($I_{1a}=I_{1d}$), and the negative-sequence reactive current ($I_{2r}=I_{2q}$). Again, the saturation algorithm described in Section 4.2 (dashed lines) is compared with the saturation algorithm described in Section 4.3 (solid lines). In both cases, the phase with the highest current is plotted.
• Bottom-center graph: The ratio of the sequence currents with saturation strategy 3 to the sequence currents with saturation strategy 2 is plotted.
• Top-right graph: It shows the peak arm current of the MMC considering the saturation algorithms presented in Section 4.2 (red line) and that in Section 4.3 (blue line). In both cases, the arm with the highest current is plotted.
• Bottom-left graph: The ratio of the arm current with saturation strategy 3 to the arm current with saturation strategy 2 is plotted.

Figure 8 shows the results for a type E voltage dip when the MMC delivers P = 400 MW (0.92 pu) and Q = 0 MVAr (0 pu). For this type of asymmetrical voltage dip, the grid voltage consists of both positive and negative sequences. As a result, according to the aforementioned grid codes, positive- and negative-sequence reactive currents have to be injected into the grid according to Equations (28) and (29). Moreover, given that the Spanish Grid Code requires the power converter to behave like a synchronous generator, a positive-sequence reactive power must be injected (thus, a negative value of $I_{1q}$ is required) and a negative-sequence reactive power must be absorbed (hence, a positive value of $I_{2q}$ is needed).

The theoretical results have been obtained considering that the phasor values of the phase-to-ground voltages at the MMC connection point are those shown in Figure 7. Using these values, the positive- and negative-sequence voltages are obtained by means of Fortescue’s theorem. Next, the saturation algorithms are applied to the reactive current references according to Equations (28) and (29). The current references are then saturated according to the algorithms presented in Section 4. Once the output active and reactive positive- and negative-sequence currents are known, the current of the phase with the highest value is computed using Equation (4). Finally, the current through the arm with the highest value is calculated using Equation (30).

Focusing on the top-center graph and the dashed lines (saturation algorithm 2), it can be observed that, as the voltage drops below 1 pu, both the positive- and the negative-sequence reactive currents increase. Simultaneously, to keep the same active power injection, the active current must increase. For small voltage dips, the negative-sequence current is low; hence, the positive-sequence limit ($I_{1lim}$) is increased beyond its initial value of 0.92 pu to accommodate the increasing active current and leverage the overall current capability of the converter. For $V_x=0.87$ pu, $I_{1q}$ is $-0.303$ pu and $I_{1a}$ is $1.006$ pu, resulting in $I_1=1.051$ pu. This implies that the positive-sequence limit has been increased from its initial value of 0.92 pu to 1.051 pu due to the low negative-sequence current demand, thereby maximizing the injection of fault current. However, at this point, the output current saturates for sat2 (see the top-left graph), indicating that the converter can no longer track all the current references below this voltage level. Consequently, $I_{1d}$ begins to decrease.

For $V_x=0.76$ pu, $I_{1q}$ is $0.56$ pu and $I_{1a}$ is $0.733$ pu, resulting in $I_1=0.92$ pu. At this point, the positive-sequence current limit is 0,92 and cannot be reduced any further. Consequently, the negative-sequence current saturates.

For $V_x=0.61$ pu, $I_{1q}$ is $0.9$ pu and $I_{1a}$ is $0.191$ pu, resulting in $I_1=0.92$ pu. The positive-sequence reactive current saturates to 0.9 pu, and the remaining current capability for the positive-sequence current (up to 0.92 pu) is used for the active current. The current margin up to 1.2 pu is allocated to the negative-sequence current. At this point, all the currents are saturated; therefore, they remain constant for voltages below 0.61 pu.

The same analysis can be carried out for the solid lines, which correspond to saturation strategy 3. In this case, the arm current saturates for a voltage dip with a lower retained voltage ($V_x=0842$ pu), which indicates that all the currents are higher at the instant they begin to saturate. This can be seen in Figure 8, where the solid lines are above the dashed lines.

The bottom-center graph shows the ratio between the currents injected into the grid using both saturation algorithms. For small voltage dips, the currents do not saturate so the same currents are injected into the grid with both saturation algorithms, resulting in a ratio of one.

For $V_x=0.84$, the active current saturates and the ratio of the positive-sequence current is greater than one, indicating that higher active currents can be injected into the grid with saturation algorithm 3. Conversely, since neither the positive- nor negative-sequence currents are saturated, the same reactive currents are injected with both algorithms, keeping the ratio at one.

For $V_x=0.72$, the negative-sequence current reaches its limit for saturation algorithm 2, while it does not saturate for saturation algorithm 3, which allows higher negative-sequence currents to be injected into the grid. In this case, the ratio is greater than 1. At this point, the positive-sequence current is not saturated so this current is the same for both saturation algorithms. For $V_x=0.61$ pu, $I_{1q}$ reaches its limit when saturation strategy 2 is used, while it does not reach its limit when saturation strategy 3 is utilized; hence, the ratio increases.

Finally, for $V_x=0.48$ pu, all the currents saturate for algorithm 3. Below this voltage, the ratio for all the currents is around 1.36; hence, they increase by 36%. All the currents increase in the same proportion as defined in Figure 6, although other strategies could also be utilized. Therefore, the currents injected into the grid when strategy 3 is used are always higher than those injected using strategy 2, except for low-voltage dips in which the currents do not saturate.

The top-right graph shows the arm current. For saturation strategy 2, the output current saturates when $V_x=0.87$ pu; therefore, at this point, the arm current reaches its maximum value. For lower retained voltages, the arm current does not increase; therefore, the AC current through the arms remains constant. However, as the voltage drops, the active power decreases and the DC current through the arms also decreases. As a result, the arm current remains below 0.9 pu for voltages lower than 0.4 pu. Conversely, when saturation strategy 3 is applied, the arm current saturates at 1.2 pu. The bottom-right graph shows the ratio of the arm currents between both saturation techniques.

The top-left graph shows the output current. For saturation strategy 2, the output current is limited to 1.2 pu; however, it keeps increasing as the voltage drops for saturation strategy 3. This is due to the reduction in the arm DC current, which allows for higher AC currents. The bottom-left graph shows the output current ratio. Note that the output current is increased by 36% when saturation strategy 3 is used. Theoretically, the maximum increase is 39%, as computed in Section 4 (see Equation (39)). In this case, such a value is not reached because some active power is still injected into the grid; thus, some DC current flows through the arms. If the limits $I_{1qlim}$ and $I_{1lim}$ were the same, all the positive-sequence current would be reactive and the active current would be zero. In this scenario, no DC circulating current would flow through the arms and an increase of 39% would be reached.

The same analysis can be carried out for the other types of voltage sags, leading to similar conclusions. Therefore, the detailed analysis is omitted here but the results are presented in Appendix B (Figure A2, Figure A3, Figure A4, Figure A5, Figure A6, Figure A7).

Table 2. Output current increase in % for strategy 3 and five voltage sag dips.

Voltage Sag Type	Voltage Dip
	0 pu	0.20 pu	0.40 pu	0.60 pu	0.80 pu
A	38%	36%	34%	26%	8%
B	31%	23%	16%	11%	3%
C	35%	34%	27%	16%	9%
D	35%	34%	27%	16%	9%
E	36%	35%	34%	23%	9%
F	36%	35%	34%	23%	9%
G	36%	35%	34%	23%	9%

provides a summary of the current increase for saturation strategy 3 under different voltage sags.

Simulation Results

To verify the proposed saturation algorithms, detailed PSCAD simulations have been carried out. The MMC presented in Section 3 is connected to an AC grid and several voltage sags are applied. The voltage sag is simulated by changing the voltage at the connection point of the MMC.

Figure 9a and Figure 9b show the PSCAD results for saturation strategies 2 and 3, respectively. The following data are plotted from top to bottom: (1) phase-to-ground voltages at the point of connection of the MMC; (2) output current of the MMC; (3) d- and q-components of the voltage at the point of connection for the positive and negative sequences; (4) d- and q-components of the output current for the positive and negative sequences, that is, the active and the reactive currents of each sequence; (5) upper and lower arm currents of the MMC for the phase with the highest current; (6) average upper and lower submodule capacitor voltages of the phase with the highest current.

The MMC is initially injecting into the grid 400 MW (0.92 pu) and 0 MVAr (0 pu). At t = 0.02 s, a two-phase voltage dip occurs (first graph) with a retained voltage of 0.3 pu. This causes a rapid increase in the output current (second graph). The SOGI detects the asymmetrical conditions and separates the positive- and negative-sequence voltages. Then, the PLLs align the d-axis of the positive and the negative reference frames with the corresponding grid voltages. This can be seen in the third graph where the q-components of both sequence voltages are zero, while $V_{1d}$ is 0.535 pu and $V_{2d}$ is 0.235 pu. Once the voltage dip is detected, the current references of the positive- and the negative-sequence reactive currents are determined based on the grid codes. According to Equations (28) and (29), the values of the non-saturated current references are $I_{1q}^{ref}=0-3.5(1-0.535)=1.628$ pu and $I_{2q}^{ref}=-3.5(0-0.235)=0.825$ pu, respectively. The non-saturated reference of the positive-sequence active current is $I_{1a}^{ref}=0.92/0.535=1.720$ pu. The previous values would cause a high overcurrent in the MMC; therefore, they must be limited.

For saturation strategy 2 (Figure 9a), the current $I_{1q}$ is limited to 0.9 pu. The value of $I_{1d}$ is 0.19 pu, which corresponds to the positive-sequence current limit of 0.92 pu ($\sqrt{0.{92}^2-0.9^2}=0.19$ pu). The remaining current capacity is used to inject negative-sequence reactive current, resulting in a value of 0.363 pu. These values match with the theoretical ones shown with dashed lines in the top-center graph of Figure 8. The output current of the phase with the highest value is 1.2 pu (second graph). Since the saturation is applied to the output current, the value of the arm current is only 0.91 pu, which matches with the value shown in the top-right graph of Figure 8. The voltage dip causes a disturbance in the capacitor voltages of the submodules; however, the inner energy control effectively stabilizes them. The capacitor voltages are restored to their reference values within approximately 150 ms (sixth graph).

For saturation strategy 3 (Figure 9b), the limits of the output current and the positive-sequence currents are increased until the arm current reaches its limit. In this case, the current $I_{1q}$ is limited to 1.164 pu and the current $I_{1d}$ to 0.248 pu, which corresponds to a positive-sequence current limit of 1.19 pu. The remaining current capacity is used to inject negative-sequence reactive current, resulting in a value of 0.489 pu. These values match with the theoretical ones shown with solid lines in the top-center graph of Figure 8. The output current for the phase with the highest value is 1.60 pu (second graph), which matches with the value shown in the top-left graph of Figure 8. Since the saturation is now applied to the arm current, its value is 1.2 pu. Again, the inner energy control effectively controls the capacitor voltages of the submodules to 1.6 kV within approximately 150 ms (sixth graph).

One-phase and three-phase voltage dips have also been simulated in PSCAD. The results are similar to those presented in Figure 9 for a two-phase voltage dip; therefore, the analysis is not repeated here, although the results are included in Appendix B (Figure A8 and Figure A9).

Finally, the system shown in Figure 10 has been simulated. It consists of a 400 MW offshore wind power plant connected to the inland grid through an HVDC link. The onshore MMC is connected to an AC grid with an SCR of 5 through two parallel 60 km long AC transmission lines. Given that the objective is to analyze the response of MMC2 in the event of an AC fault, the wind power plant and the offshore MMC have been replaced by a DC source. The system parameters are listed in

Table 3. System parameters.

Description	Parameter	Value
Nominal voltage (line-to-line)	$V_G$	220 kV
Resistance of the grid	$R_G$	$2.41\Omega$
Inductance of the grid	$L_G$	$76.65$ mH
Resistance of the line	$r_l$	7 × ${10}^{-5}$ $\Omega$/m
Inductive reactance of the line	$x_l$	4 × ${10}^{-4}$ $\Omega$/m
Capacitive reactance of the line	$x_c$	385 M$\Omega$m
Length of the line	$l_l$	60 km
Voltage ratio of the transformer	$r_T$	260/220 kV
Rated power of the transformer	$S_T$	450 MVA
Leakage inductance of the transformer	$L_T$	47.82 mH (220 kV side)

. The parameters of the MMC are those included in Table 1.

The wind power plant is delivering 400 MW when a phase-to-phase fault occurs at t = 0.02 s, with zero ohms fault resistance, located at 90% of the length of one of the AC transmission lines. The protective relays at both ends of the line (R1 and R2, respectively) should detect the fault and isolate it by tripping. Considering distance relays [34], R1 would identify the fault in zone 2 because it is beyond 80% of the line length. Unless teleprotection schemes with communication signals are used, the trip of the relay for a fault in zone 2 is intentionally delayed about 300–500 ms. Figure 11 shows the results for saturation algorithms 2 and 3. For saturation strategy 2, the low injected currents provoke the malfunction of the SOGI-PLL, which is not able to obtain the sequence voltages and align the d-xis of the reference frames with the grid voltage. As a result, the MMC loses synchronism, which causes overcurrents that would trip the converter.

On the other hand, with saturation strategy 3, the SOGI-PLL keeps working properly and the MMC is able to remain connected to the grid and inject active and reactive power. Saturation strategy 3 allows for larger currents that increase the retained voltage and reduce the unbalance. Therefore, the MMC can ride through the fault and resume normal operation as soon as the fault is isolated by the relays and their breakers.

Note that during the first cycle after the fault onset, the control of the MMC is not able to effectively limit the fault currents to 1.2 pu due to the system and control dynamics, as well as the time required to compute the sequence components. To avoid high overcurrents that could damage the power semiconductor devices, the MMC is temporarily blocked and immediately deblocked. This process is repeated several times if required, which allows the converter to remain connected to the grid. The limit for blocking the converter is set at 1.35 pu, which provides some margin and coordination over the saturation limit of 1.2 pu. If the current approaches the maximum repetitive peak forward current of the IGBTs (typically around 2 pu), the MMC would be permanently blocked and the AC breaker would trip [35].

6. Conclusions

With the increasing number of renewable power plants, future power systems will be dominated by power electronic converters. In this context, MMCs are the preferred topology for high-voltage and high-power applications. However, power electronic converters present some challenges. In case of a fault, due to their limited overcurrent capability, retained voltages will be lower and voltage dips will spread further than in the case of power systems that are based on synchronous generation. This may lead to a malfunction of some controls like the PLL. Additionally, low voltages and currents may complicate the correct operation of the protective relays. To address this issue, several TSOs have developed new grid codes with updated requirements for power electronic converters. These include the need for fast current injection of both positive- and negative-sequence currents and fault current maximization.

The control of MMCs includes saturation limits in the output AC currents to avoid overcurrents. However, using fixed current limits for the positive-sequence and total output currents does not necessarily maximize the fault current, for instance, in case of a three-phase fault that does not require the injection of negative-sequence current. To address this, as a first improvement, this paper proposes dynamic limits that adjust the positive-sequence current limit as a function of the requirements for the negative-sequence current.

However, the current flowing through the power semiconductor devices is the arm current, not the output AC current. The arm current consists of half the AC current plus one-third of the DC current. In the event of a fault, the active power is significantly reduced, which leads to a reduction in the DC current. As a result, the output AC current can be increased without exceeding the arm current limits.

Therefore, as a second improvement, the saturation limit is applied to the arm current. The proposed algorithm for such a saturation strategy is detailed in the paper. The values of the output current with both saturation strategies are compared for several fault types and voltage dips and it is concluded that the output fault current can be increased by up to 40% when the arm current saturation is used. The theoretical analysis is validated with detailed PSCAD simulations. Finally, to illustrate the superiority of the arm saturation strategy, an example of a wind power plant connected to the AC grid through an MMC-based HVDC link is presented. This example shows that the higher fault currents injected into the grid when the arm saturation strategy is used allow for a more resilient fault ride-through.