Modular Multilevel Converter Control Strategy for AC Fault Current Maximization and Grid Code Compliance
Abstract
:1. Introduction
2. Grid Codes
- Capability of staying connected to the network within given ranges of the network voltage.
- Capability to provide fast fault current injection at the connection point in case of a symmetrical fault (in coordination with the relevant TSO).
- Asymmetrical current injection in case of an asymmetrical fault (in coordination with the relevant TSO).
- Fault-ride-through capability.
- Power park modules must be capable of managing the rapid injection of fault current through a continuous control system.
- They shall have the capability to inject apparent current per phase that is at least equal to their nominal current.
- For the positive-sequence current, power park modules must inject or absorb, depending on the positive-sequence voltage error , a reactive current (pu) through a continuous proportional control (see Figure 1). The default value for the limit of this current is pu.
- In addition to the total reactive current component , power park modules must inject an active current component.
- For the negative sequence current, power park modules must inject or absorb, depending on the negative sequence voltage error , a negative sequence current through a continuous proportional control (see Figure 1).
- For balanced faults, IBR units shall inject reactive current dependent on the terminal voltage of the IBR unit. The difference between the reactive current during a fault and the pre-fault reactive current is the incremental positive-sequence reactive current . During a fault condition, priority shall be given to reactive current injection with any residual capacity being supplied as active current unless the IBR unit is specified to operate in active current priority mode by the TSO.
- For unbalanced faults, in addition to increasing positive-sequence reactive current, the IBR unit shall inject negative-sequence current , dependent on IBR unit terminal negative-sequence voltage. If the IBR unit’s total current limit is reached, either or , or both may be reduced with a preference of equal reduction in both currents.
- This standard intentionally does not specify magnitude of incremental positive- and negative-sequence reactive current injection during a fault condition. The TSO should consider specifying the required magnitudes.
3. System and Control Description
4. Current Saturation Strategies
4.1. Output Current Saturation with Fixed Limits: Saturation Algorithm 1 (sat1)
4.2. Output Current Saturation with Dynamic Limits: Saturation Algorithm 2 (sat2)
- Step 1: Define the limits of the output current () and the positive-sequence current (). In the figure, these limits are set to pu (assuming a 20% overload capability) and pu (with ), but other values could be used. To maximize the injected current, the positive sequence current limit is adjusted through an iterative process that modifies the variable r. Initially, this variable is set to 1. For subsequent iterations, an updated value of r is computed using its value in the two previous iterations, which are denoted as and , respectively. Since there are no prior values of r for the second iteration, the initial values of 0.8 and 1.35 are assigned to and , respectively.
- Step 2: Compute the positive- and negative-sequence voltages ( and ) and their angles ( and ) from the grid measurements by using the SOGI and the PLL (see Figure 3).
- Step 4: Obtain the saturated current references and of the positive-sequence according to Equations (15) and (14), respectively. Note that the injection of the reactive current is prioritized. The limit is set at 0.9 according to the Spanish Grid Code.
- Step 5: Compute the magnitude () and the angle () of the saturated positive-sequence current.
- Step 6: Compute the non-saturated reference of the negative-sequence reactive current () according to the grid code (Equation (29)).
- Step 7: Compute the magnitude () and the angle () of the negative-sequence current.
- Step 8: Compute to determine the phase with the highest current. Note that it is necessary to know the angles , , and . The first three angles were already calculated in steps 2 and 5. depends on the values of the active and reactive currents. However, given that the negative-sequence active current is always set to zero, is always , regardless of the saturation.
- Step 9: The maximum negative-sequence current is calculated using and the output current limit according to Equation (5). Using Equation (7), the saturated negative-sequence current reference () is calculated (note that given that ).
- Step 10: Using the saturated currents and , and , the output current of the phase with the highest value is computed using Equation (5).
- Step 11: Four cases may occur:
- −
- and : None of the currents saturate; hence, the MMC tracks its current references and the loop ends.
- −
- and : Both currents are saturated; hence, the MMC injects its maximum current according to the grid code. The loop ends.
- −
- and : The positive-sequence current reaches its limit but the output current does not (for instance, for a three-phase short-circuit that does not require injecting negative-sequence current). In this case, the loop returns to the first step and increases the limit of the positive-sequence current. This is achieved by means of the variable r, which is modified in each iteration to search for the current limits.
- −
- and : The MMC tracks the positive-current reference because is not saturated. The remaining margin is assigned to the negative-sequence current up to the output current limit. The loop ends because the output current reaches its limit.
4.3. Arm Current Saturation with Dynamic Limits: Saturation Algorithm 3 (sat3)
- Step 11: Using the phase with the highest output current and the DC current, the arm with the highest current is computed (Equation (34)). Note that the grid voltage , obtained in step 2, the output current , and the DC current , calculated in step 10, are used instead of the rated values in Equation (34).
- Step 12: Three cases may occur:
- −
- and and : Since none of the currents reach saturation, the MMC is able to track the current references, and the control loop terminates.
- −
- or : The positive-sequence current saturates.
- ∘
- : The arm current does not saturate; hence, the negative-sequence component does not saturate either. Therefore, there is still some margin to increase the positive-sequence current. In this case, the loop returns to the initial step and increases both the output current limit and the positive-sequence current limit. This is achieved through the variable r, which is modified in each iteration to search for the current limits.
- ∘
- : The arm current saturates and the loop ends.
5. Results
- Top-left graph: It shows the output AC current considering the saturation algorithms described in Section 4.2 (red line) and Section 4.3 (blue line). In both cases, the phase with the highest current is plotted.
- Bottom-left graph: The ratio of the output current with saturation strategy 3 to the output current with saturation strategy 2 is plotted.
- Top-center graph: It shows the output positive-sequence reactive current (), the positive-sequence active current (), and the negative-sequence reactive current (). Again, the saturation algorithm described in Section 4.2 (dashed lines) is compared with the saturation algorithm described in Section 4.3 (solid lines). In both cases, the phase with the highest current is plotted.
- Bottom-center graph: The ratio of the sequence currents with saturation strategy 3 to the sequence currents with saturation strategy 2 is plotted.
- Top-right graph: It shows the peak arm current of the MMC considering the saturation algorithms presented in Section 4.2 (red line) and that in Section 4.3 (blue line). In both cases, the arm with the highest current is plotted.
- Bottom-left graph: The ratio of the arm current with saturation strategy 3 to the arm current with saturation strategy 2 is plotted.
Simulation Results
6. Conclusions
Author Contributions
Funding
Data Availability Statement
Conflicts of Interest
Abbreviations
GC | Grid Code |
HVDC | High-Voltage Direct Current |
MMC | Modular Multilevel Converter |
PEC | Power Electronic Converter |
PLL | Phase-Locked Loop |
SC | Synchronous Condenser |
SCL | Short-Circuit Level |
SG | Synchronous Generator |
SOGI | Second Order Generalized Integrator |
TSO | Transmission System Operator |
VSC | Voltage Source Converter |
Appendix A
Appendix A.1. Inner Control of the MMC
Appendix A.2. Control Parameters
Controllers/Filters | Values |
---|---|
1: positive sequence output current control | V/A, V/As |
: negative sequence output current control | V/A, V/As |
: total MMC energy control | W/J, W/Js |
: dc current control | V/A, V/As |
: leg energy control | W/J, W/Js |
: upper and lower arms common energy difference control | W/J, W/Js |
: upper and lower arms differential energy control | W/J, W/Js |
2: MMC circulating current control | V/A, V/As |
V/A, rad/s | |
Band reject filter 3 | Vs2/A, Vs/A |
V/A, s2 | |
s, |
Appendix B
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Description | Parameter | Value |
---|---|---|
Rated apparent power | 435 MVA | |
Rated active power | 400 MW | |
Arm inductance | 76.16 mH | |
Cells per arm | N | 315 (HB-SMs) |
Submodule capacitor | 6000 F | |
Line-to-line grid voltage | 260 kV | |
Angular frequency | rad/s | |
Pole-to-ground dc voltage | kV |
Voltage Sag Type | Voltage Dip | ||||
---|---|---|---|---|---|
0 pu | 0.20 pu | 0.40 pu | 0.60 pu | 0.80 pu | |
A | 38% | 36% | 34% | 26% | 8% |
B | 31% | 23% | 16% | 11% | 3% |
C | 35% | 34% | 27% | 16% | 9% |
D | 35% | 34% | 27% | 16% | 9% |
E | 36% | 35% | 34% | 23% | 9% |
F | 36% | 35% | 34% | 23% | 9% |
G | 36% | 35% | 34% | 23% | 9% |
Description | Parameter | Value |
---|---|---|
Nominal voltage (line-to-line) | 220 kV | |
Resistance of the grid | ||
Inductance of the grid | mH | |
Resistance of the line | 7 × /m | |
Inductive reactance of the line | 4 × /m | |
Capacitive reactance of the line | 385 Mm | |
Length of the line | 60 km | |
Voltage ratio of the transformer | 260/220 kV | |
Rated power of the transformer | 450 MVA | |
Leakage inductance of the transformer | 47.82 mH (220 kV side) |
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Vidal-Albalate, R.; Belenguer, E.; Magraner, F. Modular Multilevel Converter Control Strategy for AC Fault Current Maximization and Grid Code Compliance. Electronics 2025, 14, 1763. https://doi.org/10.3390/electronics14091763
Vidal-Albalate R, Belenguer E, Magraner F. Modular Multilevel Converter Control Strategy for AC Fault Current Maximization and Grid Code Compliance. Electronics. 2025; 14(9):1763. https://doi.org/10.3390/electronics14091763
Chicago/Turabian StyleVidal-Albalate, Ricardo, Enrique Belenguer, and Francisco Magraner. 2025. "Modular Multilevel Converter Control Strategy for AC Fault Current Maximization and Grid Code Compliance" Electronics 14, no. 9: 1763. https://doi.org/10.3390/electronics14091763
APA StyleVidal-Albalate, R., Belenguer, E., & Magraner, F. (2025). Modular Multilevel Converter Control Strategy for AC Fault Current Maximization and Grid Code Compliance. Electronics, 14(9), 1763. https://doi.org/10.3390/electronics14091763