Lusardi, N.; Garzetti, F.; Fiumicelli, G.; Morabito, M.; Bonanno, G.; Ronconi, E.; Costa, A.; Geraci, A.
First Study of Bubble Error Artifacts in Field-Programmable Gate Array (FPGA)-Based Tapped Delay-Line Time-to-Digital Converters with Sum-of-Ones Decoder on Xilinx 28 nm 7-Series FPGA. Electronics 2025, 14, 1156.
https://doi.org/10.3390/electronics14061156
AMA Style
Lusardi N, Garzetti F, Fiumicelli G, Morabito M, Bonanno G, Ronconi E, Costa A, Geraci A.
First Study of Bubble Error Artifacts in Field-Programmable Gate Array (FPGA)-Based Tapped Delay-Line Time-to-Digital Converters with Sum-of-Ones Decoder on Xilinx 28 nm 7-Series FPGA. Electronics. 2025; 14(6):1156.
https://doi.org/10.3390/electronics14061156
Chicago/Turabian Style
Lusardi, Nicola, Fabio Garzetti, Gabriele Fiumicelli, Mattia Morabito, Gabriele Bonanno, Enrico Ronconi, Andrea Costa, and Angelo Geraci.
2025. "First Study of Bubble Error Artifacts in Field-Programmable Gate Array (FPGA)-Based Tapped Delay-Line Time-to-Digital Converters with Sum-of-Ones Decoder on Xilinx 28 nm 7-Series FPGA" Electronics 14, no. 6: 1156.
https://doi.org/10.3390/electronics14061156
APA Style
Lusardi, N., Garzetti, F., Fiumicelli, G., Morabito, M., Bonanno, G., Ronconi, E., Costa, A., & Geraci, A.
(2025). First Study of Bubble Error Artifacts in Field-Programmable Gate Array (FPGA)-Based Tapped Delay-Line Time-to-Digital Converters with Sum-of-Ones Decoder on Xilinx 28 nm 7-Series FPGA. Electronics, 14(6), 1156.
https://doi.org/10.3390/electronics14061156
