A Millimeter-Wave CMOS Down-Conversion Mixer with Transformer-Based Harmonic Suppression

Abstract

In this paper, we present a millimeter-wave CMOS down-conversion mixer designed for 5G cellular communications. The proposed mixer integrates a local oscillator buffer, an RF transconductance (Gm) stage, and a switching stage. A transformer-based harmonic suppression technique and separate RF Gm stage and switching stage are employed to achieve a low noise figure (NF), high conversion gain (CG), and effective harmonic suppression. Intermodulation and gain characteristics are analyzed, demonstrating enhanced harmonic suppression, high gain, and low NF. Implemented in 65 nm CMOS technology, the proposed mixer occupies a core chip area of 0.51 mm² and consumes a dc power of 7 mW. The implemented design achieves a CG of 6.4 dB, an NF of 6.1 dB, and an output third-order intercept point of 9.0 dBm at an RF frequency of 38.2 GHz. Additionally, harmonic suppression exceeds −26 dBc, highlighting the performance advantages of the proposed architecture.

1. Introduction

Recently, the standardization of fifth-generation (5G) New Radio (NR) has garnered significant attention for its ability to enable high-speed data transmission and massive connectivity, leveraging millimeter-wave (mm-wave) frequency bands. Frequency Range 2 (FR2), spanning 24.25–71 GHz, includes bands such as 24–30 GHz and 36–42 GHz, which have been allocated to various countries [1,2,3]. In these frequency bands, phased-array techniques have been proposed to extend communication distances and improve data rates [4,5,6,7,8,9,10,11,12].

In mm-wave 5G transceivers, the mixer plays a critical role as it facilitates modulation, demodulation, and spectrum shifting. Key performance metrics for down-conversion mixers include high conversion gain (CG), low noise figure (NF), high linearity, effective harmonic suppression, and low power consumption. These parameters are essential to achieving optimal receiver performance in the mm-wave band.

Previous studies have made significant strides in developing wideband, multiband, and high-performance down-conversion mixers for mm-wave applications [13,14,15,16,17,18,19,20,21,22]. CMOS technology is widely adopted for its low cost and seamless integration with digital baseband circuits. Many mm-wave CMOS mixers utilize double-balanced Gilbert-cell topologies [15,18,19,22] or separate RF transconductance (Gm) and switching stages [14,16,17,20,21]. For example, a Gilbert-cell mixer with an intermediate frequency (IF) buffer amplifier achieves a high CG of 4.8 dB but suffers from a high NF of 13.5 dB and requires a large local oscillator (LO) input power of 5 dBm [15]. Similarly, mixers with separate switching and Gm stages demonstrate broadband performance using band-switchable capacitors and transformers but exhibit limited CG (<3.1 dB) and high NF (>11 dB) [16,17]. Efforts to enhance performance have introduced mixers with body self-forward bias [18], large-resistance loads [21], or multi-gate transistors [22]. While these designs achieve specific performance gains, they often encounter trade-offs such as high NF, limited CG, or poor LO-RF isolation. For instance, a mixer employing multi-gate transistors (MGTR) achieves exceptional linearity with an IIP3 of 20.87 dBm but exhibits poor CG (−14.4 dB) and NF (16.75 dB) [22].

To address these challenges, this study presents a mm-wave CMOS down-conversion mixer optimized for 5G handheld devices, including smartphones, virtual reality (VR), augmented reality (AR), and gaming consoles. The proposed mixer integrates an LO buffer amplifier, an RF Gm stage, and a switching stage while employing transformer-based harmonic suppression. This architecture achieves a CG of 6.4 dB, an NF of 6.1 dB, a LO-RF isolation exceeding 46 dB, and a 1 dB compression point (IP1dB) of −6 dBm. These results demonstrate that the proposed mixer is well-suited for low-power mm-wave 5G handheld applications.

2. Design Methodology

2.1. Design Considerations

Figure 1 illustrates the block diagram of the proposed down-conversion mixer designed for a super-heterodyne receiver. The mixer converts RF signals (37–41 GHz) to IF signals (10–12 GHz) using an LO frequency range of 27–29 GHz. The design includes a switching stage, an RF Gm stage, an LO buffer amplifier, and transformer-based harmonic suppression.

In conventional Gilbert-cell mixers, large parasitic capacitance at the drain of the Gm stage leads to reduced CG and degraded NF. Additionally, using a single current source for both the Gm stage and switching stage results in performance trade-offs: insufficient current in the Gm stage degrades CG and NF, while excessive current in the switching stage slows down switching speed, further impairing CG and NF. To address these challenges, the proposed mixer separates the Gm stage and switching stage, optimizing gain, NF, and linearity [23].

The LO buffer amplifier is designed with a variable gain function to compensate for input power variations and deliver optimal LO power to the switching stage [24]. Furthermore, in a super-heterodyne receiver, suppressing unwanted harmonics is essential to ensure signal integrity.

Figure 2 presents the schematic of the proposed down-conversion mixer tailored for 5G handheld devices. The design incorporates an RF Gm stage, LO buffer amplifier, switching stage, and transformer-based harmonic suppression to perform RF-to-IF conversion from 39 GHz to 11 GHz. Separating the Gm stage and switching stage enhances NF, CG, and linearity. Additionally, a double-balanced mixer topology is employed to improve LO rejection compared to single-balanced mixers. Transformer-based harmonic suppression is utilized to effectively reject unwanted harmonics, ensuring robust performance in 5G applications.

2.2. Transconductance Stage

The Gm stage employs a differential common source configuration with a capacitance neutralization technique [25]. The gate-to-drain parasitic capacitance (C_gd) degrades stability, power gain, and reverse isolation due to unwanted feedback. To mitigate this, the capacitance neutralization technique enhances stability, power gain, and LO-to-RF isolation, while improving the mixer’s NF by boosting the Gm stage’s gain.

The differential RF signal is applied to the switching stage via a differential amplifier comprising transformers (TF₁, TF₂) and a neutralization capacitor (C_N). Transformer, TF₁, along with inductors, L₁ and L₃, achieves simultaneous gain and noise matching, while TF₂ and inductor L₂ provide conjugate matching between the Gm and switching stages.

To optimize the design, a custom metal–oxide–metal (MOM) capacitor [25] replaces the standard foundry-provided MOM capacitor for C_N. This custom MOM capacitor utilizes a multi-stack metal plate design, reducing interconnections and chip area while improving the quality factor. Simulation results show minimal process variation (less than ±2%), ensuring consistent performance.

2.3. Switching Stage with Transformer-Based Harmonic Suppression

The switching stage consists of switching transistors (M₃–M₆) and transformer TF₃ with harmonic suppression. Figure 3 illustrates the three- and two-dimensional layout of the switching stage, designed for symmetry to minimize LO leakage and improve LO-to-RF isolation.

The layout ensures that the IF output is isolated from RF and LO signal lines using a grounded middle metal layer, while RF and LO signals are routed through the top two metal layers and top metal layer, respectively. This separation and symmetric layout prevent signal interference and enhance performance metrics such as LO leakage and RF-to-LO isolation.

Figure 4a illustrates a transformer model based on [26]. The transformer is represented as an ideal transformer with a turn ratio of 1:n/k, where the primary and secondary leakage inductances are modeled as series components with shunt inductors (1 − k²)L_P and k²L_P, respectively. Here, L_P is the inductance of the primary winding; R_P1 and R_P2 are the parasitic resistances of the primary and secondary windings, respectively; C_P1 and C_P2 are the parasitic capacitances, including the winding capacitance; k is the magnetic coupling coefficient, and n is the turn ratio ($\sqrt{L_S/L_P})$, where L_S is the inductance of the secondary winding.

Figure 4a–c depict the 3D layout of the transformer, its equivalent circuit model, and the matching network with harmonic suppression at the switching stage output. The source resistance (R_S) and (C_S) represent the impedance looking into the switching transistors from the drain side, with a source impedance of 88.5-j438.4 Ω at 11 GHz. Similarly, the load resistance (R_L) and capacitance (C_L) represent the impedance looking into the linearization stage, with a load impedance of 26.5-j107.1 Ω at 11 GHz. Incorporating harmonic suppression and the matching network improves the simulated insertion loss by 3.6 dB within the 10–12 GHz range, and the transformer demonstrates effective high-frequency harmonic suppression. Specifically, the insertion loss is measured at 3.9 dB, 6.3 dB, and 38.9 dB at 11 GHz (IF), 17 GHz (2f_LO-f_RF), and 28 GHz (LO frequency), respectively.

The transformer TF₃ is employed for differential-to-single conversion and is constructed using the top two metal layers for magnetic coupling. Its physical primary-to-secondary winding turn ratio is 3:2, with n = 0.71 and k = 0.85. The parasitic parameters include R_S1 = 7.5 Ω, R_S2 = 7 Ω, C_S1 = 40 fF, and C_S2 = 45 fF. To further optimize performance, inductors L₄–L₅ form a matching network that reduces insertion loss and rejects high-frequency components. Additionally, a shunt resonance circuit comprising L₆ and C₁ is employed for harmonic suppression and conjugate matching with L₇.

Figure 4d compares the insertion losses of transformers with and without harmonic suppression, highlighting the effectiveness of the proposed design. The primary unwanted signals of the down-conversion mixer are 2f_LO-f_RF, 2f_RF-2f_LO, and f_LO. The transformer with harmonic rejection improves suppression by 1 dB, 13 dB, and 31 dB at 17 GHz (2f_LO-f_RF), 22 GHz (2f_RF-2f_LO), and 28 GHz (f_LO), respectively.

2.4. LO Buffer Amplifier

Figure 5 illustrates the schematic of the proposed LO buffer amplifier [24]. The design incorporates a cascode current-steering variable gain amplifier and a common-source amplifier with a capacitance neutralization technique. The LO buffer amplifier ensures a constant and sufficiently high voltage swing for the mixer core across varying input power levels. To achieve this, it included a gain control function that maintained constant output power across all gain control states.

A conventional current-steering variable gain amplifier [27] adjusts gain by steering the current of the common gate transistor (M₂). However, it typically offers limited output power. To address this limitation and meet linearity requirements, the proposed design employs additional transistors (M₃–M₄) for 2 dB (BIT0) and 4 dB (BIT1) gain control, respectively, as shown in Figure 5. By steering the current through M₁, the design achieves variable gain while maintaining constant output power, driven by the stable current of M₂.

The differential common-source amplifier (M₅–M₆) with capacitance neutralization and transformers (TF₁–TF₂) enhances the LO buffer amplifier’s performance by providing high gain, improved linearity, and a well-balanced differential signal. This configuration minimizes gain and phase imbalances, reducing the linearity burden on the first stage.

The simulation results indicate that the proposed LO buffer amplifier achieves a power gain of 15–21 dB in 2 dB steps, with an output 1 dB compression point ranging from −1 dBm to 0.3 dBm. It delivers a 0.7-V_P-P LO signal to the switching stage’s gate from an LO input power of −20 dBm. Compared to the conventional current-steering variable gain amplifier, the proposed design demonstrates a 4 dB higher output 1 dB compression point in simulations.

The two bottom metal layers are utilized as a ground plane with a mesh pattern. The inductors, transformers, neutralization capacitors, and interconnections are all modeled and analyzed using the HFSS 3-D EM simulator developed by Ansys, Canonsburg, US. All transistors feature a gate length of 60 nm.

With transformer-based harmonic suppression and the separation of the Gm stage and switching stage, the proposed down-conversion mixer, illustrated in Figure 2, achieves a simulated CG of 5.2–6.4 dB and a NF of less than 7.3 dB over an RF frequency range of 37–41 GHz and an LO frequency range of 27–29 GHz. The mixer demonstrates an input third-order intercept point (IIP3) of 3.1 dBm, an NF of 6.1 dB, a LO-to-RF isolation exceeding 46 dB, and an IP1 dB of −6 dBm.

3. Results

The proposed down-conversion mixer circuit was implemented in a standard 65 nm CMOS technology. Figure 6 shows a chip photograph of the proposed down-conversion mixer. The chip occupies an area of 0.57 × 0.9 mm², excluding the pads. The mixer consumes 18 mW of DC power from a 1 V supply voltage, including the LO buffer amplifier’s power consumption of 11 mW. Figure 7 illustrates the measurement setups for S-parameters, CG, NF, and power-handling capability. The mixer’s performance was measured on-wafer using ground–signal–ground (GSG) and ground–signal–signal–ground (GSSG) probes. The S-parameters were measured using a Keysight E8361A vector network analyzer. The NF, CG, IP1dB, and IIP3 were measured with a noise figure analyzer, signal generators, and a spectrum analyzer. Losses from the probe tips, adapters, and coaxial cables were de-embedded from the raw measurement data.

Figure 8 shows the simulated and measured return losses of the proposed mixer. The measured return losses of the IF and LO ports exceed 10 dB over 8–14 GHz and 26–31 GHz, respectively. The measured return loss of the RF port is better than 8 dB over 36–41 GHz. For the 2-bit gain control in the LO buffer amplifier, the IF and RF ports show consistent return loss performance. Simulated data show good agreement with the measurement results. Figure 9 depicts the simulated and measured NFs of the mixer. The measured single-sideband NF is less than 7.3 dB over an RF frequency range of 37–41 GHz.

Figure 10 illustrates the simulated and measured CG of the mixer. The LO frequencies are 27 GHz, 28 GHz, and 29 GHz, while the RF frequency ranges are 37–38.25 GHz, 38.25–39.75 GHz, and 39.75–41 GHz, respectively. The RF and LO input powers are −30 dBm and −20 dBm, respectively. The measured conversion gain is 5.2–6.4 dB over an RF frequency range of 37–41 GHz. The neutralization capacitors and the separation of the Gm and switching stages contribute to enhanced gain and NF performance. Figure 11 shows the CG of the mixer for varying RF input power, with an LO input power of −20 dBm. The measured IP1dB of the mixer is −6 dBm at an RF frequency of 39 GHz.

Figure 12 presents the simulated and measured output third-order intercept point (OIP3) of the mixer. The measured OIP3 exceeds 9.6 dBm at an RF frequency of 39 GHz and remains above 8.9 dBm across the RF frequency range of 37–41 GHz. The measured IIP3 is greater than 3.1 dBm across the same frequency range. Simulated data show good agreement with the measurement results. Figure 13 illustrates the measured LO-to-RF and LO-to-IF isolations. LO leakage generates unwanted spurious signals by mixing with other harmonics, leading to degraded linearity and reduced signal quality. Therefore, minimizing LO leakage is crucial to maintaining optimal performance. The LO-to-RF isolation is better than 25.3 dB, while the LO-to-IF isolation exceeds 45.7 dB. Figure 14 shows the measured output spectrum. The measured harmonic suppression for an RF input power of −30 dBm is better than −26 dBc across an RF frequency range of 37–41 GHz, with the output spectrum accounting for cable loss.

4. Discussion

Table 1. Performance comparisons of state-of-the-art.

	This Work	[15]	[16]	[17]	[18]	[20]	[21]	[22]
Process	65 nm CMOS	65 nm CMOS	40 nm CMOS	65 nm CMOS	90 nm CMOS	55 nm CMOS	22 nm CMOS	55 nm CMOS
Topology	RF Gm + Switching Core	Gilbert-cell + IF Buffer	RF Gm + Switching Core + IF Buffer	RF Gm + Switching Core + IF Buffer	Gilbert-cell + IF Buffer	Switching Core + IF Buffer	Switching Core	MGTR Gilbert-cell
Frequency (GHz)	37–41	37–40	37–40	37–40	28	19–32.8	24–34	36–42
VDD (V)	1.0	1.0	1.1	1.0	0.5	1.6	0.8	1.2
CG (dB)	5.2–6.4	4.8	−4.1–1.2	3.1	12.6	−0.5	7.8	−14.4
NF (dB)	<7.3	13.5	12.4–13	11.4	10.6	-	16	16.75
LO Power (dBm)	−20	5	−10	5	0	2	−8	9
IP1dB (dBm)	−6	−5.9	−0.5	−11	-	8.2	−7	9.85
IIP3 (dBm)	3.1	0.7	4	−1.95	1.5	-	4.8	20.87
LO-RF Isolation (dB)	>46	-	-	-	37.1	45.3	>42	>32.7
PDC (mW)	18	10.3	28.3	6.2	4.5	15.2	1.28	26
Area (mm2)	0.51	0.4	0.654	0.3	0.529	0.63	0.243	1.47

compares the performance of state-of-the-art 5G FR2 CMOS down-conversion mixers. A 5G FR2 down-conversion mixer should achieve low power consumption, high conversion gain, low noise figure, and high linearity. However, these performance parameters inherently involve trade-offs, and state-of-the-art down-conversion mixers typically prioritize two or three key aspects. The mixer utilizing MGTR at the Gm stage [22] demonstrates a high IIP3 of 20.87 dBm but suffers from a high NF of 16.75 dB and a low CG of −14.4 dB. Similarly, the mixer in [18] achieves a high CG of 12.6 dB; however, it employs a direct-conversion architecture and an IF buffer amplifier, resulting in an NF exceeding 10 dB. The proposed mixer, which incorporates neutralization capacitors, a separate Gm stage and switching stage, simultaneous gain and noise matching, and transformer-based harmonic suppression, achieves a significantly lower NF of less than 7.3 dB and a high CG of 5.2–6.4 dB, all without the need for an IF buffer amplifier. Additionally, the LO-RF isolation exceeds 46 dB, and the harmonic suppression is better than −26 dBc. The measurement results indicate that the proposed mixer is well-suited for 5G low-power mm-wave handheld devices, offering a balanced trade-off between performance and power efficiency.

5. Conclusions

A 39 GHz down-conversion mixer circuit was successfully designed and implemented using standard 65 nm CMOS technology. By incorporating neutralization capacitors, a separate Gm stage and switching stage, simultaneous gain and noise matching, and transformer-based harmonic suppression, the proposed mixer achieves a low NF of less than 7.3 dB and a high CG of 5.2–6.4 dB, all without requiring an IF buffer amplifier. Moreover, the LO-RF isolation is better than 46 dB, and the harmonic suppression exceeds −26 dBc. The measurement results validate that the proposed mixer meets the performance requirements for 5G low-power mm-wave handheld devices. Its design demonstrates the feasibility of achieving high performance with low LO input power, making it a strong candidate for next-generation wireless communication systems.