Implementation of Boolean Logic Operations and Refresh Circuit for 2T DRAM-Based PIM Architecture

Round 1

Reviewer 1 Report

Comments and Suggestions for Authors

The manuscript presents a novel approach to implementing Boolean logic operations and refresh circuitry in a 2T DRAM-based processing-in-memory (PIM) architecture. The topic is timely and relevant, and the manuscript is well organized. I recommned acceptance after the following revision.

1. While the authors discuss a comprehensive functionality of 2T DRAM cells and arrays through simulations, the manuscript lacks a detailed analysis of reliability under realistic operating conditions. Issues such as retention time variability, process-induced variations, and temperature dependence are crucial for assessing the practical viability of the proposed architecture.
2. The manuscript would benefit from a clearer comparison with prior PIM implementations (e.g., SRAM-based or capacitor-less DRAM approaches). A quantitative performance/reliability trade-off table would help contextualize the proposed architecture within existing literature.
3. The effects of low-frequency noise on the 2T0C operation should be addressed: Advanced Science, vol. 12, no. 23, 2025, 2501367;  Chaos, Solitons & Fractals, 191, 2025, 115856.

Author Response

1. While the authors discuss a comprehensive functionality of 2T DRAM cells and arrays through simulations, the manuscript lacks a detailed analysis of reliability under realistic operating conditions. Issues such as retention time variability, process-induced variations, and temperature dependence are crucial for assessing the practical viability of the proposed architecture.

Author response: Thank you for your kind and deep-knowledgeable comments. 
Since 2T DRAM has not yet been physically fabricated and characterized, device-level properties such as reliability, retention time variability, process-induced variations, and temperature dependence were not considered. Instead, the fundamental characteristics of 2T DRAM were referenced from prior studies, and this work focused on developing and verifying methods for implementing read and computational operations in the 2T DRAM array.
Author action: We revised to feedback your opinion at script. We wrote in introduction that we concentrate on reading and basic logical operations.

2. The manuscript would benefit from a clearer comparison with prior PIM implementations (e.g., SRAM-based or capacitor-less DRAM approaches). A quantitative performance/reliability trade-off table would help contextualize the proposed architecture within existing literature.

Author response: Thank you for reviewing our manuscript and your detailed comments. We revealed that DRAM is suitable for PIM structure through comparison between SRAM and DRAM according to your opinion.
Author action: We revised to feedback your opinion at Introduction. We compared SRAM with DRAM and wrote that 2T DRAM is highly applicable to PIM through comparison between 1T DRAM and 2T DRAM within DRAM. In addition, by adding Table 1, SRAM, 1T DRAM, and 2T DRAM were compared through the table.

3. The effects of low-frequency noise on the 2T0C operation should be addressed: Advanced Science, vol. 12, no. 23, 2025, 2501367; Chaos, Solitons & Fractals, 191, 2025, 115856.

Author response: Thank you for your kind and deep-knowledgeable comments. With the same content as question 1, we conducted the study focusing on reading movements and basic logical operations rather than the characteristics of the 2T DRAM array.

Author Response File: Author Response.pdf

Reviewer 2 Report

Comments and Suggestions for Authors

The manuscript introduces a 2T-DRAM array capable of performing in-memory Boolean logic (OR, AND, XOR) and refresh operations. The motivation is clear, the array structure is well-explained. The simulation results verify the basic idea. However, I would like to raise some concerns for the paper to be accepted in a high-profile journal.

Technical Comments

1. The 2T-DRAM array performed AND and XOR operations by differentiating different RBL voltages after reading out 2 2T-DRAM cell. The signal margin is 0.4V, which is susceptible to transistor threshold voltage mismatch, process variations, and parasitic charge coupling. I would recommend the author performing more detailed simulation like Monte-Carlo simulation.
2. The AND, XOR and refresh operations includes DC current path , which undermines theenergy efficiency of 2T-DRAM PIM array and could be worse as the array scales. For example, the Feri circuit diagram for XOR operation has DC current from VDD to GND when RBL[0,0] or [1,1]. I would recommend the author provide the power consumption of these operations.
3. The output of refresh circuit in Figure 10 (a) shows clear steps which means the output can be maintained even the RBL voltage changes. While the refresh circuit is made by 3 pass gates, the output of these pass gates can be changed due to subthreshold leakage even a pass gate is turned off. I would recommend the author shows the detail of this simulation.

Minor Comments 

1. The output voltage of XOR operation in Table 1 is not corresponding to the voltage shown in Figure 8(b). 
2. The signal MBL & MWL shown in Figure 4(b) is used before definition.

Comments on the Quality of English Language

Some sentences have grammatical error like " Logic functionality was realized by modulating the gate voltage of the MOSFET bit line (MBL) connected to the RBL. " (151-152)

Author Response

Reviewer: 2

1. The 2T-DRAM array performed AND and XOR operations by differentiating different RBL voltages after reading out 2 2T-DRAM cell. The signal margin is 0.4V, which is susceptible to transistor threshold voltage mismatch, process variations, and parasitic charge coupling. I would recommend the author performing more detailed simulation like Monte-Carlo simulation.

Author response: Thank you for your detailed and deep-knowledgeable comments. Our study focused on implementing refresh characteristics for Boolean operation, XOR, and MAC operation. Through future research, we plan to consider various variables using Monte-Carlo simulation and then consider additional sensing margin.
Author action: We named figures about feedback your comments at conclusion. We wrote a plan to secure additional sensing margin through Monte-Carlo simulation.

2. The AND, XOR and refresh operations includes DC current path, which undermines the energy efficiency of 2T-DRAM PIM array and could be worse as the array scales. For example, the Feri circuit diagram for XOR operation has DC current from VDD to GND when RBL[0,0] or [1,1]. I would recommend the author provide the power consumption of these operations..

Author response: Thank you for your kind and detailed comments. Direct current flow from VDD to GND is inherent in distinguishing three states with intermediate levels between 0 and 1. The resulting power consumption increases proportionally with computation time. To address this, we aim to optimize current flow and reduce the stabilization time required for the voltage to settle at the intermediate state.
Author action: We revised feedback about your comments at XOR Boolean Operation Circuit section. We wrote the possibility of increasing power consumption and solutions for DC current.

3. The output of refresh circuit in Figure 10 (a) shows clear steps which means the output can be maintained even the RBL voltage changes. While the refresh circuit is made by 3 pass gates, the output of these pass gates can be changed due to subthreshold leakage even a pass gate is turned off. I would recommend the author shows the detail of this simulation.

Author response: Thank you for your kind and detailed comments. The refresh circuit does not always operate; it operates with the retention time or voltage change of the SN is detected. Therefore, when the gate path is turned off, the circuit output change due to the leakage current is minimized.
Author action: We revised feedback about your minor comments at Refresh Circuit for Multi-Bit. 

Minor comments1. The output voltage of XOR operation in Table 1 is not corresponding to the voltage shown in Figure 8(b).
Author response: Thank you for your detailed and deep-knowledgeable comments.
Author action: We fixed the voltage in Figure 8(b) and the XOR calculation voltage in the existing Table 1.
2. The signal MBL & MWL shown in Figure 4(b) is used before definition.
Author response: Thank you for your kind and detailed comments.
Author action: We revised feedback about your minor comments at 2T DRAM Cell Simulation Results of section. We defined signal MBL and MWL before Figure 4 (b).
Comments on the Quality of English Language 
Some sentences have grammatical error like " Logic functionality was realized by modulating the gate voltage of the MOSFET bit line (MBL) connected to the RBL. " (151-152)
Author response: Thank you for your kind and detailed comments.
Author action: We revised feedback on your grammatical comments at 183 lines.

Author Response File: Author Response.pdf

Reviewer 3 Report

Comments and Suggestions for Authors

Dear authors,

First, I would like to congratulate you for this piece of research work. Now the, in order to enhance your contribution I have some comments:

  - In the introduction I miss some better explanation about why do  you choose the 2T DRAM cell. There are other DRAM configurations that could present better performance. There are previous studies where a complete cell behavior comparison was done, which can help you to prove your cell selection. For instance,  [1] shows the impact on using different DRAM cell configurations with different device technology and their impact on the memory cell performance. 
[1] E. Amat, A. Calomarde, F. Moll, R. Canal, A. Rubio, Feasibility of Embedded DRAM Cells on FinFET Technology, IEEE Trans. Comput. 65 (2016) 1068–1074. https://doi.org/10.1109/TC.2014.2375204.

 - Another question is about the technology you have used to simulate your memory cell devices; have you used planar devices or FinFETs? In the previous contribution you  can also get the impact of device technology on memory cell behavior.

 - In order to enhance the retention time of your memory cell, have you regarded the use of different devices type (only pMOS or nMOS, and mixing pMOS and nMOS)?

 - Another device detail is their dimensions are not presented.

 - Typo error, you present in the  text some Figures and you put a point after the name Figure, I think you should remove it! lines: 45, 85, 99, 102, 110, 123, 125, 138, 154, 156, 170, 208, 214

 - Do you have analyzed the impact of having high environment temperature on the performance of your memory cell configuration? Which is the impact do  you presume that it will have it?

Author Response

Reviewer: 3

1. In the introduction I miss some better explanation about why do you choose the 2T DRAM cell. There are other DRAM configurations that could present better performance. There are previous studies where a complete cell behavior comparison was done, which can help you to prove your cell selection. For instance, [1] shows the impact on using different DRAM cell configurations with different device technology and their impact on the memory cell performance. 
[1] E. Amat, A. Calomarde, F. Moll, R. Canal, A. Rubio, Feasibility of Embedded DRAM Cells on FinFET Technology, IEEE Trans. Comput. 65 (2016) 1068–1074. https://doi.org/10.1109/TC.2014.2375204

Author response: Thank you for your kind and deep-knowledgeable comments. We compared the characteristics of memory with high applicability to PIM structures to explain why 2T DRAM cells are suitable for PIM structures.
Author action: We revised to feedback your opinion at Introduction. We compared SRAM with DRAM and wrote that 2T DRAM is highly applicable to PIM through comparison between 1T DRAM and 2T DRAM within DRAM. In addition, by adding Table 1, SRAM, 1T DRAM, and 2T DRAM were compared through the table.

2. Another question is about the technology you have used to simulate your memory cell devices; have you used planar devices or FinFETs? In the previous contribution you can also get the impact of device technology on memory cell behavior.

Author response: Thank you for reviewing our manuscript and your detailed comments. We constructed a 2T DRAM cell with the planar MOSFET provided by SILVACO and verified the basic operation and data storage of SN. This paper focused on implementing a refresh circuit for boolean and MAC operations within the 2T DRAM array. In future studies, we are planning to apply a FinFET structure with a relatively low off-loss current.

3. In order to enhance the retention time of your memory cell, have you regarded the use of different devices type (only pMOS or nMOS, and mixing pMOS and nMOS)?

Author response: Thank you for your kind and deep-knowledgeable comments. This study focused on the possibility of boolean operation within the 2T DRAM array and the design of a multi-bit refresh circuit for MAC operation rather than optimizing the 2T DRAM cell characteristics. One way to increase the retention time of 2T DRAM is to configure a 2T DRAM cell by mixing nMOS and pMOS, but in the latest research, IGZO is used to secure the retention time for channel materials.

4. Another device detail is their dimensions are not presented.

Author response: Thank you for reviewing our manuscript and your detailed comments. We used the planar MOSFET provided basically by SILVACO when implementing the 2T DRAM cell in the mixed mode of SILVACO. The characteristics of 2T DRAM will change according to the change in the parameters of MOSFET, but this paper did not focus on optimizing the characteristics of 2T DRAM cell. Based on this study, further studies will conduct a study to increase the retention time by optimizing the 2T DRAM cell through parameter change and applying the structure using IGZO as a channel material.

5. Typo error, you present in the text some Figures and you put a point after the name Figure, I think you should remove it! lines: 45, 85, 99, 102, 110, 123, 125, 138, 154, 156, 170, 208, 214.

Author response: Thank you for reviewing our manuscript and your detailed comments.
Author action: We revised to feedback your opinion at manuscripts. We removed the point after the figure text.

6. Do you have analyzed the impact of having high environment temperature on the performance of your memory cell configuration? Which is the impact do you presume that it will have it?

Author response: Thank you for your kind and deep-knowledgeable comments. We verified the basic operation and data storage of the SN in the 2T DRAM cell under room temperature conditions. It is expected that the retention time will decrease due to the increased mobility of electrons at higher temperatures than the room temperature. In the future, it is necessary to optimize the characteristics of the 2T DRAM cell by changing various parameters and environmental conditions to the 2T DRAM cell.

Author Response File: Author Response.pdf

Reviewer 4 Report

Comments and Suggestions for Authors

This paper focuses on the in-memory implementation of logic operations like AND and OR using 2t0C DRAM cell. For XOR, they propose an additional circuit. Lastly, they propose a refresh strategy to retain multi-level cell value, so the CIM MAC results are correct.

Major comments:

1. 2T0C model-related questions
   1. Please provide more details on the 2T0C DRAM cell model implemented in SILVACO mixed-mode. This is important for reproducing the results shown in Figures 4 and 5. More specifically, what type of transistor model did you use? Also, mention all transistor parameters in the appendix. As of now, the only detail I get is this "The 2T DRAM cell was implemented in SILVACO mixed-mode simulation using two MOSFETs". This is not at all sufficient.
   2. In your 2T0C cell model, did you consider all parasitic elements, including the wire cap and res? If yes, please mention the values. Are the results shown in Figures 4 and 5 for a single cell or for an array? I would advise you to show the results for an array with all parasitics like BL cap, BL RES, WL cap, WL RES, gate cap, etc.
   3. I advise the authors to extend Figure 5 with a cell leakage behavior as well. Furthermore, did you verify your model with any of the actual 2T0C cell behavior published in prior work?
   4. For the read operation, It would have been better if you also showed BL current vs SN value. For multi-level MAC, what gets accumulated on BL is the current and not the voltage. See fig 9 and 10 in https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10145946  . Also, the caption for Figure 5b, says "RBL voltage decreases under the influence of SN potential and the RWL", but the plot shows RWL with reduced voltage. Did you mix up the legend? 
   5. Overall, this section would benefit from additional results. As of now, the authors have not provided concrete proof that this model is close to the actual 2T0C cell design.
2. AND/OR implementation-related question (i.e. section 4.1):
   1. The novelty of this section is showing the AND/OR operation using 2T0C cell. But it is very similar to the previously published 1T1C cell results [a]. They have even verified on a real DRAM chip [b]. Compared to such work, this section has very limited novelty and results. Furthermore, other groups have published similar types with other memory technologies. Consider citing more related work and clearly highlighting how this work is different. 
      [a] V. Seshadri et al., "Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology," 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Boston, MA, USA, 2017, pp. 273-287.
      [b] Fei Gao, Georgios Tziantzioulis, and David Wentzlaff. 2019. ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-52). Association for Computing Machinery, New York, NY, USA, 100–113. https://doi.org/10.1145/3352460.3358260
   2. The authors say, "The OR operation is performed by applying high voltage to MBL". This will make the PMOS off, assuming Vpre is high voltage. With this PMOS being off, where is VRBL voltage coming from? It is connected to VPRE via PMOS and to gnd via read Tr and MWL Tr. Please clarify this. The easier way to do this was to use C1 node: OR if C1=fully charged (i.e., 1) and AND if C1=fully discharged (i.e., 0).
   3. In your AND operation results, for "11", the BL voltage is at 0.45 and the voltage gap is 0.4V. What type of sensing would you use here? Please mention the sensing threshold. The reason for asking this is that the "10" and "01" results for XOR has RBL voltage of 0.2, but a gap of 0.4. You might need a reconfigurable reference voltage for the sense amplifier. Please address this point for better clarity for the readers.
3. XOR-related question
   1. The new circuit shown in Figure 8a, is it required per cell or common for the entire column? 
   2. The RBL is connected only to the gate of this new circuit. Firstly, how did you see low RBL voltage for "10" and "01" in figure 8b? What changes did you make to make RBL voltage different from OR or AND? Did you change anything in MBL voltage? There are a lot of circuit details missing here. 
4. Refresh related question:
   1. Figure 10a, for RBL value of 0.2-0.3, the SN value is refreshed to 0.9-1V. Is it negating the values? Please show the original SN value and the post-refresh SN value.
   2. This circuit requires varied-width transistors. Have the authors verified with transistor variation? Without a Monte-Carlo simulation, it is hard to verify if this circuit is realistic. The result shown in Figure 10 might not be as good as Figure 10 once you consider all non-idealities. 
   3. I suggest that the authors verify the same circuit with the transistors provided by the technology vendors. 
   4. Is this additional circuit common for the whole column within an array, or required for each cell.  
   5. What advantage does this circuit bring compared to the existing refresh strategy? please elaborate on this 
5. Common for all: The authors have to present the area overhead results and the reduction of memory density

Please cite:
A. Belmonte et al. Tailoring IGZO-TFT architecture for capacitorless DRAM, demonstrating >10³s retention, >10¹¹ cycles endurance and L_g scalability down to 14nm. 2021 IEEE International Electron Devices Meeting.

Minor comments:

1. Figure 2: Mark the resistor as a parasitic wire resistor
2. Figure 2: Mark the write tr as an extremely low leakage IGZO transistor
3. Figure 2: Show or mention that the node SN uses the parasitic cap for storage. mainly gate cap of read tr
4. Figure 4: Vpre color in legend (light blue) does not match the waveform color (dark blue)
5. Figure 4: read plot, the legend shows MWL signal, but it's not present in the circuit.

Author Response

Reviewer: 4

2T0C model-related questions
1. Please provide more details on the 2T0C DRAM cell model implemented in SILVACO mixed-mode. This is important for reproducing the results shown in Figures 4 and 5. More specifically, what type of transistor model did you use? Also, mention all transistor parameters in the appendix. As of now, the only detail I get is this "The 2T DRAM cell was implemented in SILVACO mixed-mode simulation using two MOSFETs". This is not at all sufficient.
Author response: Thank you for your kind and deep-knowledgeable comments.  We will explain the MOSFET model conditions constituting the 2T DRAM cell by adding a table as we believe that it is necessary to explain in detail.
Author action: We revised to feedback your opinion at 2T DRAM Cell Simulation Results. We further described the conditions of the MOSFET model constituting the 2T DRAM cell by adding table 2.

2. In your 2T0C cell model, did you consider all parasitic elements, including the wire cap and res? If yes, please mention the values. Are the results shown in Figures 4 and 5 for a single cell or for an array? I would advise you to show the results for an array with all parasitics like BL cap, BL RES, WL cap, WL RES, gate cap, etc.

Author response: Thank you for reviewing our manuscript and your detailed comments. We implemented a 2T DRAM cell and verified the possibility of storing data in the read and write operations and SN. At this time, the parasitic resistance that may occur in the actual 2T DRAM was not considered. Our research purpose focused on the proposal of a refresh circuit for Boolean and MAC operations within the 2T DRAM array. In future research, through the process of optimizing the characteristics of the 2T DRAM cell, the elements that appear in the actual process will be implemented in consideration of parasitic resistance and parasitic capacitance.  In addition, figures 4 and 5 are to verify the read and write operation of 2T DRAM cells and the possibility of storing data in the SN.

3. I advise the authors to extend Figure 5 with a cell leakage behavior as well. Furthermore, did you verify your model with any of the actual 2T0C cell behavior published in prior work?

Author response: Thank you for your kind and deep-knowledgeable comments. We are planning a study to improve 2T DRAM performance by optimizing the characteristics of 2T DRAM cells. In this paper, we verified whether 2T DRAM cells can play a role as memory. 2T DRAM is volatile memory and there is a possibility that SN data will be lost through leakage current. To solve this problem, we are planning to minimize the leakage current by using IGZO of channel material.
Author action: We named figures about feedback your comments at conclusion. Our future research plans have been additionally drawn up.

4. For the read operation, It would have been better if you also showed BL current vs SN value. For multi-level MAC, what gets accumulated on BL is the current and not the voltage. See fig 9 and 10 in https://ieeexplore.ieee.org/stamp/stamp.jsp?tp=&arnumber=10145946  . Also, the caption for Figure 5b, says "RBL voltage decreases under the influence of SN potential and the RWL", but the plot shows RWL with reduced voltage. Did you mix up the legend?

Author response: Thank you for reviewing our manuscript and your detailed comments. We showed the precharging operation and the read operation through Figure 5(b). It is essential to apply the voltage of RWL to access the selected 2T DRAM cell during the read operation. Therefore, the voltages of RBL and RWL are shown in Figure 5(b). In addition, Figures 5(a) and (b) represent the results of storing data 1 and performing the read operation.

5. Overall, this section would benefit from additional results. As of now, the authors have not provided concrete proof that this model is close to the actual 2T0C cell design.

Author response: Thank you for your kind and deep-knowledgeable comments. We revealed that DRAM is suitable for PIM structure through comparison between SRAM and DRAM according to your opinion.
Author action: We revised to feedback your opinion at Introduction. We compared SRAM with DRAM and wrote that 2T DRAM is highly applicable to PIM through comparison between 1T DRAM and 2T DRAM within DRAM. In addition, by adding Table 1, SRAM, 1T DRAM, and 2T DRAM were compared through the table.

AND/OR implementation-related question (i.e. section 4.1)
1. The novelty of this section is showing the AND/OR operation using 2T0C cell. But it is very similar to the previously published 1T1C cell results [a]. They have even verified on a real DRAM chip [b]. Compared to such work, this section has very limited novelty and results. Furthermore, other groups have published similar types with other memory technologies. Consider citing more related work and clearly highlighting how this work is different. [a] V. Seshadri et al., "Ambit: In-Memory Accelerator for Bulk Bitwise Operations Using Commodity DRAM Technology," 2017 50th Annual IEEE/ACM International Symposium on Microarchitecture (MICRO), Boston, MA, USA, 2017, pp. 273-287.[b] Fei Gao, Georgios Tziantzioulis, and David Wentzlaff. 2019. ComputeDRAM: In-Memory Compute Using Off-the-Shelf DRAMs. In Proceedings of the 52nd Annual IEEE/ACM International Symposium on Microarchitecture (MICRO-52). Association for Computing Machinery, New York, NY, USA, 100–113. https://doi.org/10.1145/3352460.3358260

Author response: Thank you for your kind and deep-knowledgeable comments. We performed OR and AND operations through the gate voltage of the MBL constituting the 2T DRAM array without using an additional circuit. This is a big advantage in terms of density of 2T DRAM. In addition, if OR and AND operations are selected according to the gate voltage of the MBL, the preliminary work to select the boolean operation is unnecessary.
Author action: We revised to feedback your opinion at 2T DRAM Array with Boolean Operation. We additionally wrote about the advantages of the proposed OR and AND operations.

2. The authors say, "The OR operation is performed by applying high voltage to MBL". This will make the PMOS off, assuming Vpre is high voltage. With this PMOS being off, where is VRBL voltage coming from? It is connected to VPRE via PMOS and to gnd via read Tr and MWL Tr. Please clarify this. The easier way to do this was to use C1 node: OR if C1=fully charged (i.e., 1) and AND if C1=fully discharged (i.e., 0).

Author response: Thank you for reviewing our manuscript and your detailed comments. We formed the voltage of the RBL through the precharging operation on the RBL before the OR operation. After that, if the 2T DRAM cell is multiple-selected and OR operation is performed, the voltage of the precharged RBL decreases in the remaining data states except for the data [0,0].

3. In your AND operation results, for "11", the BL voltage is at 0.45 and the voltage gap is 0.4V. What type of sensing would you use here? Please mention the sensing threshold. The reason for asking this is that the "10" and "01" results for XOR has RBL voltage of 0.2, but a gap of 0.4. You might need a reconfigurable reference voltage for the sense amplifier. Please address this point for better clarity for the readers.

Author response: Thank you for your kind and deep-knowledgeable comments. A sense amplifier is required to clearly distinguish between the AND and XOR operations. To enable the use of a single sense amplifier, the sensing threshold is set to approximately 0.5 V. However, considering the sensing margin, since the RBL voltage after the AND operation of data [1,1] is about 0.4 V, the AND operation must be optimized to reduce the RBL voltage to below 0.4 V in this case.
Author action: We revised feedback to your opinion at 2T DRAM Array with Boolean Operation. We additionally wrote about the necessity of the sense amplifier and the sensing threshold condition.

XOR-related question
1. The new circuit shown in Figure 8a, is it required per cell or common for the entire column? 

Author response: Thank you for reviewing our manuscript and your detailed comments. 2T DRAM cell is multiple-selected to read the stored data and XOR operation is performed. Therefore, the proposed XOR operation is necessary in common throughout the entire column.

2. The RBL is connected only to the gate of this new circuit. Firstly, how did you see low RBL voltage for "10" and "01" in figure 8b? What changes did you make to make RBL voltage different from OR or AND? Did you change anything in MBL voltage? There are a lot of circuit details missing here. 

Author response: Thank you for your kind and deep-knowledgeable comments. Figure 8 (b) is designed as a circuit for XOR operation. The OR and AND operation were performed by changing the state of the PMOSFET through the voltage change of the MBL and MBL in the 2T DRAM array. However, the XOR operation was difficult to operate within the 2T DRAM array, requiring an additional XOR circuit configuration. Therefore, a circuit capable of XOR operation was proposed by constructing a circuit with three MOSFETs and adjusting each Vth and width.
 Refresh related question
1. Figure 10a, for RBL value of 0.2-0.3, the SN value is refreshed to 0.9-1V. Is it negating the values? Please show the original SN value and the post-refresh SN value.

Author response: Thank you for your kind and deep-knowledgeable comments. Even as the RBL voltage gradually varies under the influence of the SN voltage, the output of the multi-bit refresh circuit must remain fixed within a defined range. As shown in Fig. 10(b), while the RBL voltage shifts from 0.292 V to 0.343 V, the output of the refresh circuit remains constant at 1V.

2. This circuit requires varied-width transistors. Have the authors verified with transistor variation? Without a Monte-Carlo simulation, it is hard to verify if this circuit is realistic. The result shown in Figure 10 might not be as good as Figure 10 once you consider all non-idealities. 

Author response: Thank you for your kind and deep-knowledgeable comments. We also think that there is a possibility that the characteristics of the 2T DRAM array and the output of the proposed circuit may change due to parasitic resistance and parasitic capacitors. In future studies, we will provide guidelines for predicting changes in 2T DRAM array characteristics and process distribution through Monte-Carlo simulation techniques.
Author action: We revised feedback to your opinion at conclusion. We wrote a plan to secure additional transistor variation through Monte-Carlo simulation.

3. I suggest that the authors verify the same circuit with the transistors provided by the technology vendors. 

Author response: Thank you for reviewing our manuscript and your detailed comments. This study investigates the potential of 2T DRAM cells as memory elements and focuses on the design of multi-bit refresh circuits for Boolean and MAC operations in PIM architecture. Future work will optimize 2T DRAM cell characteristics through Monte Carlo simulations, with the goal of implementing the 2T DRAM array in fabricated processes.

4. Is this additional circuit common for the whole column within an array, or required for each cell.  

Author response: Thank you for your kind and deep-knowledgeable comments. The multi-bit refresh circuit is essential for storing multiple bits in the SN of a 2T DRAM cell. Consequently, each cell requires the multi-bit refresh circuit.

5. What advantage does this circuit bring compared to the existing refresh strategy? please elaborate on this 

Author response: Thank you for your kind and deep-knowledgeable comments. The refresh circuit employed in conventional 1T-1C DRAM is designed to rewrite single-bit data and is unsuitable for multi-bit storage. To address this, we propose a circuit capable of performing multi-bit refresh operations. The proposed design achieves multi-bit refresh functionality using only three MOSFETs, preserving the potential for high-density 2T DRAM arrays in future implementations.

Common for all: The authors have to present the area overhead results and the reduction of memory density
Author response: Thank you for reviewing our manuscript and your detailed comments. The objective of this research is to enhance the integration density of 2T DRAM by designing each cell with an area smaller than 6F². Furthermore, the peripheral circuits responsible for Boolean operations and multi-bit refresh in the 2T DRAM array are implemented using a minimal number of MOSFETs, thereby supporting higher integration density.
 Minor comments1. Figure 2: Mark the resistor as a parasitic wire resistor
Author response: Thank you for your detailed and deep-knowledgeable comments.
Author action: We changed the resistance to parasitic resistance in Figure 2(a).
2. Figure 2: Mark the write tr as an extremely low leakage IGZO transistor
Author response: Thank you for your kind and detailed comments. 
Author action: We changed the write Tr to write IGZO Tr in Figure 2(a).

3. Figure 2: Show or mention that the node SN uses the parasitic cap for storage. mainly gate cap of read tr
Author response: Thank you for your detailed and deep-knowledgeable comments.
Author action: We revised feedback about your minor comments at Figure 2 (a) caption. We wrote that we store data using Read Tr's gate capacitance.
.
4. Vpre color in legend (light blue) does not match the waveform color (dark blue)
Author response: Thank you for your kind and detailed comments.
Author action: We changed the Vpre graph color and legend's Vpre color equally in Figure 4(b).
5. read plot, the legend shows MWL signal, but it's not present in the circuit.
Author response: Thank you for your detailed and deep-knowledgeable comments. The MWL is connected to the gate of the MOSFET associated with the RWL to enable read operations, while the MBL is connected to the gate of the MOSFET associated with the RBL to perform precharging operations. This configuration is illustrated in detail in Figure 6. Note that Figure 2(a) depicts a 2T DRAM cell, so the MOSFETs described above are not shown in that diagram.

Author Response File: Author Response.pdf

Round 2

Reviewer 1 Report

Comments and Suggestions for Authors

Even though the devices are not physically demonstrated, the authors should consider the reliability issues in the proposed methodology. How the proposed methods can cause additional or solve the reliability issues in their discussion. Unless this point is addressed, the manuscript cannot be accepted.

Author Response

1. Even though the devices are not physically demonstrated, the authors should consider the reliability issues in the proposed methodology. How the proposed methods can cause additional or solve the reliability issues in their discussion.

Author response: Thank you for your kind and deep-knowledgeable comments.

We added the retention time of the 2T DRAM cell to the paper considering the reliability problem. The measurement of the voltage drop of SN in the room temperature (300k) resulted in a retention time of 2.59s.

Author action: We revised to feedback your opinion at 2T DRAM Cell Simulation Results. We wrote additional retention times for SN in consideration of reliability issues

Reviewer 2 Report

Comments and Suggestions for Authors

The ahuthors addressed most of my comments.

Only one remaining comment is the output voltage of XOR operation in Table 3 is not corresponding to the voltage shown in Figure 8(b). The output voltage should be 0.6V for [1,1], 0.2V for [0,1] and [1,0].

Author Response

1. Only one remaining comment is the output voltage of XOR operation in Table 3 is not corresponding to the voltage shown in Figure 8(b). The output voltage should be 0.6V for [1,1], 0.2V for [0,1] and [1,0].

Author response: Thank you for your kind and detailed comments. Thank you for finding our mistake.

Author action: We named figures about feedback your comments at Table 3. We fixed [1,1] to 0.6 V and [1,0] and [0,1] to 0.2 V.

 

Reviewer 4 Report

Comments and Suggestions for Authors

After carefully reviewing the revised manuscript and the authors’ response, I find that the paper still requires significant improvements before it can be considered for publication. While the proposed concept is interesting, the current version lacks sufficient technical rigor and validation. My major concerns are summarized below:

Major Weaknesses:

1. The authors mention that the refresh circuit is required per cell. This effectively makes the cell consist of 5 transistors (2T0C cell + 3 for refresh). Such an implementation will severely impact the density and area of the memory array, especially since the refresh transistors require different widths. The authors need to clearly quantify this area overhead and discuss the implications for scalability.

2. The manuscript does not provide any quantitative analysis of area, energy, or latency. These results are missing for both refresh and logic-in-memory operations. Without these results, it is difficult to evaluate the practical viability of the proposed scheme. These metrics are critical for the Electronics Journal.

3. For the logic-in-memory operations like OR,AND, XOR, the authors don't compare against other similar prior work. Even though the prior work might be for another DRAM type. It is important to quantitatively compare the results in terms of latency, energy, and area. 

4. Many multi-level 2T0C DRAM arrays have already been reported. In such arrays, the refresh starts with reading the stored multi-level value first and then rewritten to restore the charge. This does not require any additional circuit for refresh. A detailed comparison and benchmarking against the prior multi-level refresh scheme is mandatory and missing in this work.   

5. The related work section is missing. The manuscript must cite and discuss prior works that have demonstrated logic-in-memory operations within memory arrays and multi-level refresh. 
6. The response states that parasitic capacitance will be considered in future work. If that's the case, how was data stored in your 2T0C cell? In such a cell, the data is stored as charge in the parasitic capacitor at node SN. What was the capacitor value at SN?

7. The response states that parasitic capacitance will be considered in future work, yet the authors mention precharging of wires (RBL) for the OR operation. The authors must clarify: which capacitor is being precharged? Furthermore, precharging requirements should be explicitly mentioned in the paper.

8. The paper states: “Figure 7(b) shows that the RBL voltage decreased for all states except [1,1], thereby confirming AND logic functionality.” However, the figure shows the opposite—only [0,0] does not exhibit reduced RBL voltage. This discrepancy must be corrected. Additionally, for the AND operation, is any precharging required? If yes, this must be clarified.

9. The authors show their logic-in-memory and refresh operation with a 1um transistor, which is very large. Please use the latest technology. if you don't have access to the latest technology, use open-source PTM model cards for the latest technology.

10. The proposed 2T0C model appears to be based on ideal transistors and does not use any model cards from the technology providers. Several works (e.g., IGZO-based 2T0C DRAM with 56 levels [b]) have already demonstrated silicon-proven results. Merely showing a refresh mechanism with an idealized cell is insufficient. It is critical that the authors first demonstrate their model’s alignment with silicon-proven 2T0C DRAM before extending it to refresh operations. Postponing Monte Carlo and variation analysis to “future work” is not acceptable for a journal-level submission; realistic results including variations and parasitics must be included.
    [b] https://www.science.org/doi/10.1126/sciadv.adu4323

Other Comments:

1. You have a section called "7. Patents", but it's empty.
2. Please give details about your experimental setup - which simulation tool did you use, which transistor model card did you employ, and other related details?

Author Response

1. The authors mention that the refresh circuit is required per cell. This effectively makes the cell consist of 5 transistors (2T0C cell + 3 for refresh). Such an implementation will severely impact the density and area of the memory array, especially since the refresh transistors require different widths. The authors need to clearly quantify this area overhead and discuss the implications for scalability.

Author response: Thank you for your kind and deep-knowledgeable comments.  The refresh circuit we proposed is not added to each cell, but is a structure in which one refresh circuit is connected to one bit line. Therefore, the area of the refresh circuit is not considered in the cell area.

2. The manuscript does not provide any quantitative analysis of area, energy, or latency. These results are missing for both refresh and logic-in-memory operations. 

Author response: Thank you for reviewing our manuscript and your detailed comments. The proposed 2T DRAM consists of two transistors per cell, exhibiting energy characteristics comparable to SRAM. In addition, the latency time during logical operations was measured to be 30 ns, defined as the interval between the initiation of the XOR circuit operation and the stabilization of the RBL voltage.

Author action: We revised to feedback your opinion at XOR Boolean Operation Circuit. We additionally wrote about the latency of the proposed XOR operations.

3. For the logic-in-memory operations like OR,AND, XOR, the authors don't compare against other similar prior work. Even though the prior work might be for another DRAM type. It is important to quantitatively compare the results in terms of latency, energy, and area. 

Author response: Thank you for your kind and deep-knowledgeable comments. We compared previous studies implementing PIM with different memory technologies in terms of the latency during logical operations. The latency in the 2T DRAM-based PIM structure is lower than that observed in DRAM- and Flash-based PIM architectures. Although its latency is higher than that of RRAM- and FeFET-based PIM structures, the 2T DRAM-based PIM offers a significant advantage in terms of endurance.

Author action: We named figures about feedback your comments at conclusion. We made a latency comparison of other memory-based PIM structures with implementation papers.

4. Many multi-level 2T0C DRAM arrays have already been reported. In such arrays, the refresh starts with reading the stored multi-level value first and then rewritten to restore the charge. This does not require any additional circuit for refresh. A detailed comparison and benchmarking against the prior multi-level refresh scheme is mandatory and missing in this work.

Author response: Thank you for reviewing our manuscript and your detailed comments. In previous 2T0C DRAM designs, multi-level refresh was not considered. During a refresh operation, it is necessary to read the stored SN value for each cell and then rewrite it, which results in significant time and power consumption. In contrast, conventional 1T1C DRAM performs refresh concurrently with reading each cell’s data. Similarly, the structure proposed in this study enables refresh to occur simultaneously with the read operation of stored data.

 

5. The related work section is missing. The manuscript must cite and discuss prior works that have demonstrated logic-in-memory operations within memory arrays and multi-level refresh.

Author response: Thank you for your kind and deep-knowledgeable comments. We compared previous studies implementing PIM with different memory technologies, evaluating the latency of logical operations in the proposed 2T DRAM-based PIM structure. Additionally, there are few studies that report circuits implementing multi-level refresh operations, limiting available references.

Author action: We named figures about feedback your comments at conclusion. We made Table 4 and compared the latency.

6. The response states that parasitic capacitance will be considered in future work. If that's the case, how was data stored in your 2T0C cell? In such a cell, the data is stored as charge in the parasitic capacitor at node SN. What was the capacitor value at SN?

Author response: Thank you for your kind and deep-knowledgeable comments. Considering the parasitic capacitance between the drain of the write transistor and the gate of the read transistor, the SN in the 2T DRAM was modeled as 10 fF for the simulation.

Author action: We revised to feedback your opinion at 2T DRAM Cell Simulation Results. We additionally showed about the parasitic capacitor at Figure 4 (a).

 

7. The response states that parasitic capacitance will be considered in future work, yet the authors mention precharging of wires (RBL) for the OR operation. The authors must clarify: which capacitor is being precharged? Furthermore, precharging requirements should be explicitly mentioned in the paper.

Author response: Thank you for reviewing our manuscript and your detailed comments. Prior to the read operation, the RBL voltage is precharged to 1 V. Subsequently, the data stored in the 2T DRAM cell is accessed through the read operation, and the data state is determined by the resulting voltage variation on the RBL.

 

8. The paper states: “Figure 7(b) shows that the RBL voltage decreased for all states except [1,1], thereby confirming AND logic functionality.” However, the figure shows the opposite—only [0,0] does not exhibit reduced RBL voltage. This discrepancy must be corrected. Additionally, for the AND operation, is any precharging required?

Author response: Thank you for your kind and deep-knowledgeable comments. The RBL voltage remains stable for all states except [1,1]. Since the [1,0] and [0,0] states differ by 0.4 V after the AND operation, the two states can be clearly distinguished. Also, the precharge operation is required for AND operation. This part was written in the paper.

Author action: We revised feedback to your opinion at 2T DRAM Array with Boolean Operation. We have rewritten the description of the AND operation. In addition, we further wrote that after performing the precharge operation, we operate the logical operation.

 

9. The authors show their logic-in-memory and refresh operation with a 1um transistor, which is very large. Please use the latest technology.

Author response: Thank you for reviewing our manuscript and your detailed comments. We applied the basic BSIM4 model, which provides the transistor model in PSPCIE, and implemented the simulation by adding the parasitic capacitor in consideration of the 0.13um technology node.

Author action: We revised feedback to your opinion at 2T DRAM Cell Simulation Results. We added that we referred to the BSIM 4 model of PSPICE when implementing 2T DRAM cell.

10. The proposed 2T0C model appears to be based on ideal transistors and does not use any model cards from the technology providers. 

Author response: Thank you for your kind and deep-knowledgeable comments. Although a detailed analysis of the intrinsic 2T DRAM characteristics is important, these have been extensively studied in prior research, as the reviewer noted. The primary contribution of this work lies in developing methods for simultaneous reading and computation—an aspect not previously addressed—and for resolving multi-level refresh behavior, which has not yet been solved. This paper presents these methods and validates the effectiveness of the proposed approaches.

 

11. You have a section called "7. Patents", but it's empty.

Author response: Thank you for your kind and deep-knowledgeable comments.  We will explain the MOSFET model conditions constituting the 2T DRAM cell by adding a table as we believe that it is necessary to explain in detail.

Author action: We revised to feedback your opinion at manuscript. We deleted 7. Patent section from this paper.

 

12. Please give details about your experimental setup - which simulation tool did you use, which transistor model card did you employ, and other related details?

Author response: Thank you for reviewing our manuscript and your detailed comments. We implemented 2T DRAM cell through mixed-mode provided by SLIVACO. Also, 2T DRAM cell was implemented by referring to PSPICE's basic BSIM 4 model.

Round 3

Reviewer 1 Report

Comments and Suggestions for Authors

The paper can now be accepted.

Author Response

1. The paper can now be accepted.

Author response: Thank you for your kind and deep-knowledgeable comments.

Reviewer 4 Report

Comments and Suggestions for Authors

The quantitative analysis of this paper still lacks many critical results. 

Major comments: there are still many quantitative results missing

1. In my previous review I requested the authors to add energy, latency, and area. However, the authors only added latency table but the energy and area table is totally missing. It is important to show the following
   1. Energy of OR, AND XOR and Refresh operation
   2. Area overhead of the entire array due to additional transistor for refresh and XOR. The area overhead should be in um^2 as your design has transistor of varied length.  
   3. Important: for both 1..1 and 1.2 evaluation, please clearly mention the methods used for your energy and area evaluation.
2. The authors in their response mention that the previous work did not consider "During a refresh operation, it is necessary to read the stored SN value for each cell and then rewrite it, which results in significant time and power consumption." This need to be proved quantitively with actual latency and energy required for your approach vs read and rewrite refresh approach. Without this quantitative analysis how can readers know which approach is better.
3. The authors mention that SN parasitic capacitance was modeled at 10 fF for their 2T0C cell. How did you come to this number. For your reference the 1T1C DRAM cell in latest DRAM technology is 10fF (https://www.techinsights.com/blog/dram-scaling-trend-and-beyond). Its strange that your 2T0C cell that rely on gate parasitic capacitance is assumed to be 10fF. As per this work https://www.science.org/doi/10.1126/sciadv.adu4323 the SN cap is 3.9fF. The authors should re-evaluate all results with this cap value. 
4. The retention time of 2.9s will reduce if you use the 3.9fF SN cap. Right now your cap is 2.5 times larger.
5. This work showed https://www.science.org/doi/10.1126/sciadv.adu4323 2T0C cell with 56 levels. Will your refresh circuit work for large number of multi-levels? Please show that your refresh circuit will work for at least 16 levels. In your approach you only showed for three levels.  Without this proof, the proposed approach can't be confirmed. 
6. The authors did not fully address my previous review comment 7. I asked for the RBL wire capacitance value, but the authors mention precharge voltage. 
7. The authors mention that they use BSIM4 transistor model from 130nm tech. These transistor are not ideal for 2T0C cells as they have high leakage. Since the authors have not made full parasitic analysis, the results might not be accurate. They should make the fully leakage analysis.
8. Normally, 2T0C cell use IGZO transistor for low leakage. I recommend authors to use IGZO transistor model. 
9. The authors say that they use "basic BSIM 4", have the authors verified that this model is suitable for 2T0C DRAM cell. Typically, DRAM cell transistors are optimized for extremely low leakage, whose transistor performance will be very different for the BSIM4 model. This might directly influence the latency.
10. For my previous review comment 10 the authors mention "Although a detailed analysis of the intrinsic 2T DRAM characteristics is important, these have been extensively studied in prior research, as the reviewer noted. The primary contribution of this work lies in developing methods for simultaneous reading and computation—an aspect not previously addressed—and for resolving multi-level refresh behavior, which has not yet been solved. This paper presents these methods and validates the effectiveness of the proposed approaches." But validating this contribution with a model close to realistic 2T0C cell is important. I feel the authors have demonstrated their work with simple model with older technology transistor and missing parasitic analysis in many places. This is the main weakness of this paper.

Author Response

Thank you very much for the kind review comments